Merge branch 'refs/heads/master' into fork/verylowfreq/pr-ch32v-usbfs-host

author: hathach <[email protected]> 2025-07-04 09:49:28 +0700
committer: hathach <[email protected]> 2025-07-04 09:49:28 +0700
commit: 1b5f97ff23776279a011e2ab14a85f29e1aa6c10 (patch)
tree: 0328289336a2b135cd8455dab70dd9bd77737590 /hw
parent: cd2b3a53217857930bd8519d074b355ae8933982 (diff)
parent: 9d872d529ffa0aa53e735b24543c26156798fc64 (diff)
203 files changed, 10394 insertions, 2693 deletions
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json
index fee8f2c97..24da362da 100644
--- a/hw/bsp/BoardPresets.json
+++ b/hw/bsp/BoardPresets.json
@@ -13,20 +13,30 @@
       }
     },
     {
+      "name": "default single",
+      "hidden": true,
+      "description": "Configure preset for the ${presetName} board",
+      "generator": "Ninja",
+      "binaryDir": "${sourceDir}/build/${presetName}",
+      "cacheVariables": {
+        "BOARD": "${presetName}"
+      }
+    },
+    {
       "name": "adafruit_clue",
       "inherits": "default"
     },
     {
       "name": "adafruit_feather_esp32_v2",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "adafruit_feather_esp32s2",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "adafruit_feather_esp32s3",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "adafruit_magtag_29gray",
@@ -34,7 +44,7 @@
     },
     {
       "name": "adafruit_metro_esp32s2",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "apard32690",
@@ -130,39 +140,39 @@
     },
     {
       "name": "espressif_addax_1",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_c3_devkitc",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_c6_devkitc",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_kaluga_1",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_p4_function_ev",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_s2_devkitc",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_s3_devkitc",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_s3_devkitm",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "espressif_saola_1",
-      "inherits": "default"
+      "inherits": "default single"
     },
     {
       "name": "f1c100s",
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 0e0fa4ac6..1ba5a1b9d 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -60,17 +60,29 @@ int sys_read(int fhdl, char *buf, size_t count) {
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
 }
-
 #endif
 
 #elif defined(LOGGER_SWO)
+
+#define ITM_BASE 0xE0000000
+#define ITM_STIM0 (*((volatile uint8_t*)(ITM_BASE + 0)))
+#define ITM_TER *((volatile uint32_t*)(ITM_BASE + 0xE00))
+#define ITM_TCR *((volatile uint32_t*)(ITM_BASE + 0xE80))
+
+#define ITM_TCR_ITMENA (1 << 0)
+
 // Logging with SWO for ARM Cortex-M
 int sys_write (int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
 
-  for(size_t i=0; i<count; i++) {
-    ITM_SendChar(buf8[i]);
+  if ((ITM_TCR & ITM_TCR_ITMENA) && (ITM_TER & 1ul)) {
+    for(size_t i=0; i < count; i++) {
+      while (!(ITM_STIM0 & 1ul)) {
+        asm("nop");
+      }
+      ITM_STIM0 = buf8[i];
+    }
   }
 
   return (int) count;
@@ -136,6 +148,9 @@ int board_getchar(void) {
   return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
 }
 
+void board_putchar(int c) {
+  sys_write(0, (const char*)&c, 1);
+}
 
 uint32_t tusb_time_millis_api(void) {
   return board_millis();
@@ -144,7 +159,7 @@ uint32_t tusb_time_millis_api(void) {
 //--------------------------------------------------------------------
 // FreeRTOS hooks
 //--------------------------------------------------------------------
-#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF
+#if CFG_TUSB_OS == OPT_OS_FREERTOS && !defined(ESP_PLATFORM)
 #include "FreeRTOS.h"
 #include "task.h"
 
@@ -226,5 +241,4 @@ void vApplicationSetupTimerInterrupt(void) {
 }
 #endif
 
-
 #endif
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 9cdbbf0d3..328fe9363 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -41,7 +41,7 @@ extern "C" {
 #if CFG_TUSB_OS == OPT_OS_ZEPHYR
   #include <zephyr/kernel.h>
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  #if TUSB_MCU_VENDOR_ESPRESSIF
+  #ifdef ESP_PLATFORM
     // ESP-IDF need "freertos/" prefix in include path.
     // CFG_TUSB_OS_INC_PATH should be defined accordingly.
     #include "freertos/FreeRTOS.h"
@@ -195,6 +195,7 @@ static inline void board_delay(uint32_t ms) {
 
 // stdio getchar() is blocking, this is non-blocking version
 int board_getchar(void);
+void board_putchar(int c);
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index a282e9961..9d4a3b76c 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -15,7 +15,7 @@ CFLAGS += \
 CROSS_COMPILE = arm-none-eabi-
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk
index 37d381f9f..1ce80e22b 100644
--- a/hw/bsp/broadcom_64bit/family.mk
+++ b/hw/bsp/broadcom_64bit/family.mk
@@ -14,7 +14,7 @@ CFLAGS += \
 CROSS_COMPILE = aarch64-none-elf-
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 6df0bfdfe..2de4dc760 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -13,7 +13,6 @@ else
 # The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
 # code for the Bridgetek SDK. This can be used instead of the prebuilt
 # library.
-DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
 # The SDK can be used to load specific files from the Bridgetek SDK.
 FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
 INC += "$(TOP)/$(FT9XX_SDK)/include"
diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk
index c08451b9c..2ff9f79e3 100644
--- a/hw/bsp/ch32f20x/family.mk
+++ b/hw/bsp/ch32f20x/family.mk
@@ -1,6 +1,5 @@
 # Submodules
 CH32F20X_SDK = hw/mcu/wch/ch32f20x
-DEPS_SUBMODULES += $(CH32F20X_SDK)
 
 # WCH-SDK paths
 CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
index 256958088..56f49205c 100644
--- a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
@@ -13,6 +13,8 @@ extern "C" {
 #define LED_PORT       GPIOA
 #define LED_PIN        GPIO_Pin_0
 #define LED_STATE_ON   0
+#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
+#define LED_MODE       GPIO_Mode_Out_OD
 
 #define UART_DEV        USART1
 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
index 827226d80..4a040e0df 100644
--- a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
@@ -13,6 +13,8 @@ extern "C" {
 #define LED_PORT       GPIOA
 #define LED_PIN        GPIO_Pin_0
 #define LED_STATE_ON   0
+#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
+#define LED_MODE       GPIO_Mode_Out_OD
 
 #define UART_DEV        USART2
 #define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
index f02fceced..63237861c 100644
--- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
@@ -13,6 +13,8 @@ extern "C" {
 #define LED_PORT       GPIOA
 #define LED_PIN        GPIO_Pin_15
 #define LED_STATE_ON   0
+#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
+#define LED_MODE       GPIO_Mode_Out_OD
 
 #define UART_DEV        USART1
 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c
index d674ccd6f..2c212a82b 100644
--- a/hw/bsp/ch32v20x/family.c
+++ b/hw/bsp/ch32v20x/family.c
@@ -99,11 +99,11 @@ void board_init(void) {
   SysTick_Config(SystemCoreClock / 1000);
 #endif
 
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+  LED_CLOCK_EN();
 
   GPIO_InitTypeDef GPIO_InitStructure = {
     .GPIO_Pin = LED_PIN,
-    .GPIO_Mode = GPIO_Mode_Out_OD,
+    .GPIO_Mode = LED_MODE,
     .GPIO_Speed = GPIO_Speed_10MHz,
   };
   GPIO_Init(LED_PORT, &GPIO_InitStructure);
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake
new file mode 100644
index 000000000..9adaefb17
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c6")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h
new file mode 100644
index 000000000..18b51410d
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Feather EPS32-C6
+   url: https://www.adafruit.com/product/5933
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          15
+
+#define BUTTON_PIN            9
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  21
+#define MAX3421_MOSI_PIN 22
+#define MAX3421_MISO_PIN 23
+#define MAX3421_CS_PIN   8
+#define MAX3421_INTR_PIN 7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
index 6f3229b70..40c4963d9 100644
--- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
@@ -41,9 +41,10 @@
 #define BUTTON_PIN            35
 #define BUTTON_STATE_ACTIVE   0
 
-// For CI hardware test, to test both device and host on the same HS port with help of
-#define HIL_DEVICE_HOST_MUX_PIN  47
-#define HIL_DEVICE_STATE         1
+// For CI hardware test, to test both device and host on the same HS port with help of TS3USB30
+// https://www.adafruit.com/product/5871
+#define HIL_TS3USB30_MODE_PIN    47
+#define HIL_TS3USB30_MODE_DEVICE 1
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
index 9c197591f..499a626a6 100644
--- a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
@@ -36,13 +36,19 @@
  extern "C" {
 #endif
 
-// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
-// however earlier revision v1.1 WS2812 is connected to GPIO 17
 #define NEOPIXEL_PIN          18
 
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
index 6d7a94668..d2483c84f 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
@@ -36,7 +36,7 @@
  extern "C" {
 #endif
 
-#define NEOPIXEL_PIN          48
+#define NEOPIXEL_PIN          38
 
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index d01fdbe5b..5c1914ebe 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -49,6 +49,11 @@
 #define MAX3421_CS_PIN   15
 #define MAX3421_INTR_PIN 14
 
+// For CI hardware test, to test both device and host on the same HS port with help of TS3USB30
+// https://www.adafruit.com/product/5871
+#define HIL_TS3USB30_MODE_PIN    47
+#define HIL_TS3USB30_MODE_DEVICE 1
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 7049c0415..2a5deed26 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -49,7 +49,9 @@ static led_strip_handle_t led_strip;
 static void max3421_init(void);
 #endif
 
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
 static bool usb_init(void);
+#endif
 
 //--------------------------------------------------------------------+
 // Implementation
@@ -92,10 +94,10 @@ void board_init(void) {
   usb_init();
 #endif
 
-#ifdef HIL_DEVICE_HOST_MUX_PIN
-  gpio_reset_pin(HIL_DEVICE_HOST_MUX_PIN);
-  gpio_set_direction(HIL_DEVICE_HOST_MUX_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(HIL_DEVICE_HOST_MUX_PIN, CFG_TUD_ENABLED ? HIL_DEVICE_STATE : (1-HIL_DEVICE_STATE));
+#ifdef HIL_TS3USB30_MODE_PIN
+  gpio_reset_pin(HIL_TS3USB30_MODE_PIN);
+  gpio_set_direction(HIL_TS3USB30_MODE_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(HIL_TS3USB30_MODE_PIN, CFG_TUD_ENABLED ? HIL_TS3USB30_MODE_DEVICE : (1-HIL_TS3USB30_MODE_DEVICE));
 #endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
@@ -154,6 +156,10 @@ int board_getchar(void) {
   return getchar();
 }
 
+void board_putchar(int c) {
+  putchar(c);
+}
+
 //--------------------------------------------------------------------
 // PHY Init
 //--------------------------------------------------------------------
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index daa12cdb4..ca9eadaf6 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -1,5 +1,3 @@
-cmake_minimum_required(VERSION 3.5)
-
 # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
 include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
 string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
@@ -32,8 +30,6 @@ endif ()
 
 # Add example src and bsp directories
 set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
-
-# set SDKCONFIG for each IDF Target
-set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET})
+set(SDKCONFIG ${CMAKE_BINARY_DIR}/sdkconfig)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/espressif/family.mk b/hw/bsp/espressif/family.mk
deleted file mode 100644
index 0dc21b8eb..000000000
--- a/hw/bsp/espressif/family.mk
+++ /dev/null
@@ -1,34 +0,0 @@
-#DEPS_SUBMODULES +=
-
-UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
-UF2_FAMILY_ID_esp32s3 = 0xc47e5767
-
-BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
-ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
-	IDF_TARGET = esp32s2
-else
-ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
-	IDF_TARGET = esp32s3
-endif
-endif
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
-
-build: all
-
-fullclean:
-	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
-	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index e7161eba3..9ec80df91 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -38,6 +38,11 @@ if (NOT DEFINED TOOLCHAIN)
   set(TOOLCHAIN gcc)
 endif ()
 
+# Optimization
+if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "")
+  set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE)
+endif ()
+
 #-------------------------------------------------------------
 # FAMILY and BOARD
 #-------------------------------------------------------------
@@ -208,13 +213,16 @@ function(family_configure_common TARGET RTOS)
 
   # LOGGER option
   if (DEFINED LOGGER)
+    string(TOUPPER ${LOGGER} LOGGER)
     target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
     # Add segger rtt to example
-    if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+    if(LOGGER STREQUAL "RTT")
       target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
       target_include_directories(${TARGET}  PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
 #      target_compile_definitions(${TARGET}  PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
     endif ()
+  else ()
+    target_compile_definitions(${TARGET} PUBLIC LOGGER_UART)
   endif ()
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
@@ -270,10 +278,6 @@ function(family_add_tinyusb TARGET OPT_MCU)
 
   # Add TinyUSB sources, include and common define
   tinyusb_target_add(${TARGET})
-
-  # path to tusb_config.h
-  target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src)
-
   target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU})
   if (DEFINED LOG)
     target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG})
@@ -486,7 +490,7 @@ function(family_flash_openocd TARGET)
   # note skip verify since it has issue with rp2040
   add_custom_target(${TARGET}-openocd
     DEPENDS ${TARGET}
-    COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
+    COMMAND ${OPENOCD} -c "tcl_port disabled; gdb_port disabled" ${OPTION_LIST} -c "init; halt; program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
     VERBATIM
     )
 endfunction()
@@ -506,10 +510,16 @@ endfunction()
 # Add flash openocd adi (Analog Devices) target
 # included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd
 function(family_flash_openocd_adi TARGET)
-  if (DEFINED $ENV{MAXIM_PATH})
-    # use openocd from msdk
-    set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd)
-    set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts")
+  if (DEFINED MAXIM_PATH)
+    # use openocd from msdk with MAXIM_PATH cmake variable first if the user specified it
+    set(OPENOCD ${MAXIM_PATH}/Tools/OpenOCD/openocd)
+    set(OPENOCD_OPTION2 "-s ${MAXIM_PATH}/Tools/OpenOCD/scripts")
+  elseif (DEFINED ENV{MAXIM_PATH})
+    # use openocd from msdk with MAXIM_PATH environment variable. Normalize
+    # since msdk can be Windows (MinGW) or Linux
+    file(TO_CMAKE_PATH "$ENV{MAXIM_PATH}" MAXIM_PATH_NORM)
+    set(OPENOCD ${MAXIM_PATH_NORM}/Tools/OpenOCD/openocd)
+    set(OPENOCD_OPTION2 "-s ${MAXIM_PATH_NORM}/Tools/OpenOCD/scripts")
   else()
     # compiled from source
     if (NOT DEFINED OPENOCD_ADI_PATH)
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
index ae1aa7fb1..b9e4851bf 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
@@ -15,11 +15,11 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v11.0
+product: Clocks v15.0
 processor: MIMXRT1015xxxxx
 package_id: MIMXRT1015DAF5A
 mcu_data: ksdk2_0
-processor_version: 13.0.2
+processor_version: 24.12.10
 board: MIMXRT1015-EVK
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
index 2acdb16a7..cccbe487a 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
@@ -36,39 +36,39 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
 
 /* Clock outputs (values are in Hz): */
-#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
-#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
-#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
-#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
-#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
-#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
-#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           196363636UL
-#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
-#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
-#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
-#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
-#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
-#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
-#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
-#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
-#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL    /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL        /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL            /* Clock consumers of CLKO1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL            /* Clock consumers of CLKO2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG */
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL     /* Clock consumers of CLK_24M output : GPT1, GPT2 */
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL    /* Clock consumers of ENET_500M_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           196363636UL    /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL    /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL     /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL    /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL     /* Clock consumers of MQS_MCLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL     /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL     /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL     /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL     /* Clock consumers of SAI2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL     /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL            /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL     /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL     /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL     /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL            /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL    /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL     /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL    /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */
 
 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
  */
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
index 97224a332..76c1dae70 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
@@ -6,11 +6,11 @@
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Pins v13.1
+product: Pins v17.0
 processor: MIMXRT1015xxxxx
 package_id: MIMXRT1015DAF5A
 mcu_data: ksdk2_0
-processor_version: 13.0.2
+processor_version: 24.12.10
 board: MIMXRT1015-EVK
 external_user_signals: {}
 pin_labels:
@@ -32,6 +32,7 @@ power_domains: {NVCC_GPIO: '3.3'}
  * END ****************************************************************************************************************/
 void BOARD_InitBootPins(void) {
     BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
 }
 
 /*
@@ -40,8 +41,6 @@ BOARD_InitPins:
 - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
 - pin_list:
   - {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
-  - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, pull_up_down_config: Pull_Down_100K_Ohm}
-  - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
   - {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT}
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  */
@@ -73,15 +72,11 @@ void BOARD_InitPins(void) {
   /* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */
   GPIO_PinInit(GPIO3, 21U, &USER_LED_config);
 
-  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
-  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
   IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U);
   IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U);
-  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
   IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitQSPIPins:
@@ -113,6 +108,30 @@ void BOARD_InitQSPIPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
 }
 
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow}
+  - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
+}
 /***********************************************************************************************************************
  * EOF
  **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
index c9cbe3b72..2f3bf2c4c 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
@@ -37,7 +37,7 @@ extern "C" {
  */
 void BOARD_InitBootPins(void);
 
-/* GPIO_EMC_09 (number 1), USER_BUTTON */
+/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */
 /* Routed pin properties */
 #define BOARD_INITPINS_USER_BUTTON_PERIPHERAL                              GPIO2   /*!< Peripheral name */
 #define BOARD_INITPINS_USER_BUTTON_SIGNAL                                gpio_io   /*!< Signal name */
@@ -51,16 +51,6 @@ void BOARD_InitBootPins(void);
 #define BOARD_INITPINS_USER_BUTTON_PIN                                        9U   /*!< PORT pin number */
 #define BOARD_INITPINS_USER_BUTTON_PIN_MASK                           (1U << 9U)   /*!< PORT pin mask */
 
-/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
-/* Routed pin properties */
-#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
-#define BOARD_INITPINS_UART1_RXD_SIGNAL                                       RX   /*!< Signal name */
-
-/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
-/* Routed pin properties */
-#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Peripheral name */
-#define BOARD_INITPINS_UART1_TXD_SIGNAL                                       TX   /*!< Signal name */
-
 /* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */
 /* Routed pin properties */
 #define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO3   /*!< Peripheral name */
@@ -69,6 +59,7 @@ void BOARD_InitBootPins(void);
 
 /* Symbols to be used with GPIO driver */
 #define BOARD_INITPINS_USER_LED_GPIO                                       GPIO3   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE                               0U   /*!< GPIO output initial state */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN                                     21U   /*!< GPIO pin number */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                        (1U << 21U)   /*!< GPIO pin mask */
 #define BOARD_INITPINS_USER_LED_PORT                                       GPIO3   /*!< PORT peripheral base pointer */
@@ -119,6 +110,23 @@ void BOARD_InitPins(void);
  */
 void BOARD_InitQSPIPins(void);
 
+/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL                             RX   /*!< Signal name */
+
+/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL                    LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL                             TX   /*!< Signal name */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
index 88265d32e..917bed375 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding= "UTF-8" ?>
-<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    <common>
       <processor>MIMXRT1015xxxxx</processor>
       <package>MIMXRT1015DAF5A</package>
@@ -13,19 +13,18 @@
    </common>
    <preferences>
       <validate_boot_init_only>true</validate_boot_init_only>
-      <generate_extended_information>false</generate_extended_information>
       <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
       <update_include_paths>true</update_include_paths>
       <generate_registers_defines>false</generate_registers_defines>
    </preferences>
    <tools>
-      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/pin_mux.c" update_enabled="true"/>
             <file path="board/pin_mux.h" update_enabled="true"/>
          </generated_project_files>
          <pins_profile>
-            <processor_version>13.0.2</processor_version>
+            <processor_version>24.12.10</processor_version>
             <pin_labels>
                <pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/>
             </pin_labels>
@@ -45,12 +44,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
-                     <feature name="initialized" evaluation="equal">
-                        <data>true</data>
-                     </feature>
-                  </dependency>
-                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -79,12 +73,6 @@
                         <pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
                      </pin_features>
                   </pin>
-                  <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
-                     <pin_features>
-                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
-                     </pin_features>
-                  </pin>
-                  <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/>
                   <pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
                      <pin_features>
                         <pin_feature name="direction" value="OUTPUT"/>
@@ -100,7 +88,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -125,15 +113,52 @@
                   <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
                </pins>
             </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
          </functions_list>
       </pins>
-      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+      <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/clock_config.c" update_enabled="true"/>
             <file path="board/clock_config.h" update_enabled="true"/>
          </generated_project_files>
          <clocks_profile>
-            <processor_version>13.0.2</processor_version>
+            <processor_version>24.12.10</processor_version>
          </clocks_profile>
          <clock_configurations>
             <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
index 778ab02f2..be684faee 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
@@ -15,11 +15,11 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v11.0
+product: Clocks v15.0
 processor: MIMXRT1064xxxxA
 package_id: MIMXRT1064DVL6A
 mcu_data: ksdk2_0
-processor_version: 13.0.2
+processor_version: 24.12.10
 board: MIMXRT1064-EVK
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
index 7ce24b6f4..2fa713c0d 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
@@ -36,56 +36,56 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
 
 /* Clock outputs (values are in Hz): */
-#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
-#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
-#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
-#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
-#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
-#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
-#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
-#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
-#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
-#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
-#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
-#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
-#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
-#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
-#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
-#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
-#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
-#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
-#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
-#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
-#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
-#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
-#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
-#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
-#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
-#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
-#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
-#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
-#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
-#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
-#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL    /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL     /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL        /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL            /* Clock consumers of CLKO1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL            /* Clock consumers of CLKO2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL      /* Clock consumers of CLK_1M output : EWM, RTWDOG */
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL     /* Clock consumers of CLK_24M output : GPT1, GPT2 */
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL     /* Clock consumers of CSI_CLK_ROOT output : CSI */
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL      /* Clock consumers of ENET2_125M_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL            /* Clock consumers of ENET2_REF_CLK output : ENET2 */
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL            /* Clock consumers of ENET2_TX_CLK output : ENET2 */
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL      /* Clock consumers of ENET_125M_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL      /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL            /* Clock consumers of ENET_REF_CLK output : ENET */
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL            /* Clock consumers of ENET_TX_CLK output : ENET */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL     /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL     /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL    /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL    /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL     /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL     /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL    /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL     /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL     /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL    /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL   /* Clock consumers of LVDS1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL     /* Clock consumers of MQS_MCLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL     /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL    /* Clock consumers of PLL7_MAIN_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL     /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL     /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL     /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL     /* Clock consumers of SAI1_MCLK3 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL     /* Clock consumers of SAI2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL     /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL            /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL     /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL     /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL     /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL            /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL     /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL     /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL     /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL            /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL    /* Clock consumers of TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL     /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL    /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL    /* Clock consumers of USBPHY2_CLK output : USB2 */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL    /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL    /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
 
 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
  */
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
index 8e975dc72..60c4bab37 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
@@ -6,11 +6,11 @@
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Pins v13.1
+product: Pins v17.0
 processor: MIMXRT1064xxxxA
 package_id: MIMXRT1064DVL6A
 mcu_data: ksdk2_0
-processor_version: 13.0.2
+processor_version: 24.12.10
 board: MIMXRT1064-EVK
 pin_labels:
 - {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
@@ -81,7 +81,6 @@ void BOARD_InitPins(void) {
   IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitDEBUG_UARTPins:
@@ -109,7 +108,6 @@ void BOARD_InitDEBUG_UARTPins(void) {
   IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitSDRAMPins:
@@ -209,7 +207,6 @@ void BOARD_InitSDRAMPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitCSIPins:
@@ -267,7 +264,6 @@ void BOARD_InitCSIPins(void) {
   IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitLCDPins:
@@ -360,7 +356,6 @@ void BOARD_InitLCDPins(void) {
   IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitCANPins:
@@ -384,7 +379,6 @@ void BOARD_InitCANPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitENETPins:
@@ -424,7 +418,6 @@ void BOARD_InitENETPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitUSDHCPins:
@@ -458,7 +451,6 @@ void BOARD_InitUSDHCPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
 }
 
-
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 BOARD_InitQSPIPins:
@@ -491,7 +483,6 @@ void BOARD_InitQSPIPins(void) {
   IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
   IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
 }
-
 /***********************************************************************************************************************
  * EOF
  **********************************************************************************************************************/
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
index bf494b6f6..be1461f16 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
@@ -47,6 +47,7 @@ void BOARD_InitBootPins(void);
 
 /* Symbols to be used with GPIO driver */
 #define BOARD_INITPINS_USER_LED_GPIO                                       GPIO1   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE                               0U   /*!< GPIO output initial state */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN                                      9U   /*!< GPIO pin number */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 9U)   /*!< GPIO pin mask */
 #define BOARD_INITPINS_USER_LED_PORT                                       GPIO1   /*!< PORT peripheral base pointer */
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
index 3f0948101..58247fa5b 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding= "UTF-8" ?>
-<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    <common>
       <processor>MIMXRT1064xxxxA</processor>
       <package>MIMXRT1064DVL6A</package>
@@ -13,19 +13,18 @@
    </common>
    <preferences>
       <validate_boot_init_only>true</validate_boot_init_only>
-      <generate_extended_information>false</generate_extended_information>
       <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
       <update_include_paths>true</update_include_paths>
       <generate_registers_defines>false</generate_registers_defines>
    </preferences>
    <tools>
-      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/pin_mux.c" update_enabled="true"/>
             <file path="board/pin_mux.h" update_enabled="true"/>
          </generated_project_files>
          <pins_profile>
-            <processor_version>13.0.2</processor_version>
+            <processor_version>24.12.10</processor_version>
             <pin_labels>
                <pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/>
                <pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/>
@@ -41,7 +40,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                  <dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -84,7 +83,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -137,7 +136,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSDRAMPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -204,12 +203,12 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -277,7 +276,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitLCDPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -450,7 +449,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCANPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -479,7 +478,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitENETPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -516,7 +515,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSDHCPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -550,7 +549,7 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
                      <feature name="initialized" evaluation="equal">
                         <data>true</data>
                      </feature>
@@ -578,13 +577,13 @@
             </function>
          </functions_list>
       </pins>
-      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+      <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/clock_config.c" update_enabled="true"/>
             <file path="board/clock_config.h" update_enabled="true"/>
          </generated_project_files>
          <clocks_profile>
-            <processor_version>13.0.2</processor_version>
+            <processor_version>24.12.10</processor_version>
          </clocks_profile>
          <clock_configurations>
             <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
@@ -751,10 +750,7 @@
          <dcdx_configurations/>
       </dcdx>
       <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
-         <generated_project_files>
-            <file path="board/peripherals.c" update_enabled="true"/>
-            <file path="board/peripherals.h" update_enabled="true"/>
-         </generated_project_files>
+         <generated_project_files/>
          <peripherals_profile>
             <processor_version>13.0.2</processor_version>
          </peripherals_profile>
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
index 66f1f983a..4f06299de 100644
--- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
@@ -11,11 +11,11 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v14.0
+product: Clocks v15.0
 processor: MIMXRT1176xxxxx
 package_id: MIMXRT1176DVMAA
 mcu_data: ksdk2_0
-processor_version: 16.3.0
+processor_version: 24.12.10
 board: MIMXRT1170-EVKB
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
index 2c83fb55e..5e8cb91c1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
@@ -6,11 +6,11 @@
 /*
  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Pins v16.0
+product: Pins v17.0
 processor: MIMXRT1176xxxxx
 package_id: MIMXRT1176DVMAA
 mcu_data: ksdk2_0
-processor_version: 16.3.0
+processor_version: 24.12.10
 board: MIMXRT1170-EVKB
 external_user_signals: {}
 pin_labels:
@@ -31,6 +31,7 @@ pin_labels:
  * END ****************************************************************************************************************/
 void BOARD_InitBootPins(void) {
     BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
 }
 
 /*
@@ -38,10 +39,6 @@ void BOARD_InitBootPins(void) {
 BOARD_InitPins:
 - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
 - pin_list:
-  - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
-    open_drain: Disable, drive_strength: High, slew_rate: Slow}
-  - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
-    open_drain: Disable, drive_strength: High, slew_rate: Slow}
   - {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper}
   - {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up}
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
@@ -78,12 +75,6 @@ void BOARD_InitPins(void) {
       IOMUXC_GPIO_AD_04_GPIO9_IO03,           /* GPIO_AD_04 is configured as GPIO9_IO03 */
       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
   IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 is configured as LPUART1_TXD */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 is configured as LPUART1_RXD */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
       IOMUXC_WAKEUP_DIG_GPIO13_IO00,          /* WAKEUP_DIG is configured as GPIO13_IO00 */
       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
   IOMUXC_SetPinConfig(
@@ -96,6 +87,40 @@ void BOARD_InitPins(void) {
                                                  Domain write protection: Both cores are allowed
                                                  Domain write protection lock: Neither of DWP bits is locked */
   IOMUXC_SetPinConfig(
+      IOMUXC_WAKEUP_DIG_GPIO13_IO00,          /* WAKEUP_DIG PAD functional properties : */
+      0x0EU);                                 /* Pull / Keep Select Field: Pull Enable
+                                                 Pull Up / Down Config. Field: Weak pull up
+                                                 Open Drain SNVS Field: Disabled
+                                                 Domain write protection: Both cores are allowed
+                                                 Domain write protection lock: Neither of DWP bits is locked */
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
+- pin_list:
+  - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow}
+  - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core.
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* LPCG on: LPCG is ON. */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 is configured as LPUART1_TXD */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 is configured as LPUART1_RXD */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinConfig(
       IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 PAD functional properties : */
       0x02U);                                 /* Slew Rate Field: Slow Slew Rate
                                                  Drive Strength Field: high drive strength
@@ -113,13 +138,6 @@ void BOARD_InitPins(void) {
                                                  Open Drain Field: Disabled
                                                  Domain write protection: Both cores are allowed
                                                  Domain write protection lock: Neither of DWP bits is locked */
-  IOMUXC_SetPinConfig(
-      IOMUXC_WAKEUP_DIG_GPIO13_IO00,          /* WAKEUP_DIG PAD functional properties : */
-      0x0EU);                                 /* Pull / Keep Select Field: Pull Enable
-                                                 Pull Up / Down Config. Field: Weak pull up
-                                                 Open Drain SNVS Field: Disabled
-                                                 Domain write protection: Both cores are allowed
-                                                 Domain write protection lock: Neither of DWP bits is locked */
 }
 /***********************************************************************************************************************
  * EOF
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
index a5b621476..0e0368ef6 100644
--- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
@@ -25,16 +25,6 @@ extern "C" {
  */
 void BOARD_InitBootPins(void);
 
-/* GPIO_AD_25 (coord M15), LPUART1_RXD */
-/* Routed pin properties */
-#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL                            LPUART1   /*!< Peripheral name */
-#define BOARD_INITPINS_LPUART1_RXD_SIGNAL                                    RXD   /*!< Signal name */
-
-/* GPIO_AD_24 (coord L13), LPUART1_TXD */
-/* Routed pin properties */
-#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL                            LPUART1   /*!< Peripheral name */
-#define BOARD_INITPINS_LPUART1_TXD_SIGNAL                                    TXD   /*!< Signal name */
-
 /* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */
 /* Routed pin properties */
 #define BOARD_INITPINS_USER_LED_PERIPHERAL                                 GPIO9   /*!< Peripheral name */
@@ -43,6 +33,7 @@ void BOARD_InitBootPins(void);
 
 /* Symbols to be used with GPIO driver */
 #define BOARD_INITPINS_USER_LED_GPIO                                       GPIO9   /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE                               0U   /*!< GPIO output initial state */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN                                      3U   /*!< GPIO pin number */
 #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK                         (1U << 3U)   /*!< GPIO pin mask */
 
@@ -63,6 +54,22 @@ void BOARD_InitBootPins(void);
  */
 void BOARD_InitPins(void);                    /* Function assigned for the Cortex-M7F */
 
+/* GPIO_AD_24 (coord L13), LPUART1_TXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_PERIPHERAL                  LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_SIGNAL                          TXD   /*!< Signal name */
+
+/* GPIO_AD_25 (coord M15), LPUART1_RXD */
+/* Routed pin properties */
+#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_PERIPHERAL                  LPUART1   /*!< Peripheral name */
+#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_SIGNAL                          RXD   /*!< Signal name */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void);          /* Function assigned for the Cortex-M7F */
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
index a4c8917f7..de6b12394 100644
--- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
+++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding= "UTF-8" ?>
-<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_16 http://mcuxpresso.nxp.com/XSD/mex_configuration_16.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="16" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_16" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    <common>
       <processor>MIMXRT1176xxxxx</processor>
       <package>MIMXRT1176DVMAA</package>
@@ -13,19 +13,18 @@
    </common>
    <preferences>
       <validate_boot_init_only>true</validate_boot_init_only>
-      <generate_extended_information>false</generate_extended_information>
       <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
       <update_include_paths>true</update_include_paths>
       <generate_registers_defines>false</generate_registers_defines>
    </preferences>
    <tools>
-      <pins name="Pins" version="16.0" enabled="true" update_project_code="true">
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/pin_mux.c" update_enabled="true"/>
             <file path="board/pin_mux.h" update_enabled="true"/>
          </generated_project_files>
          <pins_profile>
-            <processor_version>16.3.0</processor_version>
+            <processor_version>24.12.10</processor_version>
             <pin_labels>
                <pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/>
             </pin_labels>
@@ -43,11 +42,6 @@
                   <enableClock>true</enableClock>
                </options>
                <dependencies>
-                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
-                     <feature name="initialized" evaluation="equal">
-                        <data>true</data>
-                     </feature>
-                  </dependency>
                   <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
                      <feature name="enabled" evaluation="equal" configuration="cm7">
                         <data>true</data>
@@ -65,51 +59,70 @@
                   </dependency>
                </dependencies>
                <pins>
-                  <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
+                  <pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04">
                      <pin_features>
-                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="identifier" value="USER_LED"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
                         <pin_feature name="pull_up_down_config" value="Pull_Down"/>
                         <pin_feature name="pull_keeper_select" value="Keeper"/>
-                        <pin_feature name="open_drain" value="Disable"/>
-                        <pin_feature name="drive_strength" value="High"/>
-                        <pin_feature name="slew_rate" value="Slow"/>
                      </pin_features>
                   </pin>
-                  <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
+                  <pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP">
                      <pin_features>
-                        <pin_feature name="software_input_on" value="Disable"/>
-                        <pin_feature name="pull_up_down_config" value="Pull_Down"/>
-                        <pin_feature name="pull_keeper_select" value="Keeper"/>
-                        <pin_feature name="open_drain" value="Disable"/>
-                        <pin_feature name="drive_strength" value="High"/>
-                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up"/>
                      </pin_features>
                   </pin>
-                  <pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04">
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm7</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm7">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
                      <pin_features>
-                        <pin_feature name="identifier" value="USER_LED"/>
-                        <pin_feature name="direction" value="OUTPUT"/>
-                        <pin_feature name="pull_up_down_config" value="Pull_Down"/>
                         <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
                      </pin_features>
                   </pin>
-                  <pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP">
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
                      <pin_features>
-                        <pin_feature name="direction" value="INPUT"/>
-                        <pin_feature name="pull_up_down_config" value="Pull_Up"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
                      </pin_features>
                   </pin>
                </pins>
             </function>
          </functions_list>
       </pins>
-      <clocks name="Clocks" version="14.0" enabled="true" update_project_code="true">
+      <clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/clock_config.c" update_enabled="true"/>
             <file path="board/clock_config.h" update_enabled="true"/>
          </generated_project_files>
          <clocks_profile>
-            <processor_version>16.3.0</processor_version>
+            <processor_version>24.12.10</processor_version>
          </clocks_profile>
          <clock_configurations>
             <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index ad529a227..7e4734a66 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -61,7 +61,7 @@
   - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
 */
 
-static void BOARD_ConfigMPU(void);
+// static void BOARD_ConfigMPU(void);
 
 // needed by fsl_flexspi_nor_boot
 TU_ATTR_USED const uint8_t dcd_data[] = {0x00};
@@ -109,8 +109,8 @@ static void init_usb_phy(uint8_t usb_id) {
 }
 
 void board_init(void) {
-  BOARD_ConfigMPU();
-  BOARD_InitPins();
+  // BOARD_ConfigMPU();
+  BOARD_InitBootPins();
   BOARD_BootClockRUN();
   SystemCoreClockUpdate();
 
@@ -258,6 +258,7 @@ void _exit(int __status) {
 //--------------------------------------------------------------------
 // MPU configuration
 //--------------------------------------------------------------------
+#if 0 // TODO move to per board specific
 #if __CORTEX_M == 7
 static void BOARD_ConfigMPU(void) {
   #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
@@ -455,7 +456,7 @@ static void BOARD_ConfigMPU(void) {
 
 #elif __CORTEX_M == 4
 
-void BOARD_ConfigMPU(void) {
+static void BOARD_ConfigMPU(void) {
   #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
   extern uint32_t Image$$RW_m_ncache$$Base[];
   /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
@@ -636,3 +637,4 @@ void BOARD_ConfigMPU(void) {
   LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
 }
 #endif
+#endif
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f08ccb3e5..6224b63a4 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -123,8 +123,6 @@ function(family_configure_example TARGET RTOS)
   # Board target
   add_board_target(board_${BOARD})
 
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
@@ -146,8 +144,6 @@ function(family_configure_example TARGET RTOS)
     )
   target_link_libraries(${TARGET} PUBLIC board_${BOARD})
 
-
-
   # Flashing
   family_add_bin_hex(${TARGET})
   family_flash_jlink(${TARGET})
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0cf84a4ae..9a2c37121 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -1,6 +1,5 @@
 UF2_FAMILY_ID = 0x4fb2d5bd
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/bsp/kinetis_k/family.mk b/hw/bsp/kinetis_k/family.mk
index 844ce332e..e95cdb717 100644
--- a/hw/bsp/kinetis_k/family.mk
+++ b/hw/bsp/kinetis_k/family.mk
@@ -1,5 +1,4 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/${MCU_VARIANT}
 include $(TOP)/$(BOARD_PATH)/board.mk
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
index c4dc65b63..fb3eb2a03 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -3,7 +3,7 @@ MCU = K32L2A41A
 CFLAGS += -DCPU_K32L2A41VLH1A
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
 
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
index 1fdce981a..8d113aecf 100644
--- a/hw/bsp/kinetis_kl/family.mk
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -1,5 +1,4 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
index 31eb2f28f..8513c24ca 100644
--- a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 CFLAGS += \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
 
diff --git a/hw/bsp/lpc13/family.mk b/hw/bsp/lpc13/family.mk
index 4f8b48c4b..7ff2c058a 100644
--- a/hw/bsp/lpc13/family.mk
+++ b/hw/bsp/lpc13/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m3
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index b83e008e8..3267e973a 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m3
 
@@ -15,7 +13,7 @@ CFLAGS += \
 LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
 
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index d719a47b7..e8d707ea5 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m3
@@ -13,7 +11,7 @@ CFLAGS += \
   -DRTC_EV_SUPPORT=0
 
 # lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 # caused by freeRTOS port !!
 CFLAGS += -Wno-error=maybe-uninitialized
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index f120f63b2..3bbafed11 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -1,4 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
@@ -12,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-qual
 
 LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk
index ef9fe57b2..c72631235 100644
--- a/hw/bsp/lpc40/family.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m4
@@ -13,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
 LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
index e1406aae7..39be867d1 100644
--- a/hw/bsp/lpc43/family.mk
+++ b/hw/bsp/lpc43/family.mk
@@ -1,18 +1,17 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 
 include ${TOP}/${BOARD_PATH}/board.mk
 CPU_CORE ?= cortex-m4
 
 CFLAGS += \
-  -flto \
-  -nostdlib \
   -DCORE_M4 \
   -D__USE_LPCOPEN \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += \
+CFLAGS_GCC += \
+  -flto \
+  -nostdlib \
   -Wno-error=unused-parameter \
   -Wno-error=cast-qual \
   -Wno-error=incompatible-pointer-types \
diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake
index 2146c29f7..09d97d256 100644
--- a/hw/bsp/lpc51/family.cmake
+++ b/hw/bsp/lpc51/family.cmake
@@ -36,7 +36,7 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index b41b5438e..91d1261cb 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -28,15 +28,16 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c
 
 INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+    $(TOP)/$(BOARD_PATH) \
+    $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index 90497b9fb..66320870a 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,6 +56,7 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/common
     ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/flexcomm/usart
     ${SDK_DIR}/drivers/lpc_iocon
     ${SDK_DIR}/drivers/lpc_gpio
     ${SDK_DIR}/drivers/lpuart
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index ea4c9c39c..94168f6b2 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -1,5 +1,4 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m4
@@ -36,7 +35,7 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c
 
 INC += \
@@ -46,6 +45,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index cd1eb5f78..a89548635 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,9 +56,9 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/common
     ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/flexcomm/usart
     ${SDK_DIR}/drivers/lpc_iocon
     ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/lpuart
     ${SDK_DIR}/drivers/sctimer
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index d82e85904..fadf852cd 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,6 +1,5 @@
 UF2_FAMILY_ID = 0x2abc77ec
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m33
@@ -45,7 +44,7 @@ SRC_C += \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
 	lib/sct_neopixel/sct_neopixel.c
 
 INC += \
@@ -55,11 +54,10 @@ INC += \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/ \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
 	$(TOP)/$(SDK_DIR)/drivers/sctimer
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md
deleted file mode 100644
index ca66a1ac4..000000000
--- a/hw/bsp/max32650/README.md
+++ /dev/null
@@ -1,46 +0,0 @@
-# Analog Devices MAX32650/1/2
-
-This BSP is for working with the Analog Devices
-[MAX32650](https://www.analog.com/en/products/max32650.html),
-[MAX32651](https://www.analog.com/en/products/max32651.html) and
-[MAX32652](https://www.analog.com/en/products/max32652.html)
-microcontrollers.  The following boards are supported:
- * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html)
- * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html)
- * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader)
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-### MAX32650 and MAX32652
-
-The default flashing behavior in this BSP for the MAX32650 and MAX32652 is to
-utilize JLink.  This can be done by running the `flash` or `flash-jlink` rule
-for Makefiles, or the `<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
-
-### MAX32651
-
-The MAX32651 features an integrated secure bootloader which requires the
-application image be signed prior to flashing.  Both the Makefile and CMake
-scripts account for this signing automatically when building for the
-MAX32651EVKIT.
-
-To flash the signed image, the MSDK's OpenOCD variant must be used.  To flash
-the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk`
-and `<target>-msdk` rule and target.
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake
deleted file mode 100644
index fffdcc9fb..000000000
--- a/hw/bsp/max32650/boards/max32650evkit/board.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Use the standard, non-secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
-
-function(update_board_extras TARGET)
-  #No extra arguments
-endfunction()
-
-function(prepare_image TARGET_IN)
-  #No signing required
-endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk
deleted file mode 100644
index 0bc210e11..000000000
--- a/hw/bsp/max32650/boards/max32650evkit/board.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Use the standard, non-secure linker file
-LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake
deleted file mode 100644
index fffdcc9fb..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/board.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Use the standard, non-secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
-
-function(update_board_extras TARGET)
-  #No extra arguments
-endfunction()
-
-function(prepare_image TARGET_IN)
-  #No signing required
-endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk
deleted file mode 100644
index 0bc210e11..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/board.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Use the standard, non-secure linker file
-LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
deleted file mode 100644
index 0e56a91ec..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld
+++ /dev/null
@@ -1,119 +0,0 @@
-MEMORY {
-    ROM (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
-    FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
-    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
-}
-
-SECTIONS {
-    .text :
-    {
-        _text = .;
-        KEEP(*(.isr_vector))
-        *(.text*)    /* program code */
-        *(.rodata*)  /* read-only data: "const" */
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-         /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* C++ Exception handling */
-        KEEP(*(.eh_frame*))
-        _etext = .;
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    /* it's used for C++ exception handling      */
-    /* we need to keep this to avoid overlapping */
-    .ARM.exidx :
-    {
-        __exidx_start = .;
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        __exidx_end = .;
-    } > FLASH
-
-    .data :
-    {
-        _data = ALIGN(., 4);
-        *(vtable)
-        *(.data*)           /*read-write initialized data: initialized global variable*/
-        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
-        *(.flashprog*)      /* Flash program */
-
-
-        /* These array sections are used by __libc_init_array to call static C++ constructors */
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        _edata = ALIGN(., 4);
-    } > SRAM AT>FLASH
-    __load_data = LOADADDR(.data);
-    .bss :
-    {
-        . = ALIGN(4);
-        _bss = .;
-        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
-        *(COMMON)
-        _ebss = ALIGN(., 4);
-    } > SRAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > SRAM
-
-    .heap (COPY):
-    {
-        . = ALIGN(4);
-        PROVIDE ( end = . );
-        PROVIDE ( _end = . );
-        *(.heap*)
-        __HeapLimit = ABSOLUTE(__StackLimit);
-    } > SRAM
-
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
-}
diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c
deleted file mode 100644
index 8f0e56734..000000000
--- a/hw/bsp/max32650/family.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE);
-
-  //USB
-  // Startup the HIRC96M clock if it's not on already
-  if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
-      MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
-      MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
-  }
-
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[13];//USN Buffer
-  MXC_SYS_GetUSN(hw_id, 13);
-
-  size_t act_len = TU_MIN(max_len, 13);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake
deleted file mode 100644
index b1d5dded7..000000000
--- a/hw/bsp/max32650/family.cmake
+++ /dev/null
@@ -1,169 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific information and functions
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32650)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg")
-
-set(FAMILY_MCUS MAX32650 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32650
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32650
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32650
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-
-    # Run any board specific updates
-    update_board_extras(${TARGET})
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me10.c
-    ${PERIPH_SRC}/SYS/sys_me10.c
-    ${PERIPH_SRC}/TPU/tpu_me10.c
-    ${PERIPH_SRC}/TPU/tpu_reva.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me10.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me10.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me10.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/ICC/icc_common.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me10.c
-    ${PERIPH_SRC}/UART/uart_reva.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include
-    ${MAX32_PERIPH}/Include/MAX32650
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/TPU
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      -u sb_header #Needed when linking libraries to not lose the Signing header
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32650)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-
-  # Add the optional MSDK OpenOCD flashing
-  family_flash_msdk(${TARGET})
-endfunction()
-
-function(family_flash_msdk TARGET)
-  # Prepare the image (signed) if the board requires it
-  prepare_image(${TARGET})
-
-  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
-  add_custom_target(${TARGET}-msdk
-    DEPENDS ${TARGET}
-    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
-            -f interface/cmsis-dap.cfg -f target/max32650.cfg
-            -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
-    VERBATIM
-  )
-endfunction()
diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk
deleted file mode 100644
index d2fc293e4..000000000
--- a/hw/bsp/max32650/family.mk
+++ /dev/null
@@ -1,140 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32650/1/2 SDK
-CFLAGS +=   -DTARGET=MAX32650 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32650 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=cast-align \
-			-Wno-error=cast-qual \
-			-Wno-error=sign-compare
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# Configure the flash rule. By default, use JLink.
-SIGNED_BUILD ?= 0
-DEFAULT_FLASH = flash-jlink
-
-# If the applications needs to be signed (for the MAX32651), sign it first and
-# then need to use MSDK's OpenOCD to flash it
-# Also need to include the __SLA_FWK__ define to enable the signed header into
-# memory
-ifeq ($(SIGNED_BUILD), 1)
-# Extra definitions to build for the secure part
-CFLAGS += -D__SLA_FWK__
-DEFAULT_FLASH := sign-build flash-msdk
-endif
-
-# For flash-jlink target
-JLINK_DEVICE = max32650
-
-# Configure the flash rule
-flash: $(DEFAULT_FLASH)
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me10.c \
-	$(PERIPH_SRC)/SYS/sys_me10.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me10.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me10.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me10.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/ICC/icc_common.c \
-	$(PERIPH_SRC)/TPU/tpu_me10.c \
-	$(PERIPH_SRC)/TPU/tpu_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me10.c \
-	$(PERIPH_SRC)/UART/uart_reva.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TPU \
-	$(PERIPH_SRC)/UART
-
-
-# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
-# MAX32651 has a secure bootloader which requires the image to be signed before
-# loading into flash. All MAX32651EVKIT's have the same key for evaluation
-# purposes, so create a special flash rule to sign the binary and flash using
-# the MSDK.
-MCU_PATH = $(TOP)/hw/mcu/analog/max32/
-# Assume no extension for sign utility
-SIGN_EXE = sign_app
-ifeq ($(OS), Windows_NT)
-# Must use .exe extension on Windows, since the binaries
-# for Linux may live in the same place.
-SIGN_EXE := sign_app.exe
-else
-UNAME = $(shell uname -s)
-ifneq ($(findstring MSYS_NT,$(UNAME)),)
-# Must also use .exe extension for MSYS2
-SIGN_EXE := sign_app.exe
-endif
-endif
-
-# Rule to sign the build.  This will in-place modify the existing .elf file
-# an populate the .sig section with the signature value
-sign-build: $(BUILD)/$(PROJECT).elf
-	$(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
-	$(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
-		key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
-		ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
-	$(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32650.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index e5a76af85..000000000
--- a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "mxc_device.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/max32666/README.md b/hw/bsp/max32666/README.md
deleted file mode 100644
index 902d82e25..000000000
--- a/hw/bsp/max32666/README.md
+++ /dev/null
@@ -1,32 +0,0 @@
-# Analog Devices MAX32665/6
-
-This BSP is for working with the Analog Devices
-[MAX32665](https://www.analog.com/en/products/max32665.html) and
-[MAX32666](https://www.analog.com/en/products/max32666.html) microcontrollers.
-The following boards are supported:
- * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html)
- * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html)
-
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32666/boards/max32666evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32666/boards/max32666evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32666/boards/max32666fthr/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32666/boards/max32666fthr/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake
deleted file mode 100644
index 49798729a..000000000
--- a/hw/bsp/max32666/family.cmake
+++ /dev/null
@@ -1,147 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32666)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg")
-
-set(FAMILY_MCUS MAX32666 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32665
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32665
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32666
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me14.c
-    ${PERIPH_SRC}/SYS/sys_me14.c
-    ${PERIPH_SRC}/TPU/tpu_me14.c
-    ${PERIPH_SRC}/TPU/tpu_reva.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me14.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me14.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me14.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me14.c
-    ${PERIPH_SRC}/UART/uart_reva.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include
-    ${MAX32_PERIPH}/Include/MAX32665
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/TPU
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-  -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32666)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-endfunction()
diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk
deleted file mode 100644
index b4f7d1e57..000000000
--- a/hw/bsp/max32666/family.mk
+++ /dev/null
@@ -1,93 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
-LD_FILE = $(FAMILY_PATH)/max32666.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32665/6 SDK
-CFLAGS +=   -DTARGET=MAX32665 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32665 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=cast-align \
-			-Wno-error=cast-qual
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max32666
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32665.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me14.c \
-	$(PERIPH_SRC)/SYS/sys_me14.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me14.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me14.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me14.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/TPU/tpu_me14.c \
-    $(PERIPH_SRC)/TPU/tpu_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me14.c \
-	$(PERIPH_SRC)/UART/uart_reva.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TPU \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32690/README.md b/hw/bsp/max32690/README.md
deleted file mode 100644
index 081ae0ad4..000000000
--- a/hw/bsp/max32690/README.md
+++ /dev/null
@@ -1,31 +0,0 @@
-# Analog Devices MAX32690
-
-This BSP is for working with the Analog Devices
-[MAX32690](https://www.analog.com/en/products/max32690.html) microcontroller.
-The following boards are supported:
- * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html)
- * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html)
-
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32690/boards/apard32690/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32690/boards/apard32690/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32690/boards/max32690evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32690/boards/max32690evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c
deleted file mode 100644
index 7ba5fbef3..000000000
--- a/hw/bsp/max32690/family.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mcr_regs.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
-
-  //USB
-  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
-  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
-
-  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake
deleted file mode 100644
index 0d544d9e6..000000000
--- a/hw/bsp/max32690/family.cmake
+++ /dev/null
@@ -1,152 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32690)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg")
-
-set(FAMILY_MCUS MAX32690 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32690
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32690
-    FLASH_ORIGIN=0x10000000
-    FLASH_SIZE=0x340000
-    SRAM_ORIGIN=0x20000000
-    SRAM_SIZE=0x100000
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32690
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me18.c
-    ${PERIPH_SRC}/SYS/sys_me18.c
-    ${PERIPH_SRC}/CTB/ctb_me18.c
-    ${PERIPH_SRC}/CTB/ctb_reva.c
-    ${PERIPH_SRC}/CTB/ctb_common.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me18.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me18.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me18.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me18.c
-    ${PERIPH_SRC}/UART/uart_revb.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include
-    ${MAX32_PERIPH}/Include/MAX32690
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/CTB
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32690)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-endfunction()
diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk
deleted file mode 100644
index d4df8ef2f..000000000
--- a/hw/bsp/max32690/family.mk
+++ /dev/null
@@ -1,101 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S
-LD_FILE = $(FAMILY_PATH)/max32690.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32690 SDK
-CFLAGS +=   -DTARGET=MAX32690 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32690 \
-			-DFLASH_ORIGIN=0x10000000 \
-			-DFLASH_SIZE=0x340000 \
-			-DSRAM_ORIGIN=0x20000000 \
-			-DSRAM_SIZE=0x100000 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=unused-parameter \
-			-Wno-error=strict-prototypes \
-			-Wno-error=old-style-declaration \
-			-Wno-error=sign-compare \
-			-Wno-error=cast-qual \
-			-Wno-lto-type-mismatch
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max32690
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32690.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me18.c \
-	$(PERIPH_SRC)/SYS/sys_me18.c \
-	$(PERIPH_SRC)/CTB/ctb_me18.c \
-	$(PERIPH_SRC)/CTB/ctb_reva.c \
-	$(PERIPH_SRC)/CTB/ctb_common.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me18.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me18.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me18.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me18.c \
-	$(PERIPH_SRC)/UART/uart_revb.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/CTB \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max78002/README.md b/hw/bsp/max78002/README.md
deleted file mode 100644
index 4fb1bede4..000000000
--- a/hw/bsp/max78002/README.md
+++ /dev/null
@@ -1,28 +0,0 @@
-# Analog Devices MAX78002
-
-This BSP is for working with the Analog Devices
-[MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller.
-The following boards are supported:
- * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html)
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However,
-at the time of writing, the necessary flashing algorithms for OpenOCD have not
-yet been incorporated into the OpenOCD master branch.  To utilize the provided
-debug probes, please install the bundled MSDK package which includes the
-appropriate OpenOCD modifications.   To leverage this OpenOCD instance, run the
-`flash-msdk` Makefile rule, or `<target>-msdk` CMake target.
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max78002/boards/max78002evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max78002/boards/max78002evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c
deleted file mode 100644
index 5c23f40f9..000000000
--- a/hw/bsp/max78002/family.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mcr_regs.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
-  UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V
-
-  //USB
-  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
-
-  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake
deleted file mode 100644
index ce0fcfa08..000000000
--- a/hw/bsp/max78002/family.cmake
+++ /dev/null
@@ -1,166 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max78000)
-
-set(FAMILY_MCUS MAX78002 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX78002
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX78002
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX78002
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_ai87.c
-    ${PERIPH_SRC}/SYS/sys_ai87.c
-    ${PERIPH_SRC}/AES/aes_ai87.c
-    ${PERIPH_SRC}/AES/aes_revb.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_ai87.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_ai87.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_ai87.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/TRNG/trng_ai87.c
-    ${PERIPH_SRC}/TRNG/trng_revb.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_ai87.c
-    ${PERIPH_SRC}/UART/uart_revb.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include
-    ${MAX32_PERIPH}/Include/MAX78002
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/AES
-    ${PERIPH_SRC}/TRNG
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-    )
-
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX78002)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-  )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_msdk(${TARGET})
-endfunction()
-
-# Add flash msdk target
-function(family_flash_msdk TARGET)
-  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
-
-  add_custom_target(${TARGET}-msdk
-    DEPENDS ${TARGET}
-    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
-		        -f interface/cmsis-dap.cfg -f target/max78002.cfg
-		        -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
-    VERBATIM
-    )
-endfunction()
diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk
deleted file mode 100644
index 997816261..000000000
--- a/hw/bsp/max78002/family.mk
+++ /dev/null
@@ -1,99 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S
-LD_FILE = $(FAMILY_PATH)/max78002.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX78002 SDK
-CFLAGS +=   -DTARGET=MAX78002 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX78002 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=redundant-decls \
-			-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=enum-conversion \
-			-Wno-error=sign-compare \
-			-Wno-error=cast-qual
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max78000
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max78002.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_ai87.c \
-	$(PERIPH_SRC)/SYS/sys_ai87.c \
-	$(PERIPH_SRC)/AES/aes_ai87.c \
-	$(PERIPH_SRC)/AES/aes_revb.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_ai87.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_ai87.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_ai87.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/TRNG/trng_ai87.c \
-	$(PERIPH_SRC)/TRNG/trng_revb.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_ai87.c \
-	$(PERIPH_SRC)/UART/uart_revb.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/AES \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TRNG \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h
index e5a76af85..e5a76af85 100644
--- a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h
diff --git a/hw/bsp/maxim/README.md b/hw/bsp/maxim/README.md
new file mode 100644
index 000000000..e2983e899
--- /dev/null
+++ b/hw/bsp/maxim/README.md
@@ -0,0 +1,43 @@
+# Analog Devices MAXIM
+
+This BSP is for working with the Analog microcontrollers
+ - [MAX32650](https://www.analog.com/en/products/max32650.html),
+ - [MAX32651](https://www.analog.com/en/products/max32651.html)
+ - [MAX32652](https://www.analog.com/en/products/max32652.html)
+ - [MAX32665](https://www.analog.com/en/products/max32665.html)
+ - [MAX32666](https://www.analog.com/en/products/max32666.html)
+ - [MAX32690](https://www.analog.com/en/products/max32690.html)
+ - [MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller.
+
+The following boards are supported:
+ * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html)
+ * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html)
+ * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader)
+ * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html)
+ * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html)
+ * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html)
+ * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html)
+ * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html)
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+The default flashing behavior in this BSP is to utilize JLink.  This can be done
+by running the `flash` or `flash-jlink` rule for Makefiles, or the
+`<target>-jlink` target for CMake.
+
+Most the Evaluation Kit and boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch.  To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications.   To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-openocd` CMake
+target.
diff --git a/hw/bsp/maxim/boards/apard32690/board.cmake b/hw/bsp/maxim/boards/apard32690/board.cmake
new file mode 100644
index 000000000..a03d05f8d
--- /dev/null
+++ b/hw/bsp/maxim/boards/apard32690/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32690)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/maxim/boards/apard32690/board.h
index 87b9c4e88..19f74bf56 100644
--- a/hw/bsp/max32690/boards/apard32690/board.h
+++ b/hw/bsp/maxim/boards/apard32690/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32690.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/apard32690/board.mk b/hw/bsp/maxim/boards/apard32690/board.mk
new file mode 100644
index 000000000..d8a0c9cae
--- /dev/null
+++ b/hw/bsp/maxim/boards/apard32690/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32690
diff --git a/hw/bsp/maxim/boards/max32650evkit/board.cmake b/hw/bsp/maxim/boards/max32650evkit/board.cmake
new file mode 100644
index 000000000..59721e756
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650evkit/board.cmake
@@ -0,0 +1,8 @@
+set(MAX_DEVICE max32650)
+
+function(update_board TARGET)
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/maxim/boards/max32650evkit/board.h
index 65ed2659e..0dfc074fa 100644
--- a/hw/bsp/max32650/boards/max32650evkit/board.h
+++ b/hw/bsp/maxim/boards/max32650evkit/board.h
@@ -26,14 +26,13 @@
 
 /* metadata:
    name: MAX32650 EVKIT
-   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview
+   url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html
 */
 
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32650evkit/board.mk b/hw/bsp/maxim/boards/max32650evkit/board.mk
new file mode 100644
index 000000000..3a4108005
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32650
diff --git a/hw/bsp/maxim/boards/max32650fthr/board.cmake b/hw/bsp/maxim/boards/max32650fthr/board.cmake
new file mode 100644
index 000000000..59721e756
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650fthr/board.cmake
@@ -0,0 +1,8 @@
+set(MAX_DEVICE max32650)
+
+function(update_board TARGET)
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/maxim/boards/max32650fthr/board.h
index 755fa15b5..af0fa1c39 100644
--- a/hw/bsp/max32650/boards/max32650fthr/board.h
+++ b/hw/bsp/maxim/boards/max32650fthr/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32650fthr/board.mk b/hw/bsp/maxim/boards/max32650fthr/board.mk
new file mode 100644
index 000000000..3a4108005
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650fthr/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32650
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/maxim/boards/max32651evkit/board.cmake
index bd8077a42..773989126 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.cmake
+++ b/hw/bsp/maxim/boards/max32651evkit/board.cmake
@@ -1,22 +1,23 @@
+set(MAX_DEVICE max32650)
+
 # Use the secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/max32651.ld)
 
-function(update_board_extras TARGET)
+function(update_board TARGET)
   # for the signed target, need to add the __SLA_FWK__ define
   target_compile_definitions(${TARGET} PUBLIC
     __SLA_FWK__
     )
 endfunction()
 
-function(prepare_image TARGET_IN)
-  #For the signed target, set up a POST_BUILD command to sign the elf file once
-  #created
+function(sign_image TARGET_IN)
+  #For the signed target, set up a POST_BUILD command to sign the elf file once created
   if((WIN32) OR (MINGW) OR (MSYS))
     set(SIGN_EXE "sign_app.exe")
   else()
     set(SIGN_EXE "sign_app")
   endif()
-  set(MCU_PATH "${TOP}/hw/mcu/analog/max32/")
+  set(MCU_PATH "${TOP}/hw/mcu/analog/msdk/")
 
   # Custom POST_BUILD command
   add_custom_command(
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/maxim/boards/max32651evkit/board.h
index 0b49ff309..dbf2a4b7c 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.h
+++ b/hw/bsp/maxim/boards/max32651evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/maxim/boards/max32651evkit/board.mk
index b609598c1..5d4971148 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.mk
+++ b/hw/bsp/maxim/boards/max32651evkit/board.mk
@@ -1,5 +1,7 @@
+MAX_DEVICE = max32650
+
 # Use the secure linker file
-LD_FILE = $(BOARD_PATH)/max32651.ld
+LD_FILE = $(FAMILY_PATH)/linker/max32651.ld
 
 # Let the family script know the build needs to be signed
 SIGNED_BUILD := 1
diff --git a/hw/bsp/maxim/boards/max32666evkit/board.cmake b/hw/bsp/maxim/boards/max32666evkit/board.cmake
new file mode 100644
index 000000000..e7116b603
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32665)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/maxim/boards/max32666evkit/board.h
index 54589444d..42965d3c5 100644
--- a/hw/bsp/max32666/boards/max32666evkit/board.h
+++ b/hw/bsp/maxim/boards/max32666evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32665.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32666evkit/board.mk b/hw/bsp/maxim/boards/max32666evkit/board.mk
new file mode 100644
index 000000000..a1cf3045d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32665
diff --git a/hw/bsp/maxim/boards/max32666fthr/board.cmake b/hw/bsp/maxim/boards/max32666fthr/board.cmake
new file mode 100644
index 000000000..e7116b603
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666fthr/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32665)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/maxim/boards/max32666fthr/board.h
index 0caea5934..fbb217949 100644
--- a/hw/bsp/max32666/boards/max32666fthr/board.h
+++ b/hw/bsp/maxim/boards/max32666fthr/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32665.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32666fthr/board.mk b/hw/bsp/maxim/boards/max32666fthr/board.mk
new file mode 100644
index 000000000..a1cf3045d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666fthr/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32665
diff --git a/hw/bsp/maxim/boards/max32690evkit/board.cmake b/hw/bsp/maxim/boards/max32690evkit/board.cmake
new file mode 100644
index 000000000..a03d05f8d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32690evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32690)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/maxim/boards/max32690evkit/board.h
index aa8dbb1de..41c73621f 100644
--- a/hw/bsp/max32690/boards/max32690evkit/board.h
+++ b/hw/bsp/maxim/boards/max32690evkit/board.h
@@ -32,13 +32,12 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "max32690.h"
+
 // LED
 #define LED_PORT        MXC_GPIO0
 #define LED_PIN         MXC_GPIO_PIN_14
diff --git a/hw/bsp/maxim/boards/max32690evkit/board.mk b/hw/bsp/maxim/boards/max32690evkit/board.mk
new file mode 100644
index 000000000..d8a0c9cae
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32690evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32690
diff --git a/hw/bsp/maxim/boards/max78002evkit/board.cmake b/hw/bsp/maxim/boards/max78002evkit/board.cmake
new file mode 100644
index 000000000..dd4c3c215
--- /dev/null
+++ b/hw/bsp/maxim/boards/max78002evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max78002)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/maxim/boards/max78002evkit/board.h
index 85d55d7de..8c1fc13d4 100644
--- a/hw/bsp/max78002/boards/max78002evkit/board.h
+++ b/hw/bsp/maxim/boards/max78002evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max78002.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max78002evkit/board.mk b/hw/bsp/maxim/boards/max78002evkit/board.mk
new file mode 100644
index 000000000..b19e95187
--- /dev/null
+++ b/hw/bsp/maxim/boards/max78002evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max78002
diff --git a/hw/bsp/max32666/family.c b/hw/bsp/maxim/family.c
index 05306c6c9..0ef6b8c4d 100644
--- a/hw/bsp/max32666/family.c
+++ b/hw/bsp/maxim/family.c
@@ -35,7 +35,9 @@
 
 #include "gpio.h"
 #include "mxc_sys.h"
+#if __has_include("mcr_regs.h")
 #include "mcr_regs.h"
+#endif
 #include "mxc_device.h"
 #include "uart.h"
 
@@ -88,16 +90,45 @@ void board_init(void) {
   MXC_GPIO_Config(&gpioConfig);
 
   // UART
+#if MAX_PERIPH_ID == 14
   MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP);
+#elif MAX_PERIPH_ID == 18 || MAX_PERIPH_ID == 87
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+  #if MAX_PERIPH_ID == 87
+  UART_PORT->vssel |= UART_VDDIO_BITS; // Set necessary bits to 3.3V
+  #endif
+#endif
 
   //USB
+#if defined(MAX32650)
   // Startup the HIRC96M clock if it's not on already
-  if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
-      MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+  if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
+    MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
+    MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
   }
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
 
+#elif defined(MAX32665) || defined(MAX32666)
+  // Startup the HIRC96M clock if it's not on already
+  if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
+    MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+  }
   MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
   MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+
+#elif defined(MAX32690)
+  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+
+#  elif  defined(MAX78002)
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+#else
+  #error "Unsupported MAXIM MCU for board_dfu_init"
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -121,13 +152,18 @@ uint32_t board_button_read(void) {
 }
 
 size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
+#if defined(MAX32650)
+  // USN is 13 bytes on this device
+  MXC_SYS_GetUSN(id, 13);
+  return 13;
+#else
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer
+  MXC_SYS_GetUSN(hw_id, NULL); // 2nd parameter is optional checksum buffer
 
   size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
   memcpy(id, hw_id, act_len);
   return act_len;
+#endif
 }
 
 int board_uart_read(uint8_t *buf, int len) {
diff --git a/hw/bsp/maxim/family.cmake b/hw/bsp/maxim/family.cmake
new file mode 100644
index 000000000..75daec753
--- /dev/null
+++ b/hw/bsp/maxim/family.cmake
@@ -0,0 +1,196 @@
+include_guard()
+
+# stub: overridden by board.cmake if needed
+function(sign_image TARGET_IN)
+endfunction()
+
+set(MSDK_LIB ${TOP}/hw/mcu/analog/msdk/Libraries)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+string(TOUPPER ${MAX_DEVICE} MAX_DEVICE_UPPER)
+cmake_print_variables(MAX_DEVICE MAX_DEVICE_UPPER)
+
+set(JLINK_DEVICE ${MAX_DEVICE})
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${MAX_DEVICE}.cfg")
+
+set(FAMILY_MCUS ${MAX_DEVICE_UPPER} CACHE INTERNAL "")
+
+if (${MAX_DEVICE} STREQUAL "max32650")
+  set(PERIPH_ID 10)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666")
+  set(PERIPH_ID 14)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max32690")
+  set(PERIPH_ID 18)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max78002")
+  set(PERIPH_ID 87)
+  set(PERIPH_SUFFIX "ai")
+else()
+  message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}")
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MAX_DEVICE}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  # Common
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${MSDK_LIB}/CMSIS/5.9.0/Core/Include
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include
+    ${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER}
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC
+    ${MSDK_LIB}/PeriphDrivers/Source/UART
+    )
+
+  # device specific
+  if (${MAX_DEVICE} STREQUAL "max32650" OR
+    ${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU
+      )
+  elseif (${MAX_DEVICE} STREQUAL "max32690")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB
+      )
+  elseif (${MAX_DEVICE} STREQUAL "max78002")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/AES
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG
+      )
+  else()
+    message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}")
+  endif()
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    TARGET=${MAX_DEVICE_UPPER}
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    ${MAX_DEVICE_UPPER}
+    IAR_PRAGMAS=0
+    MAX_PERIPH_ID=${PERIPH_ID}
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+  target_compile_options(${BOARD_TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_${MAX_DEVICE_UPPER})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+
+  sign_image(${TARGET}) # for secured device such as max32651
+  family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/maxim/family.mk b/hw/bsp/maxim/family.mk
new file mode 100644
index 000000000..3ddf8cf39
--- /dev/null
+++ b/hw/bsp/maxim/family.mk
@@ -0,0 +1,190 @@
+MSDK_LIB = hw/mcu/analog/msdk/Libraries
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+JLINK_DEVICE = ${MAX_DEVICE}
+MAX_DEVICE_UPPER = $(call to_upper,${MAX_DEVICE})
+
+ifeq ($(MAX_DEVICE),max32650)
+  PERIPH_ID = 10
+  PERIPH_SUFFIX = me
+endif
+
+ifneq ($(filter $(MAX_DEVICE),max32665 max32666),)
+  PERIPH_ID = 14
+  PERIPH_SUFFIX = me
+endif
+
+ifeq ($(MAX_DEVICE),max32690)
+  PERIPH_ID = 18
+  PERIPH_SUFFIX = me
+endif
+
+ifeq ($(MAX_DEVICE),max78002)
+  PERIPH_ID = 87
+  PERIPH_SUFFIX = ai
+endif
+
+ifndef PERIPH_ID
+  $(error Unsupported MAX device: ${MAX_DEVICE})
+endif
+
+# Configure the flash rule. By default, use JLink.
+SIGNED_BUILD ?= 0
+DEFAULT_FLASH = flash-jlink
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DTARGET=${MAX_DEVICE_UPPER}\
+  -DTARGET_REV=0x4131 \
+	-DMXC_ASSERT_ENABLE \
+	-D${MAX_DEVICE_UPPER} \
+	-DIAR_PRAGMAS=0 \
+	-DMAX_PERIPH_ID=${PERIPH_ID} \
+  -DCFG_TUSB_MCU=OPT_MCU_${MAX_DEVICE_UPPER} \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += \
+	-Wno-error=old-style-declaration \
+	-Wno-error=redundant-decls \
+  -Wno-error=strict-prototypes \
+	-Wno-error=unused-parameter \
+	-Wno-error=cast-align \
+	-Wno-error=cast-qual \
+	-Wno-error=sign-compare \
+	-Wno-error=enum-conversion \
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+LD_FILE_GCC ?= $(FAMILY_PATH)/linker/${MAX_DEVICE}.ld
+
+# If the applications needs to be signed (for the MAX32651), sign it first and
+# then need to use MSDK's OpenOCD to flash it
+# Also need to include the __SLA_FWK__ define to enable the signed header into
+# memory
+ifeq ($(SIGNED_BUILD), 1)
+# Extra definitions to build for the secure part
+CFLAGS += -D__SLA_FWK__
+DEFAULT_FLASH := sign-build flash-msdk
+endif
+
+# -----------------
+# Sources & Include
+# -----------------
+
+# common
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c \
+	${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+
+SRC_S_GCC += ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/${MSDK_LIB}/CMSIS/5.9.0/Core/Include \
+	$(TOP)/${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER} \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/SYS \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/GPIO \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/ICC \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/FLC \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/UART \
+
+# device specific
+ifneq ($(filter $(MAX_DEVICE),max32650 max32665 max32666),)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c \
+
+  INC += $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/TPU
+endif
+
+ifeq (${MAX_DEVICE},max32690)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \
+
+  INC += ${TOP}/${MSDK_LIB}/PeriphDrivers/Source/CTB
+endif
+
+ifeq (${MAX_DEVICE},max78002)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \
+
+  INC += \
+		${TOP}/${MSDK_LIB}/PeriphDrivers/Source/AES \
+		${TOP}/${MSDK_LIB}/PeriphDrivers/Source/TRNG
+endif
+
+
+# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
+# MAX32651 has a secure bootloader which requires the image to be signed before
+# loading into flash. All MAX32651EVKIT's have the same key for evaluation
+# purposes, so create a special flash rule to sign the binary and flash using
+# the MSDK.
+MCU_PATH = $(TOP)/hw/mcu/analog/msdk/
+# Assume no extension for sign utility
+SIGN_EXE = sign_app
+ifeq ($(OS), Windows_NT)
+# Must use .exe extension on Windows, since the binaries
+# for Linux may live in the same place.
+SIGN_EXE := sign_app.exe
+else
+UNAME = $(shell uname -s)
+ifneq ($(findstring MSYS_NT,$(UNAME)),)
+# Must also use .exe extension for MSYS2
+SIGN_EXE := sign_app.exe
+endif
+endif
+
+# Rule to sign the build.  This will in-place modify the existing .elf file
+# an populate the .sig section with the signature value
+sign-build: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
+	$(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
+		key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
+		ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32650.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# Configure the flash rule
+flash: $(DEFAULT_FLASH)
diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/maxim/linker/max32650.ld
index 0e56a91ec..0e56a91ec 100644
--- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld
+++ b/hw/bsp/maxim/linker/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/maxim/linker/max32651.ld
index 3921d10f2..3921d10f2 100644
--- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld
+++ b/hw/bsp/maxim/linker/max32651.ld
diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/maxim/linker/max32665.ld
index 06c124247..06c124247 100644
--- a/hw/bsp/max32666/max32666.ld
+++ b/hw/bsp/maxim/linker/max32665.ld
diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/maxim/linker/max32690.ld
index 64b906a54..64b906a54 100644
--- a/hw/bsp/max32690/max32690.ld
+++ b/hw/bsp/maxim/linker/max32690.ld
diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/maxim/linker/max78002.ld
index e5c4866ee..e5c4866ee 100644
--- a/hw/bsp/max78002/max78002.ld
+++ b/hw/bsp/maxim/linker/max78002.ld
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
index fb1290088..86f987de9 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
@@ -39,10 +39,10 @@ extern "C" {
 // LED
 #define LED_GPIO              GPIO3
 #define LED_CLK               kCLOCK_GateGPIO3
-#define LED_PIN               12 // red
+#define LED_PIN               12 //red
 #define LED_STATE_ON          0
 
-// ISP button (Dummy, use unused pin
+// ISP button
 #define BUTTON_GPIO           GPIO3
 #define BUTTON_CLK            kCLOCK_GateGPIO3
 #define BUTTON_PIN            29 //sw2
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
index f16bc51f6..5a132dc67 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
@@ -45,14 +45,13 @@ processor_version: 0.13.0
  * Variables
  ******************************************************************************/
 /* System clock frequency. */
-//uint32_t SystemCoreClock;
+//extern uint32_t SystemCoreClock;
 
 /*******************************************************************************
  ************************ BOARD_InitBootClocks function ************************
  ******************************************************************************/
 void BOARD_InitBootClocks(void)
 {
-    BOARD_BootClockFRO96M();
 }
 
 /*******************************************************************************
@@ -386,7 +385,6 @@ void BOARD_BootClockFRO64M(void)
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!Configuration
 name: BOARD_BootClockFRO96M
-called_from_default_init: true
 outputs:
 - {id: CLK_1M_clock.outFreq, value: 1 MHz}
 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
index cc8f56e63..47709951b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
@@ -4,7 +4,6 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-
 /***********************************************************************************************************************
  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@@ -18,16 +17,13 @@ product: Pins v14.0
 processor: MCXA153
 package_id: MCXA153VLH
 mcu_data: ksdk2_0
-processor_version: 0.14.3
-pin_labels:
-- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
+processor_version: 0.14.4
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  */
 /* clang-format on */
 
 #include "fsl_common.h"
 #include "fsl_port.h"
-#include "fsl_gpio.h"
 #include "pin_mux.h"
 
 /* FUNCTION ************************************************************************************************************
@@ -47,8 +43,10 @@ void BOARD_InitBootPins(void)
 BOARD_InitPins:
 - options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
 - pin_list:
-  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  */
 /* clang-format on */
@@ -61,15 +59,6 @@ BOARD_InitPins:
  * END ****************************************************************************************************************/
 void BOARD_InitPins(void)
 {
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
-    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
-
-    /* write to PORT0: Peripheral clock is enabled */
-    CLOCK_EnableClock(kCLOCK_GatePORT0);
-
-    /* Write to GPIO3: Peripheral clock is enabled */
     CLOCK_EnableClock(kCLOCK_GateGPIO3);
     /* Write to PORT3: Peripheral clock is enabled */
     CLOCK_EnableClock(kCLOCK_GatePORT3);
@@ -78,30 +67,13 @@ void BOARD_InitPins(void)
     /* PORT3 peripheral is released from reset */
     RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
 
-    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
-                                       kPORT_PullDisable,
-                                       /* Low internal pull resistor value is selected. */
-                                       kPORT_LowPullResistor,
-                                       /* Fast slew rate is configured */
-                                       kPORT_FastSlewRate,
-                                       /* Passive input filter is disabled */
-                                       kPORT_PassiveFilterDisable,
-                                       /* Open drain output is disabled */
-                                       kPORT_OpenDrainDisable,
-                                       /* Low drive strength is configured */
-                                       kPORT_LowDriveStrength,
-                                       /* Normal drive strength is configured */
-                                       kPORT_NormalDriveStrength,
-                                       /* Pin is configured as P3_12 */
-                                       kPORT_MuxAlt0,
-                                       /* Digital input enabled */
-                                       kPORT_InputBufferEnable,
-                                       /* Digital input is not inverted */
-                                       kPORT_InputNormal,
-                                       /* Pin Control Register fields [15:0] are not locked */
-                                       kPORT_UnlockRegister};
-    /* PORT3_12 (pin 38) is configured as P3_12 */
-      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
+
+    /* Write to PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+    /* LPUART0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    /* PORT0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
 
     const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
                                                     kPORT_PullUp,
@@ -152,7 +124,6 @@ void BOARD_InitPins(void)
                                                     kPORT_UnlockRegister};
     /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
     PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
-
 }
 /***********************************************************************************************************************
  * EOF
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
index 06b6fdee9..2c0e617a5 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
@@ -1,9 +1,13 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
 
 #ifndef _PIN_MUX_H_
 #define _PIN_MUX_H_
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
new file mode 100644
index 000000000..a6aa6c2e4
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MCXA156)
+set(MCU_CORE MCXA156)
+
+set(JLINK_DEVICE MCXA156_M33)
+set(PYOCD_TARGET MCXA156)
+set(NXPLINK_DEVICE MCXA156:MCXA156)
+
+set(PORT 0)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXA156VLH
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.h b/hw/bsp/mcx/boards/frdm_mcxa156/board.h
new file mode 100644
index 000000000..6c19797c6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.h
@@ -0,0 +1,69 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Freedom MCXA156
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_GateGPIO3
+#define LED_PIN               12 // red
+#define LED_STATE_ON          0
+
+// ISP button
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_GateGPIO0
+#define BUTTON_PIN            6 //SW3
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART0
+
+static inline void board_uart_init_clock(void) {
+  /* attach 12 MHz clock to LPUART0 (debug console) */
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+}
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
new file mode 100644
index 000000000..d4a59b32a
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXA156
+MCU_CORE = MCXA156
+PORT = 0
+
+CPU_CORE = cortex-m33-nodsp-nofp
+CFLAGS += \
+	-DCPU_MCXA156VLH \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
+
+JLINK_DEVICE = MCXA156
+PYOCD_TARGET = MCXA156
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c
new file mode 100644
index 000000000..f549af243
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v13.0
+processor: MCXA156
+package_id: MCXA156VLL
+mcu_data: ksdk2_0
+processor_version: 0.15.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockFRO96M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CPU_clock.outFreq, value: 12 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO24M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 6 MHz}
+- {id: System_clock.outFreq, value: 24 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO24M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO48M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO48M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO64M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 64 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
+- {id: FRO_HF_clock.outFreq, value: 64 MHz}
+- {id: MAIN_clock.outFreq, value: 64 MHz}
+- {id: Slow_clock.outFreq, value: 16 MHz}
+- {id: System_clock.outFreq, value: 64 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 64 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO64M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO96M
+called_from_default_init: true
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 96 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
+- {id: FRO_HF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: CLKOUTDIV_HALT, value: Enable}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO96M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h
new file mode 100644
index 000000000..3f5dfefda
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO24M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO64M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c
new file mode 100644
index 000000000..de35103a6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v15.0
+processor: MCXA156
+package_id: MCXA156VLL
+mcu_data: ksdk2_0
+processor_version: 0.15.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+
+      RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+  /* GPIO3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GateGPIO3);
+  /* PORT3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GatePORT3);
+  /* GPIO3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+  /* PORT3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+
+  /* GPIO3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GateGPIO0);
+  /* PORT3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GatePORT0);
+  /* GPIO3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+  /* PORT3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+
+    /* PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+    /* LPUART0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    /* PORT0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+
+    const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_RXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_2 (pin 78) is configured as LPUART0_RXD */
+    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config);
+
+    const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_TXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_3 (pin 79) is configured as LPUART0_TXD */
+    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h
new file mode 100644
index 000000000..fb7d1fc04
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
index a35b6818a..bb15620ef 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
@@ -49,17 +49,22 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_DEV              LPUART4
+#define UART_DEV                   LPUART4
+#define LP_FLEXCOMM_INST           4
+
+#include "fsl_lpflexcomm.h"
 
 static inline void board_uart_init_clock(void) {
+
   /* attach FRO 12M to FLEXCOMM4 */
+
+  LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART);
+
   CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
   CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
   RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
 
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+}
 
 // XTAL
 #define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.c b/hw/bsp/mcx/drivers/spc/fsl_spc.c
new file mode 100644
index 000000000..b16ca5fc5
--- /dev/null
+++ b/hw/bsp/mcx/drivers/spc/fsl_spc.c
@@ -0,0 +1,1680 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_spc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mcx_spc"
+#endif
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification spc_c_ref_1$
+ * The SPC busy status flag is too short to get coverage data.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Gets selected power domain's requested low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t.
+ *
+ * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t.
+ */
+spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+
+    uint32_t val;
+
+    val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT);
+    return (spc_power_domain_low_power_mode_t)val;
+}
+
+/*!
+ * brief Gets Isolation status for each power domains.
+ *
+ * This function gets the status which indicates whether certain
+ * peripheral and the IO pads are in a latched state as a result
+ * of having been in POWERDOWN mode.
+ *
+ * param base SPC peripheral base address.
+ * return Current isolation status for each power domains.
+ */
+uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->SC;
+    return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT);
+}
+
+/*!
+ * brief Configs Low power request output pin.
+ *
+ * This function configs the low power request output pin
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer the spc_LowPower_Request_config_t structure.
+ */
+void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg;
+
+    reg = base->LPREQ_CFG;
+    reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK);
+
+    if (config->enable)
+    {
+        reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) |
+               SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override));
+    }
+    else
+    {
+        reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK;
+    }
+
+    base->LPREQ_CFG = reg;
+}
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t.
+ */
+void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg;
+
+    reg = (base->VDD_CORE_GLITCH_DETECT_SC) &
+          ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK |
+            SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK);
+
+    reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt);
+
+    base->VDD_CORE_GLITCH_DETECT_SC = reg;
+}
+#endif
+
+/*!
+ * brief Set SRAM operate voltage.
+ *
+ * param base SPC peripheral base address.
+ * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage.
+ */
+void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    reg |= SPC_SRAMCTL_VSM(config->operateVoltage);
+
+    base->SRAMCTL = reg;
+
+    if (config->requestVoltageUpdate)
+    {
+        base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK;
+        while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL)
+        {
+            /* Wait until acknowledged */
+            ;
+        }
+        base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK;
+    }
+}
+
+/*!
+ * brief Configs Bandgap mode in Active mode.
+ *
+ * @note To disable bandgap in Active mode:
+ *          1. Disable all LVD's and HVD's in active mode;
+ *          2. Disable Glitch detect;
+ *          3. Configure LDO's and DCDC to low drive strength in active mode;
+ *          4. Invoke this function to disable bandgap in active mode;
+ *      otherwise the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * param base SPC peripheral base address.
+ * param mode The Bandgap mode be selected.
+ *
+ * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode.
+ * retval kStatus_Success Config Bandgap mode in Active power mode successful.
+ */
+status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode)
+{
+    uint32_t reg;
+    uint32_t state;
+
+    reg = base->ACTIVE_CFG;
+
+    if (mode == kSPC_BandgapDisabled)
+    {
+        state = SPC_GetActiveModeVoltageDetectStatus(base);
+
+        /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */
+        if (state != 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+        /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) ==
+            SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+        /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) ==
+            SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+    }
+
+    reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK;
+    reg |= SPC_ACTIVE_CFG_BGMODE(mode);
+
+    base->ACTIVE_CFG = reg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs Bandgap mode in Low Power mode.
+ *
+ * @note To disable Bandgap in Low-power mode:
+ *          1. Disable all LVD's ad HVD's in low power mode;
+ *          2. Disable Glitch detect in low power mode;
+ *          3. Configure LDO's and DCDC to low drive strength in low power mode;
+ *          4. Disable bandgap in low power mode;
+ *      Otherwise, the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * param base SPC peripheral base address.
+ * param mode The Bandgap mode be selected.
+ *
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ * retval kStatus_Success Config Bandgap mode in Low Power power mode successful.
+ */
+status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode)
+{
+    uint32_t reg;
+    uint32_t state;
+
+    reg = base->LP_CFG;
+
+    if (mode == kSPC_BandgapDisabled)
+    {
+        state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base);
+
+        /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */
+        if (state != 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+        if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+        if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+        if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) ==
+            SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+        /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */
+        if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif
+    }
+
+    reg &= ~SPC_LP_CFG_BGMODE_MASK;
+    reg |= SPC_LP_CFG_BGMODE(mode);
+    base->LP_CFG = reg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs CORE voltage detect options.
+ *
+ * This function configs CORE voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_core_voltage_detect_config_t structure.
+ */
+void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U);
+
+    base->VD_CORE_CFG = reg;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+/*!
+ * brief Enables the Core High Voltage Detector in Active mode.
+ *
+ * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in active mode.
+ *          false   -   Disable Core High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable Core High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the Core High Voltage Detector in Low Power mode.
+ *
+ * note If the CORE_LDO high voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each regulator
+ * must not set to low in low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in low power mode.
+ *          false   -   Disable Core High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+
+/*!
+ * brief Enables the Core VDD Low Voltage Detector in Active mode.
+ *
+ * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core LVD.
+ *          true    -   Enable Core Low voltage detector in active mode.
+ *          false   -   Disable Core Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable Core Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the Core Low Voltage Detector in Low Power mode.
+ *
+ * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core Low voltage detector in low power mode.
+ *          false   -   Disable Core Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set system VDD Low-voltage level selection.
+ *
+ * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level
+ * must be done after disabling the System VDD low voltage reset and interrupt.
+ *
+ * @deprecated In latest RM, reserved for all devices, will removed in next release.
+ *
+ * param base SPC peripheral base address.
+ * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details.
+ */
+void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)
+{
+    (void)level;
+    (void)base;
+
+    /*
+    uint32_t reg;
+
+    reg = base->VD_SYS_CFG;
+
+    base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK);
+    reg |= SPC_VD_SYS_CFG_LVSEL(level);
+
+    base->VD_SYS_CFG = reg; */
+}
+
+/*!
+ * brief Configs SYS VDD voltage detect options.
+ *
+ * This function config SYS voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_system_voltage_detect_config_t structure.
+ */
+void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U);
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U);
+
+    base->VD_SYS_CFG = reg;
+
+    (void)(config->level);
+    /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */
+}
+
+/*!
+ * brief Enables the System VDD High Voltage Detector in Active mode.
+ *
+ * note If the System_LDO high voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of
+ * each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in active mode.
+ *          false   -   Disable System High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable System High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD Low Voltage Detector in Active mode.
+ *
+ * note If the System_LDO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System LVD.
+ *          true    -   Enable System Low voltage detector in active mode.
+ *          false   -   Disable System Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable the System Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD High Voltage Detector in Low Power mode.
+ *
+ * note If the System_LDO high voltage detect is enabled in low power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in low power mode.
+ *          false   -   Disable System High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD Low Voltage Detector in Low Power mode.
+ *
+ * note If the System_LDO low voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System Low voltage detector in low power mode.
+ *          false   -   Disable System Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK;
+    }
+
+    return status;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * brief Set IO VDD Low-Voltage level selection.
+ *
+ * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level
+ * must be done after disabling the IO VDD low voltage reset and interrupt.
+ *
+ * param base SPC peripheral base address.
+ * param level IO VDD Low-voltage level selection.
+ */
+void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)
+{
+    uint32_t reg;
+
+    reg = base->VD_IO_CFG;
+
+    base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK);
+    reg |= SPC_VD_IO_CFG_LVSEL(level);
+
+    base->VD_IO_CFG = reg;
+}
+
+/*!
+ * brief Configs IO VDD voltage detect options.
+ *
+ * This function config IO voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_IO_voltage_detect_config_t structure.
+ */
+void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    /* Set trip voltage level. */
+    SPC_SetIOVDDLowVoltageLevel(base, config->level);
+
+    reg = base->VD_IO_CFG;
+    reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK);
+
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U);
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U);
+
+    base->VD_IO_CFG = reg;
+}
+
+/*!
+ * brief Enables the IO VDD High Voltage Detector in Active mode.
+ *
+ * note If the IO high voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength
+ * of each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in active mode.
+ *          false   -   Disable IO High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable IO High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD Low Voltage Detector in Active mode.
+ *
+ * note If the IO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength
+ * of each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in active mode.
+ *          false   -   Disable IO Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable IO Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD High Voltage Detector in Low Power mode.
+ *
+ * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in low power mode.
+ *          false   -   Disable IO High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD Low Voltage Detector in Low Power mode.
+ *
+ * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO Low voltage detector in low power mode.
+ *          false   -   Disable IO Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * brief Configs external voltage domains
+ *
+ * This function configs external voltage domains isolation.
+ *
+ * param base SPC peripheral base address.
+ * param lowPowerIsoMask The mask of external domains isolate enable during low power mode.
+ * param IsoMask The mask of external domains isolate.
+ */
+void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask)
+{
+    uint32_t reg = 0UL;
+
+    reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask);
+    base->EVD_CFG = reg;
+}
+
+/*!
+ * brief Configs Core LDO Regulator in Active mode.
+ *
+ * @note The bandgap must be enabled before invoking this function.
+ * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_Core_LDO_option_t structure.
+ *
+ * retval kStatus_Success Config Core LDO regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function.
+ * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength,
+ *                                                  all LVDs/HVDs must be disabled before invoking this function.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option)
+{
+    assert(option != NULL);
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameters. */
+    /*  1. Bandgap must not be disabled. */
+    if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /*  2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */
+    if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) &&
+        (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+
+    if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage))
+    {
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+        (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength);
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+        (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage);
+    }
+
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+    (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength);
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Voltage level in Active mode.
+ *
+ * @note In active mode, the Core LDO voltage level should only be changed when the
+ *  Core LDO is in normal drive strength.
+ *
+ * @note Update Core LDO voltage level will set Busy flag,
+ *      this function return only when busy flag is cleared by hardware
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * retval kStatus_SPC_CORELDOVoltageSetFail  Core LDO voltage level should only be
+ *                                          changed when the CORE_LDO is in normal drive strength.
+ * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)
+{
+    if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))
+    {
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+        if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength)
+        {
+            return kStatus_SPC_CORELDOVoltageSetFail;
+        }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+        base->ACTIVE_CFG =
+            ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel));
+
+        /*
+         * $Branch Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+        {
+        }
+    }
+    return kStatus_Success;
+}
+
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+/*!
+ * brief Set Core LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_drive_strength_t.
+ *
+ * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful.
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled,
+            core_ldo's drive strength can not set to low.
+ * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_CoreLDO_LowDriveStrength)
+    {
+        /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low.
+         */
+        if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+        }
+    }
+
+    if (driveStrength == kSPC_CoreLDO_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength));
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+/*!
+ * brief Configs CORE LDO Regulator in low power mode
+ *
+ * This function configs CORE LDO Regulator in Low Power mode.
+ * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage
+ * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap
+ * must be programmed to select bandgap enabled.
+ * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE
+ * LDO Drive Strength is set as Normal.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure.
+ * retval kStatus_Success Config Core LDO regulator in power mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option)
+{
+    status_t status = kStatus_Success;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength);
+    if (status == kStatus_Success)
+    {
+        (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Voltage level in Low power mode.
+ *
+ * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the
+ * same value in active and low power mode. Application should take care of this limitation.
+ *
+ * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should
+ * take care of this limitation.
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation.
+ * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)
+{
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+            * $Line Coverage Justification$
+            * $ref spc_c_ref_1$.
+            */
+        return kStatus_SPC_Busy;
+    }
+
+    base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel));
+
+    /*
+        * $Branch Coverage Justification$
+        * $ref spc_c_ref_1$.
+        */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Drive Strength in Low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify drive strength of CORE LDO in low power mode.
+ *
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set
+ *           as low.
+ * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_CoreLDO_LowDriveStrength)
+    {
+        /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to
+         * low.
+         */
+        if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+        }
+    }
+    else
+    {
+        /* To specify normal drive strength, the bandgap must be enabled in low power mode. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength));
+
+    return kStatus_Success;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * brief Configs System LDO VDD Regulator in Active mode.
+ *
+ * This function configs System LDO VDD Regulator in Active mode.
+ * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed
+ * to a value that enable the bandgap.
+ * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will
+ * be ignored.
+ * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD
+ * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal.
+ * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled.
+ * Otherwise it will be fail to regulator to Over Drive Voltage.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure.
+ * retval kStatus_Success Config System LDO regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be
+ * ignored.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option)
+{
+    assert(option != NULL);
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameters before setting registers. */
+    /*  1. To set to low DS, all LVDs/HVDs must be disabled previously. */
+    if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) &&
+        (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+    /* 2. If specify normal drive strength, bandgap must not be disabled. */
+    if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) &&
+        (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /* 3. Must disable system LDO high voltage detector before specifying overdrive voltage. */
+    if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) &&
+        ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL))
+    {
+        return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+    }
+
+    (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength);
+    (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set System LDO Regulator voltage level in Active mode.
+ *
+ * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the
+ * life of chip.
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully.
+ * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying
+ * overdrive voltage.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel)
+{
+    if (voltageLevel == kSPC_SysLDO_OverDriveVoltage)
+    {
+        /* Must disable system LDO high voltage detector before specifying overdrive voltage. */
+        if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set System LDO Regulator Drive Strength in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength  of System LDO Regulator in Active mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in active mode.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_SysLDO_LowDriveStrength)
+    {
+        /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */
+        if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+        }
+    }
+
+    if (driveStrength == kSPC_SysLDO_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs System LDO regulator in low power modes.
+ *
+ * This function configs System LDO regulator in low power modes.
+ * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power
+ * mode must be programmed to a value that enables the Bandgap.
+ * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration
+ * to set System LDO Regulator drive strength as Low will be ignored.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure.
+ *
+ * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option)
+{
+    status_t status;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength);
+
+    return status;
+}
+
+/*!
+ * brief Set System LDO Regulator drive strength in Low Power Mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in low power mode.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_SysLDO_LowDriveStrength)
+    {
+        /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */
+        if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+        }
+    }
+    else
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * brief Configs DCDC VDD Regulator in Active mode.
+ *
+ * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_DCDC_option_t structure.
+ *
+ * retval kStatus_Success Config DCDC regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option)
+{
+    assert(option != NULL);
+    status_t status = kStatus_Success;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength);
+
+    if (status == kStatus_Success)
+    {
+        SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage);
+    }
+
+    /*
+     * $Branch Coverage Justification$
+     * $ref spc_c_ref_1$.
+     */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set DCDC VDD Regulator drive strength in Active mode.
+ *
+ * note To set DCDC drive strength as Normal, the bandgap must be enabled.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully.
+ * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_DCDC_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs DCDC VDD Regulator in Low power modes.
+ *
+ * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed
+ * to a value that enables the Bandgap.
+ * In Deep Power Down mode, DCDC regulator is always turned off.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure.
+ *
+ * retval kStatus_Success Config DCDC regulator in low power mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option)
+{
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameter before setting registers. */
+    if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) &&
+        (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /*
+        1. Configure to desired voltage level.
+        2. Change to low drive strength.
+        3. Configure same voltage level in active mode.
+    */
+    SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage);
+
+    /* Change to desired drive strength. */
+    if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength)
+    {
+        (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength);
+    }
+
+    /*
+     * $Branch Coverage Justification$
+     * $ref spc_c_ref_1$.
+     */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set DCDC VDD Regulator drive strength in Low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully.
+ * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_DCDC_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Config DCDC Burst options
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_DCDC_burst_config_t structure.
+ */
+void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config)
+{
+    assert(config != NULL);
+    uint32_t reg;
+    reg = base->DCDC_CFG;
+    reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK);
+    reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq);
+    reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U);
+    base->DCDC_CFG = reg;
+
+    /* Blocking until previous DCDC burst completed. */
+    while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL)
+    {
+    }
+
+    if ((config->sofwareBurstRequest) || (config->externalBurstRequest))
+    {
+        /* Clear DCDC burst acknowledge flag. */
+        base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK;
+    }
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest);
+
+    if (config->sofwareBurstRequest)
+    {
+        base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK;
+    }
+}
+
+/*!
+ * brief Set the count value of the reference clock.
+ *
+ * This function set the count value of the reference clock to control the frequency
+ * of dcdc refresh when dcdc is configured in Pulse Refresh mode.
+ *
+ * param base SPC peripheral base address.
+ * param count The count value, 16 bit width.
+ */
+void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count)
+{
+    uint32_t reg;
+
+    reg = base->DCDC_BURST_CFG;
+    reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK;
+    reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count);
+
+    base->DCDC_BURST_CFG = reg;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * brief Configs all settings of regulators in Active mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in active mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other low-level functions.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_active_mode_regulators_config_t structure.
+ * retval kStatus_Success Config regulators in Active power mode successful.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed.
+ * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored.
+ * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored.
+ */
+status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base);
+
+    /* Check input parameters */
+    /*  1. Bandgap should not be disabled if any of regulator in normal drive strength or
+            if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */
+    if ((config->bandgapMode == kSPC_BandgapDisabled) &&
+        ((activeModeVDValue != 0UL)
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+         || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+         || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+         || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+         || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+             ))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /*  2. Must disable system LDO high voltage detector before specifying SysLDO to overdrive voltage  */
+    if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) &&
+        (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage))
+    {
+        return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+    /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    /* 5. Core LDO and DCDC should have same voltage level. */
+    if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage)
+    {
+        return kStatus_SPC_CORELDOVoltageWrong;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        return kStatus_SPC_Busy;
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode);
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs regulators in Low Power mode.
+ *
+ * This function provides the method to config all on-chip regulators in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_lowpower_mode_regulators_config_t structure.
+ * retval #kStatus_Success Config regulators in Low power mode successful.
+ * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings.
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config)
+{
+    assert(config != NULL);
+    uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base);
+
+    /* Check input parameters */
+    /*  1. Bandgap should not be disabled if any of regulator in normal drive strength or
+            if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */
+    if ((config->bandgapMode == kSPC_BandgapDisabled) &&
+        ((lpModeVDValue != 0UL)
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+         || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+         || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+         || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+         || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+             ))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+    /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    /* 5. Core LDO and DCDC should have same voltage level. */
+    if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage)
+    {
+        return kStatus_SPC_CORELDOVoltageWrong;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+    base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode);
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+    SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+    SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption);
+
+    return kStatus_Success;
+}
diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.h b/hw/bsp/mcx/drivers/spc/fsl_spc.h
new file mode 100644
index 000000000..69a001098
--- /dev/null
+++ b/hw/bsp/mcx/drivers/spc/fsl_spc.h
@@ -0,0 +1,2433 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SPC_H_
+#define FSL_SPC_H_
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mcx_spc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SPC driver version 2.4.2. */
+#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
+/*! @} */
+
+#define SPC_EVD_CFG_REG_EVDISO_SHIFT   0UL
+#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL
+#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT  16UL
+
+#define SPC_EVD_CFG_REG_EVDISO(x)   ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT)
+#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT)
+#define SPC_EVD_CFG_REG_EVDSTAT(x)  ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT)
+
+#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK))
+#define VDD_CORE_GLITCH_DETECT_SC                             GLITCH_DETECT_SC
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG      SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK               SPC_GLITCH_DETECT_SC_LOCK_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK         SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT              SPC_GLITCH_DETECT_SC_CNT_SELECT
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK                 SPC_GLITCH_DETECT_SC_RE_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE                      SPC_GLITCH_DETECT_SC_RE
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK            SPC_GLITCH_DETECT_SC_TIMEOUT_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT                 SPC_GLITCH_DETECT_SC_TIMEOUT
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK                 SPC_GLITCH_DETECT_SC_IE_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE                      SPC_GLITCH_DETECT_SC_IE
+#endif
+
+/*!
+ * @brief SPC status enumeration.
+ *
+ * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual
+ * to check.
+ */
+enum
+{
+    kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any
+                                                                type of power mode transition. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be
+                                                                                    ignored for LVD/HVD enabled. */
+    kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive
+                                                                    strength setting be ignored for LVD/HVD enabled. */
+#endif                                                                          /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive
+                                                                    voltage failed for SYS LDO HVD must be disabled. */
+    kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U),  /*!< SYS LDO Low driver strength
+                                                                        setting be ignored for LDO LVD/HVD enabled. */
+#endif                                                                             /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+    kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength
+                                                                        setting be ignored for LDO LVD/HVD enabled. */
+    kStatus_SPC_CORELDOVoltageWrong   = MAKE_STATUS(kStatusGroup_SPC, 7U),         /*!< Core LDO voltage is wrong. */
+    kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U),         /*!< Core LDO voltage set fail. */
+    kStatus_SPC_BandgapModeWrong      = MAKE_STATUS(kStatusGroup_SPC, 6U),         /*!< Selected Bandgap Mode wrong. */
+};
+
+/*!
+ * @brief Voltage Detect Status Flags.
+ */
+enum _spc_voltage_detect_flags
+{
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+    kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK,      /*!< IO VDD High-Voltage detect flag. */
+    kSPC_IOVDDLowVoltageDetectFlag  = SPC_VD_STAT_IOVDD_LVDF_MASK,      /*!< IO VDD Low-Voltage detect flag. */
+#endif                                                                  /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+    kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */
+    kSPC_SystemVDDLowVoltageDetectFlag  = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+    kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK,  /*!< Core VDD High-Voltage detect flag. */
+#endif                                                                  /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+    kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK,   /*!< Core VDD Low-Voltage detect flag. */
+};
+
+/*!
+ * @brief SPC power domain isolation status.
+ * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to
+ * check.
+ */
+enum _spc_power_domains
+{
+    kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */
+    kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */
+};
+
+/*!
+ * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes.
+ * @anchor spc_analog_module_control
+ */
+enum _spc_analog_module_control
+{
+    kSPC_controlVref       = 1UL << 0UL,  /*!< Enable/disable VREF in active or low-power modes. */
+    kSPC_controlUsb3vDet   = 1UL << 1UL,  /*!< Enable/disable USB3V_Det in active or low-power modes. */
+    kSPC_controlDac0       = 1UL << 4UL,  /*!< Enable/disable DAC0 in active or low-power modes. */
+    kSPC_controlDac1       = 1UL << 5UL,  /*!< Enable/disable DAC1 in active or low-power modes.  */
+    kSPC_controlDac2       = 1UL << 6UL,  /*!< Enable/disable DAC2 in active or low-power modes. */
+    kSPC_controlOpamp0     = 1UL << 8UL,  /*!< Enable/disable OPAMP0 in active or low-power modes. */
+    kSPC_controlOpamp1     = 1UL << 9UL,  /*!< Enable/disable OPAMP1 in active or low-power modes. */
+    kSPC_controlOpamp2     = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */
+    kSPC_controlCmp0       = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */
+    kSPC_controlCmp1       = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */
+    kSPC_controlCmp2       = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */
+    kSPC_controlCmp0Dac    = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */
+    kSPC_controlCmp1Dac    = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */
+    kSPC_controlCmp2Dac    = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */
+    kSPC_controlAllModules = 0x770773UL,  /*!< Enable/disable all modules in active or low-power modes. */
+};
+
+/*!
+ * @brief The enumeration of spc power domain, the connected power domain is chip specific, please refer to chip's RM
+ * for details.
+ */
+typedef enum _spc_power_domain_id
+{
+    kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */
+    kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */
+} spc_power_domain_id_t;
+
+/*!
+ * @brief The enumeration of Power domain's low power mode.
+ */
+typedef enum _spc_power_domain_low_power_mode
+{
+    kSPC_SleepWithSYSClockRunning     = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */
+    kSPC_DeepSleepWithSysClockOff     = 1U, /*!< Power domain request deep sleep mode with system clock off. */
+    kSPC_PowerDownWithSysClockOff     = 2U, /*!< Power domain request power down mode with system clock off. */
+    kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */
+} spc_power_domain_low_power_mode_t;
+
+/*!
+ * @brief SPC low power request output pin polarity.
+ */
+typedef enum _spc_lowPower_request_pin_polarity
+{
+    kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Request Pin. */
+    kSPC_LowTruePolarity  = 0x1U, /*!< Control the Low Polarity of the Low Power Request Pin. */
+} spc_lowpower_request_pin_polarity_t;
+
+/*!
+ * @brief SPC low power request output override.
+ */
+typedef enum _spc_lowPower_request_output_override
+{
+    kSPC_LowPowerRequestNotForced  = 0x0U, /*!< Not Forced. */
+    kSPC_LowPowerRequestReserved   = 0x1U, /*!< Reserved. */
+    kSPC_LowPowerRequestForcedLow  = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */
+    kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */
+} spc_lowpower_request_output_override_t;
+
+/*!
+ * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_bandgap_mode
+{
+    kSPC_BandgapDisabled              = 0x0U, /*!< Bandgap disabled. */
+    kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */
+    kSPC_BandgapEnabledBufferEnabled  = 0x2U, /*!< Bandgap enabled with Buffer enabled. */
+    kSPC_BandgapReserved              = 0x3U, /*!< Reserved. */
+} spc_bandgap_mode_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode.
+ *
+ * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes.
+ */
+typedef enum _spc_dcdc_voltage_level
+{
+    kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention
+                                           Voltage(Only supportedin low power modes) */
+    kSPC_DCDC_MidVoltage       = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */
+    kSPC_DCDC_NormalVoltage    = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */
+    kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */
+} spc_dcdc_voltage_level_t;
+
+/*!
+ * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode.
+ *
+ * @note Different drive strength differ in these DCDC characteristics:
+ *              Maximum load current
+ *              Quiescent current
+ *              Transient response.
+ */
+typedef enum _spc_dcdc_drive_strength
+{
+    kSPC_DCDC_PulseRefreshMode = 0x0U,    /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode,
+                                           * This enum member is only useful for Low Power Mode config, please
+                                           * note that pulse refresh mode is invalid in SLEEP mode.
+                                           */
+    kSPC_DCDC_LowDriveStrength    = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */
+    kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */
+} spc_dcdc_drive_strength_t;
+#endif                                    /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief SYS LDO regulator voltage level enumeration in Active mode.
+ */
+typedef enum _spc_sys_ldo_voltage_level
+{
+    kSPC_SysLDO_NormalVoltage    = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */
+    kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */
+} spc_sys_ldo_voltage_level_t;
+
+/*!
+ * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_sys_ldo_drive_strength
+{
+    kSPC_SysLDO_LowDriveStrength    = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */
+    kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */
+} spc_sys_ldo_drive_strength_t;
+#endif                                      /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+/*!
+ * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_core_ldo_voltage_level
+{
+    kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use
+                                            #kSPC_Core_LDO_RetentionVoltage as instead. */
+    kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that
+                                           only useful in low power modes and not all devices support this options
+                                           please refer to devices' RM for details. */
+    kSPC_CoreLDO_MidDriveVoltage  = 0x1U,  /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */
+    kSPC_CoreLDO_NormalVoltage    = 0x2U,  /*!< Core LDO VDD regulator regulate to Normal Voltage. */
+    kSPC_CoreLDO_OverDriveVoltage = 0x3U,  /*!< Core LDO VDD regulator regulate to overdrive Voltage. */
+} spc_core_ldo_voltage_level_t;
+
+/*!
+ * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode.
+ */
+typedef enum _spc_core_ldo_drive_strength
+{
+    kSPC_CoreLDO_LowDriveStrength    = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */
+    kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */
+} spc_core_ldo_drive_strength_t;
+
+/*!
+ * @brief IO VDD Low-Voltage Level Select.
+ */
+typedef enum _spc_low_voltage_level_select
+{
+    kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */
+    kSPC_LowVoltageSafeLevel   = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */
+
+    kSPC_LowVoltageHighRange = 0x0U,   /*!< High range LVD threshold. */
+    kSPC_LowVoltageLowRange  = 0x1U,  /*!< Low range LVD threshold. */
+} spc_low_voltage_level_select_t;
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core.
+ */
+typedef enum _spc_vdd_core_glitch_ripple_counter_select
+{
+    kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+} spc_vdd_core_glitch_ripple_counter_select_t;
+#endif
+
+/*!
+ * @brief The list of the operating voltage for the SRAM's read/write timing margin.
+ */
+typedef enum _spc_sram_operate_voltage
+{
+    kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */
+    kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */
+    kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */
+} spc_sram_operate_voltage_t;
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief The configuration of VDD Core glitch detector.
+ */
+typedef struct _spc_vdd_core_glitch_detector_config
+{
+    spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */
+    uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial
+                              glitch is detected. */
+    bool enableReset;          /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */
+    bool enableInterrupt;      /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */
+} spc_vdd_core_glitch_detector_config_t;
+#endif
+
+typedef struct _spc_sram_voltage_config
+{
+    spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's
+                                                     read/write timing margin.  */
+    bool requestVoltageUpdate;                 /*!< Used to control whether request an SRAM trim value change. */
+} spc_sram_voltage_config_t;
+
+/*!
+ * @brief Low Power Request output pin configuration.
+ */
+typedef struct _spc_lowpower_request_config
+{
+    bool enable;                                     /*!< Low Power Request Output enable. */
+    spc_lowpower_request_pin_polarity_t polarity;    /*!< Low Power Request Output pin polarity select. */
+    spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */
+} spc_lowpower_request_config_t;
+
+/*!
+ * @brief Core LDO regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_core_ldo_option
+{
+    spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+    spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength
+                                                            selection in Active mode */
+#endif                                                  /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+} spc_active_mode_core_ldo_option_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief System LDO regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_sys_ldo_option
+{
+    spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */
+    spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength
+                                                            selection in Active mode. */
+} spc_active_mode_sys_ldo_option_t;
+#endif                                                /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_dcdc_option
+{
+    spc_dcdc_voltage_level_t DCDCVoltage;        /*!< DCDC Regulator Voltage Level selection in Active mode. */
+    spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */
+} spc_active_mode_dcdc_option_t;
+#endif                                           /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * @brief Core LDO regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_core_ldo_option
+{
+    spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */
+    spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength
+                                                            selection in Low Power mode */
+} spc_lowpower_mode_core_ldo_option_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief System LDO regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_sys_ldo_option
+{
+    spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength
+                                                            selection in Low Power mode. */
+} spc_lowpower_mode_sys_ldo_option_t;
+#endif                                                /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_dcdc_option
+{
+    spc_dcdc_voltage_level_t DCDCVoltage;        /*!< DCDC Regulator Voltage Level selection in Low Power mode. */
+    spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */
+} spc_lowpower_mode_dcdc_option_t;
+
+/*!
+ * @brief DCDC Burst configuration.
+ * @deprecated Do not recommend to use this structure.
+ */
+typedef struct _spc_dcdc_burst_config
+{
+    bool sofwareBurstRequest;  /*!< Enable/Disable DCDC Software Burst Request. */
+    bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */
+    bool stabilizeBurstFreq;   /*!< Enable/Disable DCDC frequency stabilization. */
+    uint8_t freq;              /*!< The frequency of the current burst.  */
+} spc_dcdc_burst_config_t;
+#endif                         /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * @brief CORE/SYS/IO VDD Voltage Detect options.
+ */
+typedef struct _spc_voltage_detect_option
+{
+    bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */
+    bool HVDResetEnable;     /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */
+    bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */
+    bool LVDResetEnable;     /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */
+} spc_voltage_detect_option_t;
+
+/*!
+ * @brief Core Voltage Detect configuration.
+ */
+typedef struct _spc_core_voltage_detect_config
+{
+    spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */
+} spc_core_voltage_detect_config_t;
+
+/*!
+ * @brief System Voltage Detect Configuration.
+ */
+typedef struct _spc_system_voltage_detect_config
+{
+    spc_voltage_detect_option_t option;   /*!< System VDD Voltage Detect option. */
+    spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */
+} spc_system_voltage_detect_config_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * @brief IO Voltage Detect Configuration.
+ */
+typedef struct _spc_io_voltage_detect_config
+{
+    spc_voltage_detect_option_t option;   /*!< IO VDD Voltage Detect option. */
+    spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */
+} spc_io_voltage_detect_config_t;
+#endif                                    /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * @brief Active mode configuration.
+ */
+typedef struct _spc_active_mode_regulators_config
+{
+    spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */
+#endif           /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */
+#endif                                        /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    spc_active_mode_sys_ldo_option_t SysLDOOption;   /*!< Specify System LDO configurations in active mode. */
+#endif                                               /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+    spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */
+} spc_active_mode_regulators_config_t;
+
+/*!
+ * @brief Low Power Mode configuration.
+ */
+typedef struct _spc_lowpower_mode_regulators_config
+{
+    bool lpIREF;                    /*!< Enable/disable low power IREF in low power modes. */
+    spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */
+#endif           /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+    bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */
+#endif            /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */
+#endif                                          /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    spc_lowpower_mode_sys_ldo_option_t SysLDOOption;   /*!< Specify system LDO configurations in low power modes. */
+#endif                                                 /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+    spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */
+} spc_lowpower_mode_regulators_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name SPC Status
+ * @{
+ */
+/*!
+ * @brief Gets Isolation status for each power domains.
+ *
+ * This function gets the status which indicates whether certain
+ * peripheral and the IO pads are in a latched state as a result
+ * of having been in POWERDOWN mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Current isolation status for each power domains. See @ref _spc_power_domains for details.
+ */
+uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base);
+
+/*!
+ * @brief Clears peripherals and I/O pads isolation flags for each power domains.
+ *
+ * This function clears peripherals and I/O pads isolation flags for each power domains.
+ * After recovering from the POWERDOWN mode, user must invoke this function to release the
+ * I/O pads and certain peripherals to their normal run mode state. Before invoking this
+ * function, user must restore chip configuration in particular pin configuration for enabled
+ * WUU wakeup pins.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base)
+{
+    base->SC |= SPC_SC_ISO_CLR_MASK;
+}
+
+/*!
+ * @brief Gets SPC busy status flag.
+ *
+ * This function gets SPC busy status flag. When SPC executing any type of power mode
+ * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set
+ * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level
+ * in ACTIVE mode, the SPC busy status flag is set and this function return true.
+ *
+ * @param base SPC peripheral base address.
+ * @return Ack busy flag.
+ *          true    -   SPC is busy.
+ *          false   -   SPC is not busy.
+ */
+static inline bool SPC_GetBusyStatusFlag(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_BUSY_MASK) != 0UL);
+}
+
+/*!
+ * @brief Checks system low power request.
+ *
+ * @note Only when all power domains request low power mode entry, the result of this function is true. That means when
+ * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register.
+ *
+ * @param base SPC peripheral base address.
+ * @return The system low power request check result.
+ *       - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode
+ *                 configuration are based on the LP_CFG configuration register.
+ *       - \b false SPC in active mode and ACTIVE_CFG register control system power supply.
+ */
+static inline bool SPC_CheckLowPowerReqest(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK);
+}
+
+/*!
+ * @brief Clears system low power request, set SPC in active mode.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_ClearLowPowerRequest(SPC_Type *base)
+{
+    base->SC |= SPC_SC_SPC_LP_REQ_MASK;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT)
+/*!
+ * @brief Checks whether the power switch is on.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval true The power switch is on.
+ * @retval false The power switch is off.
+ */
+static inline bool SPC_CheckSwitchState(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL);
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */
+
+/*!
+ * @brief Gets selected power domain's requested low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ *
+ * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t.
+ */
+spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId);
+
+/*!
+ * @brief Checks power domain's low power request.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ * @return The result of power domain's low power request.
+ *            - \b true The selected power domain requests low power mode entry.
+ *            - \b false The selected power domain does not request low power mode entry.
+ */
+static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+    return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) ==
+            SPC_PD_STATUS_PWR_REQ_STATUS_MASK);
+}
+
+/*!
+ * @brief Clears selected power domain's low power request flag.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ */
+static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+    base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK;
+}
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG)
+/*!
+ * @name SRAM Retention LDO Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V.
+ *
+ * @param base SPC peripheral base address.
+ * @param trimValue Reference voltage trim value.
+ */
+static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue)
+{
+    base->SRAMRETLDO_REFTRIM =
+        ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue));
+}
+
+/*!
+ * @brief Enables/disables SRAM retention LDO.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable SRAM LDO :
+ *          - \b true Enable SRAM LDO;
+ *          - \b false Disable SRAM LDO.
+ */
+static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK;
+    }
+    else
+    {
+        base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK;
+    }
+}
+
+/*!
+ * @brief
+ *
+ * @todo Need to check.
+ *
+ * @param base SPC peripheral base address.
+ * @param mask The OR'ed value of SRAM Array.
+ */
+static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask)
+{
+    base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask);
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */
+
+/*!
+ * @name Low Power Request configuration
+ * @{
+ */
+/*!
+ * @brief Configs Low power request output pin.
+ *
+ * This function config the low power request output pin
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer the @ref spc_lowpower_request_config_t structure.
+ */
+void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config);
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG)
+/*!
+ * @name Integrated Power Switch Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the integrated power switch manually.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable the integrated power switch:
+ *             - \b true Enable the integrated power switch;
+ *             - \b false Disable the integrated power switch.
+ */
+static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK);
+    }
+    else
+    {
+        base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK);
+    }
+}
+
+/*!
+ * @brief Enables/disables the integrated power switch automatically.
+ *
+ * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low
+ * power modes:
+ * @code
+ *   SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true);
+ * @endcode
+ *
+ * @param base SPC peripheral base address.
+ * @param sleepGate Enable the integrated power switch when chip enter low power modes:
+ *          - \b true SPC asserts an output pin at low-power entry to power-gate the switch;
+ *          - \b false SPC does not assert an output pin at low-power entry to power-gate the switch.
+ * @param wakeupUngate Enables the switch after wake-up from low power modes:
+ *          - \b true SPC asserts an output pin at low-power exit to power-ungate the switch;
+ *          - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch.
+ */
+static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate)
+{
+    uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK));
+
+    tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate);
+
+    base->CFG = tmp32;
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @name VDD Core Glitch Detector Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t.
+ */
+void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config);
+
+/*!
+ * @brief Checks selected 4-bit glitch ripple counter's output.
+ *
+ * @param base SPC peripheral base address.
+ * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t.
+ *
+ * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings.
+ * @retval false The selected ripple counter output is 0.
+ */
+
+static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base,
+                                                      spc_vdd_core_glitch_ripple_counter_select_t rippleCounter)
+{
+    return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) ==
+            SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)));
+}
+
+/*!
+ * @brief Clears output of selected glitch ripple counter.
+ *
+ * @param base SPC peripheral base address.
+ * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t.
+ */
+static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base,
+                                                      spc_vdd_core_glitch_ripple_counter_select_t rippleCounter)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC |=
+        SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter));
+}
+
+/*!
+ * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK;
+}
+
+/*!
+ * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK;
+}
+
+/*!
+ * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable.
+ * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable.
+ */
+static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base)
+{
+    return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL);
+}
+
+/*! @} */
+#endif
+
+/*!
+ * @name SRAM Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Set SRAM operate voltage.
+ *
+ * @param base SPC peripheral base address.
+ * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage.
+ */
+void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config);
+
+/*! @} */
+
+/*!
+ * @name Active Mode configuration
+ * @{
+ */
+
+/*!
+ * @brief Gets the Bandgap mode in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration.
+ */
+static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base)
+{
+    return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >>
+                                          SPC_ACTIVE_CFG_BGMODE_SHIFT);
+}
+
+/*!
+ * @brief Gets all voltage detectors status in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return All voltage detectors status in Active mode.
+ */
+static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base)
+{
+    uint32_t state;
+    state = base->ACTIVE_CFG &
+            (
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+                SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK |
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+                SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+                | SPC_ACTIVE_CFG_CORE_HVDE_MASK
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+            );
+    return state;
+}
+
+/*!
+ * @brief Configs Bandgap mode in Active mode.
+ *
+ * @note To disable bandgap in Active mode:
+ *          1. Disable all LVD's and HVD's in active mode;
+ *          2. Disable Glitch detect;
+ *          3. Configure LDO's and DCDC to low drive strength in active mode;
+ *          4. Invoke this function to disable bandgap in active mode;
+ *      otherwise the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * @param base SPC peripheral base address.
+ * @param mode The Bandgap mode be selected.
+ *
+ * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode.
+ * @retval #kStatus_Success Config Bandgap mode in Active power mode successful.
+ */
+status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+/*!
+ * @brief Enables/Disable the CMP Bandgap Buffer in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference voltage to CMP.
+ */
+static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+/*!
+ * @brief Sets the delay when the regulators change voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param delay The number of SPC timer clock cycles.
+ */
+static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay)
+{
+    base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay);
+}
+
+/*!
+ * @brief Configs all settings of regulators in Active mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in active mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_active_mode_regulators_config_t structure.
+ *
+ * @retval #kStatus_Success Config regulators in Active power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to
+ *                                                  System VDD HVD is not disabled.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function.
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config);
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Disables/Enables VDD Core Glitch Detect in Active mode.
+ *
+ * @note State of glitch detect disable feature will be ignored if bandgap is disabled and
+ * glitch detect hardware will be forced to OFF state.
+ *
+ * @param base SPC peripheral base address.
+ * @param disable Used to disable/enable VDD Core Glitch detect feature.
+ *         - \b true Disable VDD Core Low Voltage detect;
+ *         - \b false Enable VDD Core Low Voltage detect.
+ */
+static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable)
+{
+    if (disable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+}
+
+/*!
+ * @brief Check if Glitch detect hardware is enabled in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Indicate if Glitch detector is enabled.
+ */
+static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base)
+{
+    if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+
+/*!
+ * @brief Enables analog modules in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value
+ * of @ref spc_analog_module_control.
+ */
+static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Disables analog modules in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value
+ * of @ref spc_analog_module_control.
+ */
+static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Gets enabled analog modules that enabled in active mode.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @return The mask of enabled analog modules that enabled in active mode.
+ */
+static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base)
+{
+    return base->ACTIVE_CFG1;
+}
+
+/*! @} */
+
+/*!
+ * @name Low Power mode configuration
+ * @{
+ */
+
+/*!
+ * @brief Gets the Bandgap mode in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration.
+ */
+static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base)
+{
+    return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT);
+}
+
+/*!
+ * @brief Gets the status of all voltage detectors in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return The status of all voltage detectors in low power mode.
+ */
+static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base)
+{
+    uint32_t state;
+    state = base->LP_CFG & (
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+                               SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK |
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+                               SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+                               | SPC_LP_CFG_CORE_HVDE_MASK
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+                           );
+    return state;
+}
+
+/*!
+ * @brief Enables/Disables Low Power IREF in low power modes.
+ *
+ * This function enables/disables Low Power IREF. Low Power IREF can only get
+ * disabled in Deep power down mode. In other low power modes, the Low Power IREF
+ * is always enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Low Power IREF.
+ *          true    -   Enable Low Power IREF for Low Power modes.
+ *          false   -   Disable Low Power IREF for Deep Power Down mode.
+ */
+static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK;
+    }
+}
+
+/*!
+ * @brief Configs Bandgap mode in Low Power mode.
+ *
+ * @note To disable Bandgap in Low-power mode:
+ *          1. Disable all LVD's ad HVD's in low power mode;
+ *          2. Disable Glitch detect in low power mode;
+ *          3. Configure LDO's and DCDC to low drive strength in low power mode;
+ *          4. Disable bandgap in low power mode;
+ *      Otherwise, the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * @param base SPC peripheral base address.
+ * @param mode The Bandgap mode be selected.
+ *
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful.
+ */
+status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT)
+/*!
+ * @brief Enables/disables SRAM_LDO deep power low power IREF.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable low power IREF :
+ *        - \b true: Low Power IREF is enabled ;
+ *        - \b false: Low Power IREF is disabled for power saving.
+ */
+static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+/*!
+ * @brief Enables/Disables CMP Bandgap Buffer.
+ *
+ * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off
+ * in Deep Power Down mode.
+ *
+ * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference Voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference Voltage to CMP.
+ */
+static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/Disables CMP Bandgap Buffer.
+ *
+ * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off
+ * in Deep Power Down mode.
+ *
+ * @deprecated No longer used.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference Voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference Voltage to CMP.
+ */
+static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+/*!
+ * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes.
+ *
+ * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the
+ * external input CORE VDD to a lower voltage level to reduce internal leakage.
+ * IVS is invalid in Sleep or Deep power down mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IVS.
+ *          true    -   enable CORE VDD IVS in Power Down mode.
+ *          false   -   disable CORE VDD IVS in Power Down mode.
+ */
+static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+
+/*!
+ * @brief Sets the delay when exit the low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes.
+ */
+static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay)
+{
+    base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay);
+}
+
+/*!
+ * @brief Configs all settings of regulators in Low power mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in low power mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_lowpower_mode_regulators_config_t structure.
+ * @retval #kStatus_Success Config regulators in Low power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config);
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Disable/Enable VDD Core Glitch Detect in low power mode.
+ *
+ * @note State of glitch detect disable feature will be ignored if bandgap is disabled and
+ * glitch detect hardware will be forced to OFF state.
+ *
+ * @param base SPC peripheral base address.
+ * @param disable Used to disable/enable VDD Core Glitch detect feature.
+ *         - \b true Disable VDD Core Low Voltage detect;
+ *         - \b false Enable VDD Core Low Voltage detect.
+ */
+static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable)
+{
+    if (disable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+}
+
+/*!
+ * @brief Check if Glitch detect hardware is enabled in low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Indicate if Glitch detector is enabled.
+ */
+static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base)
+{
+    if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif
+
+/*!
+ * @brief Enables analog modules in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value
+                    of @ref spc_analog_module_control.
+ */
+static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Disables analog modules in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value
+                    of @ref spc_analog_module_control.
+ */
+static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Gets enabled analog modules that enabled in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @return The mask of enabled analog modules that enabled in low power modes.
+ */
+static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base)
+{
+    return base->LP_CFG1;
+}
+
+/*! @} */
+
+/*!
+ * @name Voltage Detect Status
+ * @{
+ */
+/*!
+ * @brief Get Voltage Detect Status Flags.
+ *
+ * @param base SPC peripheral base address.
+ * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details.
+ */
+static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base)
+{
+    return (uint8_t)(base->VD_STAT);
+}
+
+/*!
+ * @brief Clear Voltage Detect Status Flags.
+ *
+ * @param base SPC peripheral base address.
+ * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details.
+ */
+static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask)
+{
+    base->VD_STAT |= mask;
+}
+
+/*! @} */
+
+/*!
+ * @name Voltage Detect configuration for Core voltage domain.
+ * @{
+ */
+
+/*!
+ * @brief Configs CORE voltage detect options.
+ *
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_core_voltage_detect_config_t structure.
+ */
+void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config);
+
+/*!
+ * @brief Locks Core voltage detect reset setting.
+ *
+ * This function locks core voltage detect reset setting. After invoking this function
+ * any configuration of Core voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlocks Core voltage detect reset setting.
+ *
+ * This function unlocks core voltage detect reset setting. If locks the Core
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the Core Low Voltage Detector in Active mode.
+ *
+ * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core LVD.
+ *          true    -   Enable Core Low voltage detector in active mode.
+ *          false   -   Disable Core Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode.
+ *
+ * This function enables/disables the Core Low Voltage Detector.
+ * If enabled the Core Low Voltage detector. The Bandgap mode in
+ * low power mode must be programmed so that Bandgap is enabled.
+ *
+ * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core Low voltage detector in low power mode.
+ *          false   -   Disable Core Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+/*!
+ * @brief Enables/Disables the Core High Voltage Detector in Active mode.
+ *
+ * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in active mode.
+ *          false   -   Disable Core High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the Core High Voltage Detector in Low Power mode.
+ *
+ * This function enables/disables the Core High Voltage Detector.
+ * If enabled the Core High Voltage detector. The Bandgap mode in
+ * low power mode must be programmed so that Bandgap is enabled.
+ *
+ * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in low power mode.
+ *          false   -   Disable Core High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+
+/*! @} */
+
+/*!
+ * @name Voltage detect configuration for System Voltage domain
+ * @{
+ */
+/*!
+ * @brief Set system VDD Low-voltage level selection.
+ *
+ * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level
+ * must be done after disabling the System VDD low voltage reset and interrupt.
+ *
+ * @deprecated In latest RM, reserved for all devices, will removed in next release.
+ *
+ * @param base SPC peripheral base address.
+ * @param level System VDD Low-Voltage level selection.
+ */
+void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level);
+
+/*!
+ * @brief Configs SYS voltage detect options.
+ *
+ * This function config SYS voltage detect options.
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_system_voltage_detect_config_t structure.
+ */
+void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config);
+
+/*!
+ * @brief Lock System voltage detect reset setting.
+ *
+ * This function locks system voltage detect reset setting. After invoking this function
+ * any configuration of System Voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlock System voltage detect reset setting.
+ *
+ * This function unlocks system voltage detect reset setting. If locks the System
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the System High Voltage Detector in Active mode.
+ *
+ * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in active mode.
+ *          false   -   Disable System High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disable the System Low Voltage Detector in Active mode.
+ *
+ * @note If the System_LDO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System LVD.
+ *          true    -   Enable System Low voltage detector in active mode.
+ *          false   -   Disable System Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the System High Voltage Detector in Low Power mode.
+ *
+ * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note
+ * that the bandgap must be enabled and the drive strength of each regulator must
+ * not set to low in Low Power  mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in low power mode.
+ *          false   -   Disable System High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the System Low Voltage Detector in Low Power mode.
+ *
+ * @note If the System_LDO low voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System Low voltage detector in low power mode.
+ *          false   -   Disable System Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * @name Voltage detect configuration for IO voltage domain
+ * @{
+ */
+/*!
+ * @brief Set IO VDD Low-Voltage level selection.
+ *
+ * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level
+ * must be done after disabling the IO VDD low voltage reset and interrupt.
+ *
+ * @param base SPC peripheral base address.
+ * @param level IO VDD Low-voltage level selection.
+ */
+void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level);
+
+/*!
+ * @brief Configs IO voltage detect options.
+ *
+ * This function config IO voltage detect options.
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_voltage_detect_config_t structure.
+ */
+void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config);
+
+/*!
+ * @brief Lock IO Voltage detect reset setting.
+ *
+ * This function locks IO voltage detect reset setting. After invoking this function
+ * any configuration of system voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlock IO voltage detect reset setting.
+ *
+ * This function unlocks IO voltage detect reset setting. If locks the IO
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the IO High Voltage Detector in Active mode.
+ *
+ * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in active mode.
+ *          false   -   Disable IO High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO Low Voltage Detector in Active mode.
+ *
+ * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in active mode.
+ *          false   -   Disable IO Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable IO Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO High Voltage Detector in Low Power mode.
+ *
+ * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in low power mode.
+ *          false   -   Disable IO High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode.
+ *
+ * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in low power mode.
+ *          false   -   Disable IO Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*! @} */
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * @name External Voltage domains configuration
+ * @{
+ */
+/*!
+ * @brief Configs external voltage domains
+ *
+ * This function configs external voltage domains isolation.
+ *
+ * @param base SPC peripheral base address.
+ * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference
+ * Manual for the Bitmap.
+ * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap.
+ */
+void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask);
+
+/*!
+ * @brief Gets External Domains status.
+ *
+ * @param base SPC peripheral base address.
+ * @return The status of each external domain.
+ */
+static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base)
+{
+    return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT);
+}
+
+/*! @} */
+
+/*!
+ * @name Low Level APIs To Set CORE LDO Regulator
+ * @{
+ */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG)
+/*!
+ * @brief Enable/Disable Core LDO regulator.
+ *
+ * @note The CORE LDO enable bit is write-once.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CORE LDO Regulator.
+ *          true   -   Enable CORE LDO Regulator.
+ *          false  -   Disable CORE LDO Regulator.
+ */
+static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If CORE_LDO is disabled, all RAMs data will powered off.
+         */
+        base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \
+     FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT)
+/*!
+ * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down.
+ *
+ * @note This function only useful when enabled the CORE LDO Regulator.
+ *
+ * @param base SPC peripheral base address.
+ * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode.
+ *          true    -   CORE LDO Regulator will discharge in Deep Power Down mode.
+ *          false   -   CORE LDO Regulator will not discharge in Deep Power Down mode.
+ */
+static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown)
+{
+    if (pulldown)
+    {
+        base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK;
+    }
+    else
+    {
+        base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */
+
+/*!
+ * @brief Configs Core LDO Regulator in Active mode.
+ *
+ * @note The bandgap must be enabled before invoking this function.
+ * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_core_ldo_option_t structure.
+ *
+ * @retval kStatus_Success Config Core LDO regulator in Active power mode successful.
+ * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function.
+ * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength,
+ *                                                  all LVDs/HVDs must be disabled before invoking this function.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option);
+
+/*!
+ * @brief Set Core LDO Regulator Voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * @note In active mode, the Core LDO voltage level should only be changed when the
+ *  Core LDO is in normal drive strength.
+ *
+ * @note Update Core LDO voltage level will set Busy flag,
+ *      this function return only when busy flag is cleared by hardware
+ *
+ * @retval kStatus_SPC_CORELDOVoltageSetFail  The drive strength of Core LDO is not normal.
+ * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Gets CORE LDO Regulator Voltage level.
+ *
+ * This function returns the voltage level of CORE LDO Regulator in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration.
+ */
+static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base)
+{
+    return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >>
+                                                    SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+/*!
+ * @brief Set Core LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled,
+            core_ldo's drive strength can not set to low.
+ * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t.
+ */
+static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base)
+{
+    return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >>
+                                                     SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT);
+}
+#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+/*!
+ * @brief Configs CORE LDO Regulator in low power mode
+ *
+ * This function configs CORE LDO Regulator in Low Power mode.
+ * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage
+ * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap
+ * must be programmed to select bandgap enabled.
+ * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE
+ * LDO Drive Strength set as Normal.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config Core LDO regulator in power mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option);
+
+/*!
+ * @brief Set Core LDO VDD Regulator Voltage level in Low power mode.
+ *
+ * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power
+ *  mode must be same.
+ * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as
+ * Normal.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same.
+ * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful.
+ * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @return The CORE LDO VDD Regulator's voltage level.
+ */
+static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base)
+{
+    return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >>
+                                                     SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT));
+}
+
+/*!
+ * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify drive strength of CORE LDO in low power mode.
+ *
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set
+ *           as low.
+ * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Gets CORE LDO VDD Drive Strength for Low Power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @return The CORE LDO's VDD Drive Strength.
+ */
+static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base)
+{
+    return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >>
+                                                     SPC_LP_CFG_CORELDO_VDD_DS_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @name Low Level APIs To Set System LDO Regulator
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable System LDO regulator.
+ *
+ * @note The SYSTEM LDO enable bit is write-once.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System LDO Regulator.
+ *          true     -   Enable System LDO Regulator.
+ *          false    -    Disable System LDO Regulator.
+ */
+static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If SYSTEM_LDO is disabled, may cause some unexpected issues.
+         */
+        base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Enable/Disable current sink feature of System LDO Regulator.
+ *
+ * @param base SPC peripheral base address.
+ * @param sink Enable/Disable current sink feature.
+ *          true    -   Enable current sink feature of System LDO Regulator.
+ *          false   -   Disable current sink feature of System LDO Regulator.
+ */
+static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink)
+{
+    if (sink)
+    {
+        base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK;
+    }
+    else
+    {
+        base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK;
+    }
+}
+
+/*!
+ * @brief Configs System LDO VDD Regulator in Active mode.
+ *
+ * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed
+ * to a value that enables the bandgap.
+ * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will
+ * be ignored.
+ * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD
+ * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal.
+ * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be
+ * disabled. Otherwise it will be fail to regulator to Over Drive Voltage.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config System LDO regulator in Active power mode successful.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive
+ * voltage.
+ * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be
+ * ignored.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option);
+
+/*!
+ * @brief Set System LDO Regulator voltage level in Active mode.
+ *
+ * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the
+ * life of chip.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying
+ * overdrive voltage.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Get System LDO Regulator voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t.
+ */
+static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >>
+                                                   SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT);
+}
+
+/*!
+ * @brief Set System LDO Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength  of System LDO Regulator in Active mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in active mode.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get System LDO Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t.
+ */
+static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >>
+                                                    SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT);
+}
+
+/*!
+ * @brief Configs System LDO regulator in low power modes.
+ *
+ * This function configs System LDO regulator in low power modes.
+ * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power
+ * mode must be programmed to a value that enables the Bandgap.
+ * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration
+ * to set System LDO Regulator drive strength as Low will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option);
+
+/*!
+ * @brief Set System LDO Regulator drive strength in Low Power Mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in low power mode.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get System LDO Regulator drive strength in Low Power Mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t.
+ */
+static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >>
+                                                    SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT);
+}
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @name Low Level APIs To Set DCDC Regulator
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable DCDC Regulator.
+ *
+ * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable DCDC Regulator.
+ *          true    -   Enable DCDC Regulator.
+ *          false   -   Disable DCDC Regulator.
+ */
+static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If DCDC is disabled, all RAMs data will powered off.
+         */
+        base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Config DCDC Burst options
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_dcdc_burst_config_t structure.
+ */
+void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config);
+
+/*!
+ * @brief Trigger a software burst request to DCDC.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base)
+{
+    /* Blocking until previous DCDC burst completed. */
+    while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL)
+    {
+    }
+
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK;
+}
+
+/*!
+ * @brief Check if burst acknowledge flag is asserted.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval false DCDC burst not complete.
+ * @retval true DCDC burst complete.
+ */
+static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base)
+{
+    return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL);
+}
+
+/*!
+ * @brief Clear DCDC busrt acknowledge flag.
+ *
+ * @param base SPC periphral base address.
+ */
+static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base)
+{
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK;
+}
+
+/*!
+ * @brief Set the count value of the reference clock to configure the period of DCDC not active.
+ *
+ * @note This function is only useful when DCDC's drive strength is set as pulse refresh.
+ * @note The pulse duration(time between on and off) is: reference clock period * (count + 2).
+ *
+ * @param base SPC peripheral base address.
+ * @param count The count value, 16 bit width.
+ */
+void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN)
+/*!
+ * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable bleed resistor.
+ */
+static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK;
+    }
+    else
+    {
+        base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */
+
+/*!
+ * @brief Configs DCDC_CORE Regulator in Active mode.
+ *
+ * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_dcdc_option_t structure.
+ *
+ * @retval #kStatus_Success Config DCDC regulator in Active power mode successful.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option);
+
+/*!
+ * @brief Set DCDC_CORE Regulator voltage level in Active mode.
+ *
+ * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)
+{
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel);
+}
+
+/*!
+ * @brief Get DCDC_CORE Regulator voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >>
+                                                 SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT));
+}
+
+/*!
+ * @brief Set DCDC_CORE Regulator drive strength in Active mode.
+ *
+ * @note To set DCDC drive strength as Normal, the bandgap must be enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get DCDC_CORE Regulator drive strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ */
+static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >>
+                                                  SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT));
+}
+
+/*!
+ * @brief Configs DCDC_CORE Regulator in Low power modes.
+ *
+ * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed
+ * to a value that enables the Bandgap.
+ * @note In Deep Power Down mode, DCDC regulator is always turned off.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure.
+ *
+ * @retval #kStatus_Success Config DCDC regulator in low power mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option);
+
+/*!
+ * @brief Set DCDC_CORE Regulator drive strength in Low power mode.
+ *
+ * @note To set drive strength as normal, the bandgap must be enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get DCDC_CORE Regulator drive strength in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ */
+static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >>
+                                                  SPC_LP_CFG_DCDC_VDD_DS_SHIFT));
+}
+
+/*!
+ * @brief Set DCDC_CORE Regulator voltage level in Low power mode.
+ *
+ * @note To change DCDC level in Low-Power mode:
+ *          1. Configure LP_CFG[DCDC_VDD_LVL] to desired level;
+ *          2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength;
+ *  	    3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1.
+ *
+ * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed,
+ * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)
+{
+    base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel);
+    (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength);
+    SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel);
+}
+
+/*!
+ * @brief Get DCDC_CORE Regulator voltage level in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >>
+                                                 SPC_LP_CFG_DCDC_VDD_LVL_SHIFT));
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* FSL_SPC_H_ */
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 2b9c60beb..2dfefeb92 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -60,9 +60,14 @@ void USB0_IRQHandler(void) {
 
 
 void board_init(void) {
+
   BOARD_InitPins();
+
   BOARD_InitBootClocks();
+
+  #ifdef XTAL0_CLK_HZ
   CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+  #endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -84,15 +89,7 @@ void board_init(void) {
   board_led_write(0);
 
 #ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
+  // No neo pixel support yet
 #endif
 
   // Button
@@ -103,9 +100,6 @@ void board_init(void) {
 #endif
 
 #ifdef UART_DEV
-  // UART
-//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
 
   // Enable UART when debug log is on
   board_uart_init_clock();
@@ -115,6 +109,7 @@ void board_init(void) {
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
   uart_config.enableTx = true;
   uart_config.enableRx = true;
+
   LPUART_Init(UART_DEV, &uart_config, 12000000u);
 #endif
 
@@ -196,17 +191,6 @@ void board_init(void) {
 
 void board_led_write(bool state) {
   GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
 }
 
 uint32_t board_button_read(void) {
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 413c1b372..f857ed31a 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -10,6 +10,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 if (MCU_VARIANT STREQUAL "MCXA153")
   set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
   set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+elseif (MCU_VARIANT STREQUAL "MCXA156")
+    set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+    set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
 elseif (MCU_VARIANT STREQUAL "MCXN947")
   set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
   set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
@@ -38,12 +41,14 @@ function(add_board_target BOARD_TARGET)
   endif()
   set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+
   add_library(${BOARD_TARGET} STATIC
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     # driver
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
@@ -51,18 +56,27 @@ function(add_board_target BOARD_TARGET)
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/drivers/gpio/
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/port
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc
     ${SDK_DIR}/devices/${MCU_VARIANT}
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
     )
 
   if (${FAMILY_MCUS} STREQUAL "MCXN9")
+
     target_sources(${BOARD_TARGET} PRIVATE
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+            ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
+    )
+
+    target_include_directories(${BOARD_TARGET} PUBLIC
+            ${SDK_DIR}/drivers/lpflexcomm
     )
   elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
-    target_sources(${BOARD_TARGET} PRIVATE
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
-  )
+
+
   endif()
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 58149fb8d..a16f4b6c0 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -1,8 +1,6 @@
 UF2_FAMILY_ID = 0x2abc77ec
 SDK_DIR = hw/mcu/nxp/mcux-sdk
 
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 # Default to Highspeed PORT1
@@ -35,18 +33,19 @@ SRC_C += \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+	${SDK_DIR}/drivers/gpio/fsl_gpio.c \
+	${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \
+	${SDK_DIR}/drivers/common/fsl_common_arm.c\
+	hw/bsp/mcx/drivers/spc/fsl_spc.c
 
 # fsl_lpflexcomm for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
-	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
+	SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
 endif
 
 # fsl_spc for MCXNA15
 ifeq ($(MCU_VARIANT), MCXA153)
-	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
+
 endif
 
 INC += \
@@ -54,5 +53,15 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
 	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/ \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
+  	$(TOP)/$(SDK_DIR)/drivers/common\
+  	$(TOP)/$(SDK_DIR)/drivers/gpio\
+  	$(TOP)/$(SDK_DIR)/drivers/port\
+   	$(TOP)/hw/bsp/mcx/drivers/spc
+
+
+
 
 SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake
index ddd54b675..d9b4bf770 100644
--- a/hw/bsp/msp430/family.cmake
+++ b/hw/bsp/msp430/family.cmake
@@ -11,36 +11,37 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${T
 
 set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "")
 
-
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} INTERFACE)
-    target_compile_definitions(${BOARD_TARGET} INTERFACE
-      CFG_TUD_ENDPOINT0_SIZE=8
-      CFG_EXAMPLE_VIDEO_READONLY
-      CFG_EXAMPLE_MSC_READONLY
-      )
-    target_include_directories(${BOARD_TARGET} INTERFACE
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-      ${SDK_DIR}
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  add_library(${BOARD_TARGET} INTERFACE)
+  target_compile_definitions(${BOARD_TARGET} INTERFACE
+    CFG_TUD_ENDPOINT0_SIZE=8
+    CFG_EXAMPLE_VIDEO_READONLY
+    CFG_EXAMPLE_MSC_READONLY
+    )
+  target_include_directories(${BOARD_TARGET} INTERFACE
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${SDK_DIR}
+    )
+
+  update_board(${BOARD_TARGET})
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} INTERFACE
-        "LINKER:--script=${LD_FILE_GNU}"
-        -L${SDK_DIR}
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} INTERFACE
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} INTERFACE
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${SDK_DIR}
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} INTERFACE
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
@@ -75,7 +76,6 @@ function(family_configure_example TARGET RTOS)
     )
   target_link_libraries(${TARGET} PUBLIC board_${BOARD})
 
-
   # Flashing
   family_add_bin_hex(${TARGET})
   family_flash_msp430flasher(${TARGET})
diff --git a/hw/bsp/msp430/family.mk b/hw/bsp/msp430/family.mk
index 06508ab2c..c973d9dcd 100644
--- a/hw/bsp/msp430/family.mk
+++ b/hw/bsp/msp430/family.mk
@@ -1,5 +1,4 @@
 CROSS_COMPILE = msp430-elf-
-DEPS_SUBMODULES += hw/mcu/ti
 SKIP_NANOLIB = 1
 
 SDK_DIR = hw/mcu/ti/msp430/msp430-gcc-support-files/include
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index 161ff9041..06c47d544 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
 CFLAGS += \
   -flto \
   -mthumb \
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index 081764fd3..50b9d866a 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
 CFLAGS += \
   -flto \
   -mthumb \
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 2466b3a31..e87d1aad0 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
 CFLAGS += \
   -flto \
   -mthumb \
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index b54895b58..d982bdc06 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
 CFLAGS += \
   -flto \
   -mthumb \
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index f3b389354..1dc8b244e 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nuvoton
-
 CFLAGS += \
   -flto \
   -mthumb \
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake
new file mode 100644
index 000000000..97621d855
--- /dev/null
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.cmake
@@ -0,0 +1,2 @@
+set(PICO_PLATFORM rp2040)
+set(PICO_BOARD pico_w)
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h
new file mode 100644
index 000000000..8af32fc9e
--- /dev/null
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico_w/board.h
@@ -0,0 +1,70 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Pico
+   url: https://www.raspberrypi.com/products/raspberry-pi-pico/
+*/
+
+#ifndef TUSB_BOARD_H
+#define TUSB_BOARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// UART and LED are already defined in pico-sdk board
+
+//--------------------------------------------------------------------+
+// PIO_USB
+//--------------------------------------------------------------------+
+// default to pico brain tester
+#define PICO_DEFAULT_PIO_USB_DP_PIN       20
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
+#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
+
+//--------------------------------------------------------------------
+// USB Host MAX3421E
+//--------------------------------------------------------------------
+
+#ifdef PICO_DEFAULT_SPI
+#define MAX3421_SPI      PICO_DEFAULT_SPI // sdk v2
+#else
+#define MAX3421_SPI      PICO_DEFAULT_SPI_INSTANCE // sdk v1
+#endif
+
+#define MAX3421_SCK_PIN  PICO_DEFAULT_SPI_SCK_PIN
+#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN
+#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 9
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 8c85c5cc8..a22924131 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -254,7 +254,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
 int board_uart_read(uint8_t *buf, int len) {
 #ifdef UART_DEV
   int count = 0;
-  while ( (count < len) && uart_is_readable(uart_inst) ) {
+  while ((count < len) && uart_is_readable(uart_inst)) {
     buf[count] = uart_getc(uart_inst);
     count++;
   }
@@ -282,6 +282,10 @@ int board_getchar(void) {
   return getchar_timeout_us(0);
 }
 
+void board_putchar(int c) {
+  stdio_putchar(c);
+}
+
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 // rp2040 implementation will install appropriate handler when initializing
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
deleted file mode 100644
index 25d1ad9c5..000000000
--- a/hw/bsp/rp2040/family.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-JLINK_DEVICE = rp2040_m0_0
-PYOCD_TARGET = rp2040
-
-DEPS_SUBMODULES += hw/mcu/raspberry_pi/Pico-PIO-USB
-
-ifeq ($(DEBUG), 1)
-CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
-endif
-
-$(BUILD):
-	cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
-
-all: $(BUILD)
-	$(MAKE) -C $(BUILD)
-
-flash: flash-pyocd
-flash-uf2:
-	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
diff --git a/hw/bsp/rp2040/skip_ci.txt b/hw/bsp/rp2040/skip_ci.txt
new file mode 100644
index 000000000..fe99c9f65
--- /dev/null
+++ b/hw/bsp/rp2040/skip_ci.txt
@@ -0,0 +1,7 @@
+# boards in this files are skipped when running CI with this family
+adafruit_feather_rp2040_usb_host
+adafruit_fruit_jam
+adafruit_metro_rp2350
+feather_rp2040_max3421
+pico_sdk
+raspberry_pi_pico_w
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index 02ea0dfa4..4ecf80409 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/renesas/rx
-
 # Cross Compiler for RX
 CROSS_COMPILE = rx-elf-
 
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 281a947f3..7e949e135 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -1,4 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/microchip
 ASF_DIR = hw/mcu/microchip/same70
 
 CFLAGS += \
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 60702f14a..2d97ecdc1 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -1,4 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/microchip
 ASF_DIR = hw/mcu/microchip/same70
 
 CFLAGS += \
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index 687761364..5dd7a158f 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -16,9 +16,6 @@ CFLAGS += \
 SILABS_FAMILY = efm32gg12b
 SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z)
 
-DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
-DEPS_SUBMODULES += lib/CMSIS_5
-
 LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # All source paths should be relative to the top level.
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index 15fa0ff20..24f39d2b6 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk
-
 # Platforms are: Linux, Darwin, MSYS, CYGWIN
 PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null)))
 
diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h
index c7d809717..751df2251 100644
--- a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h
+++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h
@@ -55,9 +55,45 @@
 
 // Enable UART serial communication with the ST-Link
 #define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
 #define UART_GPIO_PORT        GPIOA
 #define UART_GPIO_AF          GPIO_AF1_USART2
 #define UART_TX_PIN           GPIO_PIN_2
 #define UART_RX_PIN           GPIO_PIN_3
 
+static inline void board_clock_init(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+
+  /* -1- Enable HSIUSB48  Oscillator */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* -2- Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSIUSB48;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
+
+
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  // Configures CRS
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+}
+
 #endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c
index ace3f2a71..09704b527 100644
--- a/hw/bsp/stm32c0/family.c
+++ b/hw/bsp/stm32c0/family.c
@@ -53,31 +53,16 @@ UART_HandleTypeDef UartHandle;
 
 void board_init(void) {
   HAL_Init();
-
-  // Enable the HSIUSB48 48 MHz oscillator.
-  RCC->CR |= RCC_CR_HSIUSB48ON;
-
-  // Wait for HSIUSB48 to be ready.
-  while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { }
-
-  // Change the SYSCLK source to HSIUSB48.
-  RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48;
-
-  // Wait for the SYSCLK source to change.
-  while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { }
-
-  // Disable HSI48 to save power.
-  RCC->CR &= ~RCC_CR_HSION;
+  board_clock_init();
 
   // Enable peripheral clocks.
-  RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN;
-  RCC->APBENR2 = RCC_APBENR2_USART1EN;
-
-  // Enable all GPIO clocks.
-  RCC->IOPENR = 0x2F;
-
-  // Turn on CRS to make the HSIUSB48 clock more precise when USB is connected.
-  CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
+  __HAL_RCC_USB_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -109,6 +94,7 @@ void board_init(void) {
   }
 
 #ifdef UART_DEV
+  UART_CLK_EN();
   // UART
   {
     GPIO_InitTypeDef gpio_init = { 0 };
diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk
index 9ff3a2fdf..bdb34454e 100644
--- a/hw/bsp/stm32c0/family.mk
+++ b/hw/bsp/stm32c0/family.mk
@@ -1,6 +1,4 @@
 ST_FAMILY = c0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 431709de0..9b8305874 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -1,7 +1,5 @@
 UF2_FAMILY_ID = 0x647824b6
 ST_FAMILY = f0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 364616304..ca95f2315 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -1,6 +1,4 @@
 ST_FAMILY = f1
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
-
 ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY}
 ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
 
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
index ba185d199..6e681ef57 100644
--- a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
@@ -1,12 +1,9 @@
-CFLAGS += \
-  -DSTM32F207xx \
+MCU_VARIANT = stm32f207xx
+CFLAGS += -DSTM32F207xx
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/STM32F207ZGTx_FLASH.ld
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
-
 # For flash-jlink target
 JLINK_DEVICE = stm32f207zg
 
diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk
index 7af9a76a0..ef14a9d67 100644
--- a/hw/bsp/stm32f2/family.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -1,24 +1,17 @@
 ST_FAMILY = f2
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
-DEPS_SUBMODULES += \
-	lib/CMSIS_5 \
-	$(ST_CMSIS) \
-	$(ST_HAL_DRIVER)
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m3
 
 CFLAGS += \
 	-DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
+# mcu driver cause following warnings
 CFLAGS_GCC += \
   -flto \
-
-# mcu driver cause following warnings
-CFLAGS_GCC += -Wno-error=sign-compare
+  -Wno-error=sign-compare
 
 LDFLAGS_GCC += \
   -nostdlib -nostartfiles \
@@ -40,3 +33,10 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/$(BOARD_PATH)
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s
+
+# Linker
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
index e387f2d54..6b9a3e283 100644
--- a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32f303xc
 CFLAGS += \
   -DSTM32F303xC \
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/STM32F303VCTx_FLASH.ld
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
-
 # For flash-jlink target
 JLINK_DEVICE = stm32f303vc
 
diff --git a/hw/bsp/stm32f3/family.mk b/hw/bsp/stm32f3/family.mk
index 4fe3aa99d..13734583a 100644
--- a/hw/bsp/stm32f3/family.mk
+++ b/hw/bsp/stm32f3/family.mk
@@ -1,22 +1,17 @@
 ST_FAMILY = f3
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
-DEPS_SUBMODULES += \
-	lib/CMSIS_5 \
-	$(ST_CMSIS) \
-	$(ST_HAL_DRIVER)
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m4
 
 CFLAGS += \
-  -flto \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F3
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
+CFLAGS_GCC += \
+  -flto \
+  -Wno-error=unused-parameter
 
 LDFLAGS_GCC += \
   -nostdlib -nostartfiles \
@@ -36,3 +31,10 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/$(BOARD_PATH)
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s
+
+# Linker
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 51ff43a60..c3c41dc3f 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -1,6 +1,5 @@
 UF2_FAMILY_ID = 0x57755a57
 ST_FAMILY = f4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index abeea784c..d3422e03c 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -1,6 +1,5 @@
 UF2_FAMILY_ID = 0x53b80f00
 ST_FAMILY = f7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index 95b8e537d..d735ca92d 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -1,5 +1,4 @@
 ST_FAMILY = g0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 334876e51..7c3f6414a 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -184,7 +184,7 @@ static MFXSTM32L152_Object_t  mfx_obj = { 0 };
 static MFXSTM32L152_IO_Mode_t* mfx_io = NULL;
 static uint32_t mfx_vbus_pin[2] = { MFXSTM32L152_GPIO_PIN_7, MFXSTM32L152_GPIO_PIN_9 };
 
-int32_t board_i2c_init(void) {
+static int32_t board_i2c_init(void) {
   __HAL_RCC_I2C1_CLK_ENABLE();
   __HAL_RCC_I2C1_FORCE_RESET();
   __HAL_RCC_I2C1_RELEASE_RESET();
@@ -200,16 +200,16 @@ int32_t board_i2c_init(void) {
   return 0;
 }
 
-int32_t board_i2c_deinit(void) {
+static int32_t board_i2c_deinit(void) {
   return 0;
 }
 
-int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+static int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
   TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
   return 0;
 }
 
-int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+static int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
   TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
   return 0;
 }
@@ -249,7 +249,7 @@ static inline void board_init2(void) {
 }
 
 // VBUS1 is actually controlled by USB3320C PHY (using dwc2 drivebus signal)
-void board_vbus_set(uint8_t rhport, bool state) {
+static void TU_ATTR_UNUSED board_vbus_set(uint8_t rhport, bool state) {
   if (mfx_io) {
     mfx_io->IO_WritePin(&mfx_obj, mfx_vbus_pin[rhport], state);
   }
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index e5228b29b..f8723b0c7 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -80,7 +80,7 @@ void OTG_HS_IRQHandler(void) {
 }
 
 #ifdef TRACE_ETM
-void trace_etm_init(void) {
+static void trace_etm_init(void) {
   // H7 trace pin is PE2 to PE6
   GPIO_InitTypeDef  gpio_init;
   gpio_init.Pin       = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6;
@@ -94,7 +94,7 @@ void trace_etm_init(void) {
   DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN;
 }
 #else
-  #define trace_etm_init()
+#define trace_etm_init()
 #endif
 
 void board_init(void) {
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 29b83cf7d..19a085424 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -45,11 +45,9 @@ CFLAGS += \
 	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
 
 # GCC Flags
-CFLAGS_GCC += \
-  -flto \
-
 # suppress warning caused by vendor mcu driver
 CFLAGS_GCC += \
+  -flto \
   -Wno-error=cast-align \
   -Wno-error=unused-parameter \
 
diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h
index e5a76af85..9fd3f6c50 100644
--- a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,7 +44,7 @@
 
 // skip if included from IAR assembler
 #ifndef __IASMARM__
-  #include "mxc_device.h"
+  #include "stm32h7rsxx.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
@@ -59,7 +59,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
@@ -127,7 +127,7 @@
 //--------------------------------------------------------------------+
 
 // For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
+#define configPRIO_BITS       4
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
new file mode 100644
index 000000000..f52b70408
--- /dev/null
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
@@ -0,0 +1,19 @@
+set(MCU_VARIANT stm32h7s3xx)
+set(JLINK_DEVICE stm32h7s3xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H7S3xx
+    )
+  target_sources(${TARGET} PUBLIC
+    ${ST_TCPP0203}/tcpp0203.c
+    ${ST_TCPP0203}/tcpp0203_reg.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${ST_TCPP0203}
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
new file mode 100644
index 000000000..dfa77a8fb
--- /dev/null
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
@@ -0,0 +1,262 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H7S3L8 Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "tcpp0203.h"
+#include "stm32h7rsxx_ll_exti.h"
+#include "stm32h7rsxx_ll_system.h"
+
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+#define PINID_TCPP0203_EN  4
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOD,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // VBUS input pin used for TCPP0203 EN
+    .port = GPIOM,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // I2C SCL for TCPP0203
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF4_I2C3 },
+  },
+  { // I2C SDA for TCPP0203
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = GPIO_AF4_I2C3 },
+  },
+  { // INT for TCPP0203
+    .port = GPIOM,
+    .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 },
+  },
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI;
+  RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure the main internal regulator output voltage
+  */
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL1.PLLM = 12;
+  RCC_OscInitStruct.PLL1.PLLN = 300;
+  RCC_OscInitStruct.PLL1.PLLP = 1;
+  RCC_OscInitStruct.PLL1.PLLQ = 2;
+  RCC_OscInitStruct.PLL1.PLLR = 2;
+  RCC_OscInitStruct.PLL1.PLLS = 2;
+  RCC_OscInitStruct.PLL1.PLLT = 2;
+  RCC_OscInitStruct.PLL1.PLLFractional = 0;
+  RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL2.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL2.PLLM = 12;
+  RCC_OscInitStruct.PLL2.PLLN = 200;
+  RCC_OscInitStruct.PLL2.PLLP = 2;
+  RCC_OscInitStruct.PLL2.PLLQ = 2;
+  RCC_OscInitStruct.PLL2.PLLR = 2;
+  RCC_OscInitStruct.PLL2.PLLS = 2;
+  RCC_OscInitStruct.PLL2.PLLT = 2;
+  RCC_OscInitStruct.PLL2.PLLFractional = 0;
+  RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_PCLK4|RCC_CLOCKTYPE_PCLK5;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHYC;
+  PeriphClkInit.UsbPhycClockSelection = RCC_USBPHYCCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  __HAL_RCC_SBS_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// USB PD
+//--------------------------------------------------------------------+
+static I2C_HandleTypeDef i2c_handle = {
+  .Instance = I2C3,
+  .Init = {
+    .Timing = 0x20C0EDFF,
+    .OwnAddress1 = 0,
+    .AddressingMode = I2C_ADDRESSINGMODE_7BIT,
+    .DualAddressMode = I2C_DUALADDRESS_DISABLE,
+    .OwnAddress2 = 0,
+    .OwnAddress2Masks = I2C_OA2_NOMASK,
+    .GeneralCallMode = I2C_GENERALCALL_DISABLE,
+    .NoStretchMode = I2C_NOSTRETCH_DISABLE,
+  }
+};
+static TCPP0203_Object_t tcpp0203_obj = { 0 };
+
+int32_t board_tcpp0203_init(void) {
+  board_pindef_t* pindef = &board_pindef[PINID_TCPP0203_EN];
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET);
+
+  __HAL_RCC_I2C3_CLK_ENABLE();
+  __HAL_RCC_I2C3_FORCE_RESET();
+  __HAL_RCC_I2C3_RELEASE_RESET();
+  if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
+    return HAL_ERROR;
+  }
+
+  NVIC_SetPriority(EXTI8_IRQn, 12);
+  NVIC_EnableIRQ(EXTI8_IRQn);
+
+  return 0;
+}
+
+int32_t board_tcpp0203_deinit(void) {
+  return 0;
+}
+
+int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+static inline void board_init2(void) {
+  TCPP0203_IO_t            io_ctx;
+
+  io_ctx.Address     = TCPP0203_I2C_ADDRESS_X68;
+  io_ctx.Init        = board_tcpp0203_init;
+  io_ctx.DeInit      = board_tcpp0203_deinit;
+  io_ctx.ReadReg     = i2c_readreg;
+  io_ctx.WriteReg    = i2c_writereg;
+
+  TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, );
+
+  TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, );
+
+  TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) state;
+  if (rhport == 1) {
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  }
+}
+
+void EXTI8_IRQHandler(void) {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8);
+    if (tcpp0203_obj.IsInitialized) {
+      TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
+      TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+    }
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
new file mode 100644
index 000000000..cf0c2ff54
--- /dev/null
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
@@ -0,0 +1,19 @@
+MCU_VARIANT = stm32h7s3xx
+CFLAGS += -DSTM32H7S3xx
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h7s3xx
+
+# flash target using on-board stlink
+flash: flash-stlink
+
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
+
+SRC_C += \
+	$(ST_TCPP0203)/tcpp0203.c \
+	$(ST_TCPP0203)/tcpp0203_reg.c \
+
+INC += \
+	$(TOP)/$(ST_TCPP0203) \
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
new file mode 100644
index 000000000..8ffaa74a7
--- /dev/null
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
@@ -0,0 +1,55 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol NONCACHEABLEBUFFER_size   = 0x4000;
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
+define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
+define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ITCM_start__ = 0x00000000;
+define symbol __region_ITCM_end__   = 0x0000FFFF;
+define symbol __region_DTCM_start__ = 0x20000000;
+define symbol __region_DTCM_end__   = 0x2000FFFF;
+define symbol __region_SRAMAHB_start__ = 0x30000000;
+define symbol __region_SRAMAHB_end__   = 0x30007FFF;
+define symbol __region_BKPSRAM_start__ = 0x38800000;
+define symbol __region_BKPSRAM_end__   = 0x38800FFF;
+
+export symbol NONCACHEABLEBUFFER_start;
+export symbol NONCACHEABLEBUFFER_size;
+
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
+define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
+define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
+define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
+define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite };
+place in NONCACHEABLE_region { section noncacheable_buffer };
+place in DTCM_region  { block CSTACK, block HEAP };
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld
new file mode 100644
index 000000000..3bd7f0b89
--- /dev/null
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld
@@ -0,0 +1,208 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32H7S3xx Device from STM32H7RS series
+**                      64Kbytes FLASH
+**                      456Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+__FLASH_BEGIN  = 0x08000000;
+__FLASH_SIZE   = 0x00010000;
+
+__RAM_BEGIN    = 0x24000000;
+__RAM_SIZE     = 0x4FC00;
+__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000;
+
+/* Memories definition */
+MEMORY
+{
+  RAM       (xrw) : ORIGIN = __RAM_BEGIN,    LENGTH = __RAM_SIZE
+  RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE,  LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
+
+  ITCM      (xrw) : ORIGIN = 0x00000000,    LENGTH = 0x00010000
+  DTCM       (rw) : ORIGIN = 0x20000000,    LENGTH = 0x00010000
+  SRAMAHB   (rw)  : ORIGIN = 0x30000000,  LENGTH = 0x00008000
+  BKPSRAM   (rw)  : ORIGIN = 0x38800000,  LENGTH = 0x00001000
+
+  FLASH     (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab :
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM :
+   {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array   :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array  :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array  :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  RW_NONCACHEABLE :
+  {
+    __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
+    KEEP(*(noncacheable_buffer))
+    __NONCACHEABLEBUFFER_END = .;  /* create symbol for start of section */
+  } > RAM_NONCACHEABLEBUFFER
+
+  /* User_heap_stack section, used to check that there is enough "DTCM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >DTCM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c
new file mode 100644
index 000000000..4b81deea0
--- /dev/null
+++ b/hw/bsp/stm32h7rs/family.c
@@ -0,0 +1,340 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019
+ *    William D. Jones ([email protected]),
+ *    Ha Thach (tinyusb.org)
+ *    Uwe Bonnes ([email protected]
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+#include "stm32h7rsxx_hal.h"
+#include "bsp/board_api.h"
+
+TU_ATTR_UNUSED static void Error_Handler(void) { }
+
+typedef struct {
+  GPIO_TypeDef* port;
+  GPIO_InitTypeDef pin_init;
+  uint8_t active_state;
+} board_pindef_t;
+
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle = {
+  .Instance = UART_DEV,
+  .Init = {
+    .BaudRate = CFG_BOARD_UART_BAUDRATE,
+    .WordLength = UART_WORDLENGTH_8B,
+    .StopBits = UART_STOPBITS_1,
+    .Parity = UART_PARITY_NONE,
+    .HwFlowCtl = UART_HWCONTROL_NONE,
+    .Mode = UART_MODE_TX_RX,
+    .OverSampling = UART_OVERSAMPLING_16,
+  }
+};
+#endif
+
+#ifndef SWO_FREQ
+#define SWO_FREQ  4000000
+#endif
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// Despite being call USB2_OTG_FS on some MCUs
+// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
+void OTG_FS_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+// Despite being call USB1_OTG_HS on some MCUs
+// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
+void OTG_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
+}
+
+#ifdef TRACE_ETM
+void trace_etm_init(void) {
+  // H7 trace pin is PE2 to PE6
+  GPIO_InitTypeDef  gpio_init;
+  gpio_init.Pin       = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6;
+  gpio_init.Mode      = GPIO_MODE_AF_PP;
+  gpio_init.Pull      = GPIO_PULLUP;
+  gpio_init.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_init.Alternate = GPIO_AF0_TRACE;
+  HAL_GPIO_Init(GPIOE, &gpio_init);
+
+  // Enable trace clk, also in D1 and D3 domain
+  DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN;
+}
+#else
+  #define trace_etm_init()
+#endif
+
+#ifdef LOGGER_SWO
+void log_swo_init(void)
+{
+  //UNLOCK FUNNEL
+  *(volatile uint32_t*)(0x5C004FB0) = 0xC5ACCE55; // SWTF_LAR
+  *(volatile uint32_t*)(0x5C003FB0) = 0xC5ACCE55; // SWO_LAR
+
+  //SWO current output divisor register
+  //To change it, you can use the following rule
+  // value = (CPU_Freq / 3 / SWO_Freq) - 1
+  *(volatile uint32_t*)(0x5C003010) = ((SystemCoreClock / 3 / SWO_FREQ) - 1); // SWO_CODR
+
+  //SWO selected pin protocol register
+  *(volatile uint32_t*)(0x5C0030F0) = 0x00000002; // SWO_SPPR
+
+  //Enable ITM input of SWO trace funnel
+  *(volatile uint32_t*)(0x5C004000) |= 0x00000001; // SWFT_CTRL
+}
+#else
+  #define log_swo_init()
+#endif
+
+void board_init(void) {
+  HAL_Init();
+
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  // Implemented in board.h
+  SystemClock_Config();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOM_CLK_ENABLE();
+  __HAL_RCC_GPION_CLK_ENABLE();
+  __HAL_RCC_GPIOO_CLK_ENABLE();
+  __HAL_RCC_GPIOP_CLK_ENABLE();
+
+  log_swo_init();
+  trace_etm_init();
+
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
+    HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
+  }
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  #ifdef USB_OTG_FS_PERIPH_BASE
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  #endif
+
+  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+
+
+#ifdef UART_DEV
+  UART_CLK_EN();
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  //------------- USB FS -------------//
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
+  // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
+
+  HAL_PWREx_EnableUSBVoltageDetector();
+  HAL_PWREx_EnableUSBReg();
+
+  __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
+
+  // PM14 VUSB, PM10 ID, PM11 DM, PM12 DP
+  // Configure DM DP Pins
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+
+  // This for ID line debug
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+
+#if OTG_FS_VBUS_SENSE
+  // Configure VBUS Pin
+  GPIO_InitStruct.Pin = GPIO_PIN_14;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+
+  // Enable VBUS sense (B device) via pin PM14
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
+  // Disable VBUS sense (B device)
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#endif // vbus sense
+#endif
+
+  //------------- USB HS -------------//
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+
+  // Enable USB HS & ULPI Clocks
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_USBPHYC_CLK_ENABLE();
+
+  // Enable USB power
+  HAL_PWREx_EnableUSBVoltageDetector();
+  HAL_PWREx_EnableUSBHSregulator();
+
+#if OTG_HS_VBUS_SENSE
+  // Configure VBUS Pin
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+
+  // Enable VBUS sense (B device) via pin PM9
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
+  // Disable VBUS sense (B device)
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#else
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
+#endif
+
+#endif
+#endif
+
+  board_init2();
+
+#if CFG_TUH_ENABLED
+  board_vbus_set(BOARD_TUH_RHPORT, 1);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#ifdef PINID_LED
+  board_pindef_t* pindef = &board_pindef[PINID_LED];
+  GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
+#else
+  (void) state;
+#endif
+}
+
+uint32_t board_button_read(void) {
+#ifdef PINID_BUTTON
+  board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
+  return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
+#else
+  return 0;
+#endif
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len;
+  return -1;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake
new file mode 100644
index 000000000..e5e98f914
--- /dev/null
+++ b/hw/bsp/stm32h7rs/family.cmake
@@ -0,0 +1,150 @@
+include_guard()
+
+set(ST_FAMILY h7rs)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32H7RS CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  if(NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
+  endif()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if(NOT DEFINED LD_FILE_IAR)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  endif()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    SEGGER_RTT_SECTION="noncacheable_buffer"
+    BUFFER_SIZE_UP=0x3000
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H7RS ${RTOS})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk
new file mode 100644
index 000000000..9970059f8
--- /dev/null
+++ b/hw/bsp/stm32h7rs/family.mk
@@ -0,0 +1,95 @@
+ST_FAMILY = h7rs
+ST_PREFIX = stm32${ST_FAMILY}xx
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
+ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203
+
+UF2_FAMILY_ID = 0x6db66083
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m7
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 1
+
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H7RS \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
+	-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
+	-DBUFFER_SIZE_UP=0x3000 \
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += \
+  -Wno-error=cast-align \
+  -Wno-error=unused-parameter \
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
+    $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \
+    $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h
new file mode 100644
index 000000000..6fd90abde
--- /dev/null
+++ b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h
@@ -0,0 +1,500 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7rsxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32h7rsxx_hal_conf.h.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7RSxx_HAL_CONF_H
+#define STM32H7RSxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_CORDIC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DCMIPP_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_GFXTIM_MODULE_ENABLED   */
+/* #define HAL_GPU2D_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_I3C_MODULE_ENABLED   */
+/* #define HAL_ICACHE_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_MCE_MODULE_ENABLED   */
+/* #define HAL_MDF_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_PKA_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_RAMECC_MODULE_ENABLED   */
+/* #define HAL_RCC_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_XSPI_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    24000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up (in ms) */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE          64000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low-power oscillator (CSI) default value.
+  *        This value is the default CSI range value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE          4000000UL  /*!< Value of the Internal oscillator in Hz */
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG.
+ *        This internal oscillator is mainly dedicated to provide a high precision clock to
+ *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ *        which is subject to manufacturing process variations.
+  */
+  #if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE        48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz.
+                                            The real value my vary depending on manufacturing process variations. */
+  #endif /* HSI48_VALUE */
+
+/**
+* @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  32000UL              /*!< LSI Typical Value in Hz.
+                                            Value of the Internal Low Speed oscillator in Hz.
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+#endif /* LSI_VALUE */
+
+/**
+* @brief External Low Speed oscillator (LSE) value.
+*/
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768UL /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL   /*!< Time out for LSE start up (in ms) */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF
+  *        This value is used by the RCC HAL module to provide the digital audio interfaces
+  *        frequency. This clock source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE      48000UL /*!< Value of the external clock source in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (15UL)/*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0U
+
+/* ########################## Assert Selection ############################## */
+/**
+* @brief Uncomment the line below to expanse the "assert_param" macro in the
+*        HAL drivers code
+*/
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+* @brief Set below the peripheral configuration  to "1U" to add the support
+*        of HAL callback registration/unregistration feature for the HAL
+*        driver(s). This allows user application to provide specific callback
+*        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+*        the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file
+*        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+*        for each PPP peripheral).
+*/
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_CEC_REGISTER_CALLBACKS        0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS     0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DCMIPP_REGISTER_CALLBACKS     0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS     0U
+#define USE_HAL_HASH_REGISTER_CALLBACKS       0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_JPEG_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_MDF_REGISTER_CALLBACKS        0U
+#define USE_HAL_MMC_REGISTER_CALLBACKS        0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_PKA_REGISTER_CALLBACKS        0U
+#define USE_HAL_PSSI_REGISTER_CALLBACKS       0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SD_REGISTER_CALLBACKS         0U
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS      0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS    0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+#define USE_HAL_XSPI_REGISTER_CALLBACKS       0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                   1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME   0U
+
+/* ################## HASH peripheral configuration ########################## */
+
+#define USE_HAL_HASH_SUSPEND_RESUME   0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER            0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DCMIPP_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_dcmipp.h"
+#endif /* HAL_DCMIPP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_GFXTIM_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_gfxtim.h"
+#endif /* HAL_GFXTIM_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7rsxx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_I3C_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_i3c.h"
+#endif /* HAL_I3C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MCE_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_mce.h"
+#endif /* HAL_MCE_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_ramecc.h"
+#endif /* HAL_RAMECC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+  #include "stm32h7rsxx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7RSxx_HAL_CONF_H */
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
index 0b1348474..e63b41f12 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
@@ -1,10 +1,9 @@
+MCU_VARIANT = stm32l052xx
 CFLAGS += \
 	-DSTM32L052xx
 
 LD_FILE = $(BOARD_PATH)/STM32L052K8Ux_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l052xx.s
-
 # For flash-jlink target
 JLINK_DEVICE = stm32l052k8
 
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
index deed519ba..f3e6978b0 100644
--- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32l053xx
 CFLAGS += \
   -DSTM32L053xx
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/STM32L053C8Tx_FLASH.ld
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
-
 # For flash-jlink target
 JLINK_DEVICE = STM32L053R8
 
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index fe7561fc2..921b1b413 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -1,9 +1,4 @@
 ST_FAMILY = l0
-DEPS_SUBMODULES += \
-	lib/CMSIS_5 \
-	hw/mcu/st/cmsis_device_$(ST_FAMILY) \
-	hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
@@ -11,20 +6,17 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
-  -flto \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
 # mcu driver cause following warnings
 CFLAGS_GCC += \
+  -flto \
 	-Wno-error=unused-parameter \
 	-Wno-error=redundant-decls \
 	-Wno-error=cast-align \
-
-ifeq ($(TOOLCHAIN),gcc)
-CFLAGS_GCC += -Wno-error=maybe-uninitialized
-endif
+	-Wno-error=maybe-uninitialized \
 
 CFLAGS_CLANG += \
   -Wno-error=parentheses-equality
@@ -48,3 +40,10 @@ INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}.s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_${MCU_VARIANT}.s
+
+# Linker
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 950b6f9cb..01d059236 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -1,5 +1,4 @@
 ST_FAMILY = l4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h
index e5a76af85..a1b83c802 100644
--- a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,10 +44,11 @@
 
 // skip if included from IAR assembler
 #ifndef __IASMARM__
-  #include "mxc_device.h"
+  #include "stm32n6xx.h"
 #endif
 
-/* Cortex M23/M33 port configuration. */
+/* Cortex M55 port configuration. */
+#define configENABLE_MVE                        0
 #define configENABLE_MPU                        0
 #define configENABLE_FPU                        1
 #define configENABLE_TRUSTZONE                  0
@@ -59,7 +60,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
@@ -127,7 +128,7 @@
 //--------------------------------------------------------------------+
 
 // For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
+#define configPRIO_BITS       4
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld b/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld
new file mode 100644
index 000000000..e4c792cd8
--- /dev/null
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld
@@ -0,0 +1,203 @@
+/*
+******************************************************************************
+**
+** @file        : STM32N657XX_AXISRAM2_fsbl.ld
+**
+** @author      : GPM Application Team
+**
+** @brief       : Linker script for STM32N657XX Device from STM32N6 series
+**                      512 KBytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+_sstack = _estack - _Min_Stack_Size;
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (xrw)    : ORIGIN = 0x34180400,   LENGTH = 255K
+  RAM    (xrw)    : ORIGIN = 0x341C0000,   LENGTH = 256K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >ROM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >ROM
+
+  .ARM.extab   (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+   {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >ROM
+
+  .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+   {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >ROM
+
+  .preinit_array     (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> ROM
+
+  .noncacheable :
+  {
+    . = ALIGN(8);
+    __snoncacheable = .;/* create symbol for start of section */
+    KEEP(*(.noncacheable))
+    . = ALIGN(8);
+    __enoncacheable = .;  /* create symbol for end of section */
+  } > RAM
+
+
+  .gnu.sgstubs :
+  {
+    . = ALIGN(4);
+    *(.gnu.sgstubs*)   /* Secure Gateway stubs */
+    . = ALIGN(4);
+  } >ROM
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
new file mode 100644
index 000000000..e88efefb9
--- /dev/null
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT stm32n657xx)
+set(JLINK_DEVICE stm32n6xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32N657xx
+    )
+  target_sources(${TARGET} PUBLIC
+    ${ST_TCPP0203}/tcpp0203.c
+    ${ST_TCPP0203}/tcpp0203_reg.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${ST_TCPP0203}
+    )
+endfunction()
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
new file mode 100644
index 000000000..963ecad61
--- /dev/null
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
@@ -0,0 +1,283 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 N657X0-Q Nucleo
+   url: https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32n657xx.h"
+#include "stm32n6xx_ll_exti.h"
+#include "stm32n6xx_ll_system.h"
+#include "tcpp0203.h"
+
+#define UART_DEV USART1
+#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
+
+#define BOARD_TUD_RHPORT 1
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE 1
+#define OTG_HS_VBUS_SENSE 1
+
+#define PINID_LED 0
+#define PINID_BUTTON 1
+#define PINID_UART_TX 2
+#define PINID_UART_RX 3
+#define PINID_TCPP0203_EN 4
+
+static board_pindef_t board_pindef[] = {
+    {// LED
+     .port = GPIOG,
+     .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+     .active_state = 1},
+    {// Button
+     .port = GPIOC,
+     .pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+     .active_state = 1},
+    {// UART TX
+     .port = GPIOE,
+     .pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
+     .active_state = 0},
+    {// UART RX
+     .port = GPIOE,
+     .pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
+     .active_state = 0},
+    {// VBUS input pin used for TCPP0203 EN
+     .port = GPIOA,
+     .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+     .active_state = 0},
+    {
+        // I2C SCL for TCPP0203
+        .port = GPIOB,
+        .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    },
+    {
+        // I2C SDA for TCPP0203
+        .port = GPIOB,
+        .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    },
+    {
+        // INT for TCPP0203
+        .port = GPIOD,
+        .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    },
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  /* Configure the power domain */
+  if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /* Get current CPU/System buses clocks configuration */
+  /* and if necessary switch to intermediate HSI clock */
+  /* to ensure target clock can be set                 */
+  HAL_RCC_GetClockConfig(&RCC_ClkInitStruct);
+  if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) ||
+      (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) {
+    RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK);
+    RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
+      Error_Handler();
+    }
+  }
+
+  /* HSE selected as source (stable clock on Level 0 samples */
+  /* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2             */
+  /*             = ((48000000/3)*75)/1/1                     */
+  /*             = (16000000*75)/1/1                         */
+  /*             = 1200000000 (1200 MHz)                     */
+  /* PLL2 off                                                */
+  /* PLL3 off                                                */
+  /* PLL4 off                                                */
+
+  /* Enable HSE && HSI */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */
+
+  RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL1.PLLM = 3;
+  RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */
+  RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */
+  RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */
+  RCC_OscInitStruct.PLL1.PLLFractional = 0;
+
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    /* Initialization error */
+    Error_Handler();
+  }
+
+  /* Select PLL1 outputs as CPU and System bus clock source */
+  /* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */
+  /* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */
+  /* Configure the HCLK clock divider */
+  /* HCLK =  PLL1 SYSCLK/HCLK divider = 200 MHz */
+  /* PCLKx = HCLK / PCLKx divider = 200 MHz */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+                                 RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5);
+  RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
+  RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
+  RCC_ClkInitStruct.IC1Selection.ClockDivider = 2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
+  RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
+  RCC_ClkInitStruct.IC2Selection.ClockDivider = 3;
+  RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
+  RCC_ClkInitStruct.IC6Selection.ClockDivider = 3;
+  RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
+  RCC_ClkInitStruct.IC11Selection.ClockDivider = 3;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+  RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /** Initializes the peripherals clock
+    */
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
+  PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    /* Initialization Error */
+    Error_Handler();
+  }
+
+  /** Set USB OTG HS PHY1 Reference Clock Source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
+  PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
+
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    /* Initialization Error */
+    Error_Handler();
+  }
+}
+
+//--------------------------------------------------------------------+
+// USB PD
+//--------------------------------------------------------------------+
+static I2C_HandleTypeDef i2c_handle = {
+    .Instance = I2C2,
+    .Init = {
+        .Timing = 0x20C0EDFF,
+        .OwnAddress1 = 0,
+        .AddressingMode = I2C_ADDRESSINGMODE_7BIT,
+        .DualAddressMode = I2C_DUALADDRESS_DISABLE,
+        .OwnAddress2 = 0,
+        .OwnAddress2Masks = I2C_OA2_NOMASK,
+        .GeneralCallMode = I2C_GENERALCALL_DISABLE,
+        .NoStretchMode = I2C_NOSTRETCH_DISABLE,
+    }};
+static TCPP0203_Object_t tcpp0203_obj = {0};
+
+int32_t board_tcpp0203_init(void) {
+  board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN];
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET);
+
+  __HAL_RCC_I2C2_CLK_ENABLE();
+  __HAL_RCC_I2C2_FORCE_RESET();
+  __HAL_RCC_I2C2_RELEASE_RESET();
+  if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
+    return HAL_ERROR;
+  }
+
+  NVIC_SetPriority(EXTI8_IRQn, 12);
+  NVIC_EnableIRQ(EXTI8_IRQn);
+
+  return 0;
+}
+
+int32_t board_tcpp0203_deinit(void) {
+  return 0;
+}
+
+int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
+  TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
+  return 0;
+}
+
+static inline void board_init2(void) {
+  TCPP0203_IO_t io_ctx;
+
+  io_ctx.Address = TCPP0203_I2C_ADDRESS_X68;
+  io_ctx.Init = board_tcpp0203_init;
+  io_ctx.DeInit = board_tcpp0203_deinit;
+  io_ctx.ReadReg = i2c_readreg;
+  io_ctx.WriteReg = i2c_writereg;
+
+  TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, );
+
+  TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, );
+
+  TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) state;
+  if (rhport == 1) {
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  }
+}
+
+void EXTI8_IRQHandler(void) {
+  __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8);
+  if (tcpp0203_obj.IsInitialized) {
+    TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
new file mode 100644
index 000000000..05717699c
--- /dev/null
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
@@ -0,0 +1,17 @@
+MCU_VARIANT = stm32n657xx
+CFLAGS += -DSTM32N657xx
+JLINK_DEVICE = stm32n6xx
+
+LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
+
+# flash target using on-board stlink
+flash: flash-stlink
+
+PORT = 1
+
+SRC_C += \
+	$(ST_TCPP0203)/tcpp0203.c \
+	$(ST_TCPP0203)/tcpp0203_reg.c \
+
+INC += \
+	$(TOP)/$(ST_TCPP0203) \
diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c
new file mode 100644
index 000000000..1d0616d8e
--- /dev/null
+++ b/hw/bsp/stm32n6/family.c
@@ -0,0 +1,280 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019
+ *    William D. Jones ([email protected]),
+ *    Ha Thach (tinyusb.org)
+ *    Uwe Bonnes ([email protected]
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-align"
+#endif
+
+#include "stm32n6xx_hal.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+
+TU_ATTR_UNUSED static void Error_Handler(void) { }
+
+void HardFault_Handler(void);
+
+typedef struct {
+  GPIO_TypeDef* port;
+  GPIO_InitTypeDef pin_init;
+  uint8_t active_state;
+} board_pindef_t;
+
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#ifdef UART_DEV
+UART_HandleTypeDef UartHandle = {
+  .Instance = UART_DEV,
+  .Init = {
+    .BaudRate = CFG_BOARD_UART_BAUDRATE,
+    .WordLength = UART_WORDLENGTH_8B,
+    .StopBits = UART_STOPBITS_1,
+    .Parity = UART_PARITY_NONE,
+    .HwFlowCtl = UART_HWCONTROL_NONE,
+    .Mode = UART_MODE_TX_RX,
+    .OverSampling = UART_OVERSAMPLING_16,
+  }
+};
+#endif
+
+#ifndef SWO_FREQ
+#define SWO_FREQ  4000000
+#endif
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// Despite being call USB2_OTG_FS on some MCUs
+// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
+void USB2_OTG_HS_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+// Despite being call USB1_OTG_HS on some MCUs
+// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
+void USB1_OTG_HS_IRQHandler(void) {
+  tusb_int_handler(1, true);
+}
+
+void board_init(void) {
+
+  /* Enable BusFault and SecureFault handlers (HardFault is default) */
+  SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
+
+  HAL_PWREx_EnableVddA();
+  HAL_PWREx_EnableVddIO2();
+  HAL_PWREx_EnableVddIO3();
+  HAL_PWREx_EnableVddIO4();
+  HAL_PWREx_EnableVddIO5();
+
+  HAL_Init();
+
+  // Implemented in board.h
+  SystemClock_Config();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPION_CLK_ENABLE();
+  __HAL_RCC_GPIOO_CLK_ENABLE();
+  __HAL_RCC_GPIOP_CLK_ENABLE();
+  __HAL_RCC_GPIOQ_CLK_ENABLE();
+
+  // HAL_ICACHE_Enable();
+
+  for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
+    HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
+  }
+
+  NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
+  NVIC_EnableIRQ(UCPD1_IRQn);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+
+  NVIC_SetPriority(USB1_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+
+
+#ifdef UART_DEV
+  UART_CLK_EN();
+  HAL_UART_Init(&UartHandle);
+#endif
+
+
+  __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWREx_EnableVddUSBVMEN();
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
+  HAL_PWREx_EnableVddUSB();
+
+  LL_AHB5_GRP1_ForceReset(0x00800000);
+  __HAL_RCC_USB1_OTG_HS_FORCE_RESET();
+  __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET();
+
+  LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
+  LL_AHB5_GRP1_ReleaseReset(0x00800000);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
+
+  /* Required few clock cycles before accessing USB PHY Controller Registers */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
+
+  USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
+                              (0x2 << 4)  |
+                              (0x1 << 2)  |
+                                0x1U;
+
+  __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
+
+  /* Required few clock cycles before Releasing Reset */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  __HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
+
+  /* Peripheral PHY clock enable */
+  __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
+
+  board_init2();
+
+#if CFG_TUH_ENABLED
+  board_vbus_set(BOARD_TUH_RHPORT, 1);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#ifdef PINID_LED
+  board_pindef_t* pindef = &board_pindef[PINID_LED];
+  GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
+  HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
+#else
+  (void) state;
+#endif
+}
+
+uint32_t board_button_read(void) {
+#ifdef PINID_BUTTON
+  board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
+  return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
+#else
+  return 0;
+#endif
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len;
+  return -1;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake
new file mode 100644
index 000000000..76763937e
--- /dev/null
+++ b/hw/bsp/stm32n6/family.cmake
@@ -0,0 +1,148 @@
+include_guard()
+
+set(ST_FAMILY n6)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif ()
+
+# N6 are all high speed
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  set(RHPORT_DEVICE_SPEED OPT_MODE_HIGH_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  set(RHPORT_HOST_SPEED OPT_MODE_HIGH_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+  if(NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
+  endif()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+  if(NOT DEFINED LD_FILE_IAR)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  endif()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_fsbl.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    SEGGER_RTT_SECTION="noncacheable_buffer"
+    BUFFER_SIZE_UP=0x3000
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk
new file mode 100644
index 000000000..37087ed42
--- /dev/null
+++ b/hw/bsp/stm32n6/family.mk
@@ -0,0 +1,89 @@
+ST_FAMILY = n6
+ST_PREFIX = stm32${ST_FAMILY}xx
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
+ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203
+
+UF2_FAMILY_ID = 0x6db66083
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m55
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 1
+
+ifndef RHPORT_DEVICE_SPEED
+  RHPORT_DEVICE_SPEED = OPT_MODE_HIGH_SPEED
+endif
+
+ifndef RHPORT_HOST_SPEED
+  RHPORT_HOST_SPEED = OPT_MODE_HIGH_SPEED
+endif
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32N6 \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
+	-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
+	-DBUFFER_SIZE_UP=0x3000 \
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += \
+  -Wno-error=cast-align \
+  -Wno-error=unused-parameter \
+
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_fsbl.s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32n6/partition_stm32n657xx.h b/hw/bsp/stm32n6/partition_stm32n657xx.h
new file mode 100644
index 000000000..4efdc5668
--- /dev/null
+++ b/hw/bsp/stm32n6/partition_stm32n657xx.h
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n657xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32N657XX_H
+#define PARTITION_STM32N657XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          0
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x00000000      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00000000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x00000000      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x00000000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x00000000      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x00000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x00000000      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  PVD_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DTS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LOCKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CACHE_ECC_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TCM_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.7>  BKP_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> RIFSC_TAMPER_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.13> IAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> IWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.27> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  SAES_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CRYP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.8>  RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> MCE1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.11> MCE2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> MCE3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.13> MCE4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.14> ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> CSI_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DCMIPP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.19> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.20> PAHB_ERR_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.21> NPU0_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> NPU1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> NPU2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> NPU3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> CACHEAXI_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.26> LTDC_LO_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> LTDC_LO_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMA2D_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> JPEG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> VENC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> GFXMMU_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  GFXTIM_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPU2D_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPU2D_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  HPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  HPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  HPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  HPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  HPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.10> HPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.11> HPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.12> HPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.13> HPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.20> GPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> GPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> GPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> GPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> GPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.25> GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.3>  GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.9>  I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.10> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> I3C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> I3C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.29> TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> TIM9_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.31> TIM10_IRQn            <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS3_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..159
+//   <o.0>  TIM11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM12_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM13_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM14_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM18_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.11> LPTIM4_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> LPTIM5_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.13> ADF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.14> MDF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.15> MDF1_FLT1_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.16> MDF1_FLT2_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.17> MDF1_FLT3_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.18> MDF1_FLT4_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.19> MDF1_FLT5_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.20> SAI1_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.21> SAI1_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> SAI2_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> SAI2_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPDIFRX1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> SPI5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> SPI6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    1
+
+/*
+// Interrupts 160..191
+//   <o.0>  USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  USART6_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  UART8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  UART9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  USART10_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.10> XSPI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> XSPI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> XSPI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.16> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> USB1_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.18> USB2_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.19> ETH1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.21> FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.22> FDCAN2_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.23> FDCAN2_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.24> FDCAN3_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.25> FDCAN3_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.26> FDCAN_CU_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.27> MDIOS_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> DCMI_PSSI_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> WAKEUP_PIN_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.30> CTI_INT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.31> CTI_INT1_IRQn       <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    1
+
+/*
+// Interrupts 192..223
+//   <o.0>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LTDC_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LTDC_UP_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32N657XX_H */
diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
new file mode 100644
index 000000000..00cb31159
--- /dev/null
+++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
@@ -0,0 +1,504 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32n6xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CONF_H
+#define STM32N6xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED      */
+/*#define HAL_BSEC_MODULE_ENABLED     */
+/*#define HAL_CRC_MODULE_ENABLED      */
+/*#define HAL_CRYP_MODULE_ENABLED     */
+/*#define HAL_DCMI_MODULE_ENABLED     */
+/*#define HAL_DCMIPP_MODULE_ENABLED   */
+/*#define HAL_DMA2D_MODULE_ENABLED    */
+/*#define HAL_DTS_MODULE_ENABLED      */
+/*#define HAL_ETH_MODULE_ENABLED      */
+/*#define HAL_EXTI_MODULE_ENABLED     */
+/*#define HAL_FDCAN_MODULE_ENABLED    */
+/*#define HAL_GFXMMU_MODULE_ENABLED   */
+/*#define HAL_GFXTIM_MODULE_ENABLED   */
+/*#define HAL_HASH_MODULE_ENABLED     */
+/*#define HAL_HCD_MODULE_ENABLED      */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED      */
+/*#define HAL_I3C_MODULE_ENABLED      */
+/*#define HAL_ICACHE_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED     */
+/*#define HAL_IWDG_MODULE_ENABLED     */
+/*#define HAL_JPEG_MODULE_ENABLED     */
+/*#define HAL_LPTIM_MODULE_ENABLED    */
+/*#define HAL_LTDC_MODULE_ENABLED     */
+/*#define HAL_MCE_MODULE_ENABLED      */
+/*#define HAL_MDF_MODULE_ENABLED      */
+/*#define HAL_MMC_MODULE_ENABLED      */
+/*#define HAL_NAND_MODULE_ENABLED     */
+/*#define HAL_NOR_MODULE_ENABLED      */
+/*#define HAL_PCD_MODULE_ENABLED      */
+/*#define HAL_PKA_MODULE_ENABLED      */
+/*#define HAL_PSSI_MODULE_ENABLED     */
+/*#define HAL_RAMCFG_MODULE_ENABLED   */
+/*#define HAL_RIF_MODULE_ENABLED      */
+/*#define HAL_RNG_MODULE_ENABLED      */
+/*#define HAL_RTC_MODULE_ENABLED      */
+/*#define HAL_SAI_MODULE_ENABLED      */
+/*#define HAL_SD_MODULE_ENABLED       */
+/*#define HAL_SDIO_MODULE_ENABLED     */
+/*#define HAL_SDRAM_MODULE_ENABLED    */
+/*#define HAL_SMARTCARD_MODULE_ENABLED*/
+/*#define HAL_SMBUS_MODULE_ENABLED    */
+/*#define HAL_SPDIFRX_MODULE_ENABLED  */
+/*#define HAL_SPI_MODULE_ENABLED      */
+/*#define HAL_SRAM_MODULE_ENABLED     */
+/*#define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED    */
+/*#define HAL_WWDG_MODULE_ENABLED     */
+/*#define HAL_XSPI_MODULE_ENABLED     */
+/*#define HAL_CACHEAXI_MODULE_ENABLED */
+/*#define HAL_MDIOS_MODULE_ENABLED    */
+/*#define HAL_GPU2D_MODULE_ENABLED    */
+/*#define HAL_CACHEAXI_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE              48000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE              32768UL   /*!< Value of the External oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+#define MSI_VALUE              4000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE              64000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE               32000UL    /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz */
+/* The real value may vary depending on the variations in voltage and temperature.*/
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                  3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY          15U  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                   0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32n6xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define  USE_HAL_ADC_REGISTER_CALLBACKS       0U /* ADC register callback disabled       */
+#define  USE_HAL_CACHEAXI_REGISTER_CALLBACKS  0U /* CACHEAXI register callback disabled  */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS      0U /* CRYP register callback disabled      */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS      0U /* DCMI register callback disabled      */
+#define  USE_HAL_DCMIPP_REGISTER_CALLBACKS    0U /* DCMIPP register callback disabled    */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS     0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS       0U /* DTS register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS       0U /* ETH register callback disabled       */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS     0U /* FDCAN register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS    0U /* GFXMMU register callback disabled    */
+#define  USE_HAL_GFXTIM_REGISTER_CALLBACKS    0U /* GFXTIM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS      0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS       0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS       0U /* I2C register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS       0U /* I2S register callback disabled       */
+#define  USE_HAL_I3C_REGISTER_CALLBACKS       0U /* I3C register callback disabled       */
+#define  USE_HAL_IWDG_REGISTER_CALLBACKS      0U /* IWDG register callback disabled      */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS      0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS     0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS      0U /* LTDC register callback disabled      */
+#define  USE_HAL_MCE_REGISTER_CALLBACKS       0U /* MCE register callback disabled       */
+#define  USE_HAL_MDF_REGISTER_CALLBACKS       0U /* MDF register callback disabled       */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS       0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS      0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS       0U /* NOR register callback disabled       */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS       0U /* PCD register callback disabled       */
+#define  USE_HAL_PKA_REGISTER_CALLBACKS       0U /* PKA register callback disabled       */
+#define  USE_HAL_PSSI_REGISTER_CALLBACKS      0U /* PSSI register callback disabled      */
+#define  USE_HAL_RAMCFG_REGISTER_CALLBACKS    0U /* RAMCFG register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS       0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS       0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS       0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS        0U /* SD register callback disabled        */
+#define  USE_HAL_SDIO_REGISTER_CALLBACKS      0U /* SDIO register callback disabled      */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS     0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS     0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS   0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS       0U /* SPI register callback disabled       */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS      0U /* SRAM register callback disabled      */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS       0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS      0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS     0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS      0U /* WWDG register callback disabled      */
+#define  USE_HAL_XSPI_REGISTER_CALLBACKS      0U /* XSPI register callback disabled      */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC                   0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER            0U
+
+/* ################## SDIO peripheral configuration ########################## */
+#define USE_SDIO_TRANSCEIVER          1U
+#define SDIO_MAX_IO_NUMBER            7U /*!< SDIO device support maximum IO number */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32n6xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32n6xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_RIF_MODULE_ENABLED
+#include "stm32n6xx_hal_rif.h"
+#endif /* HAL_RIF_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32n6xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CACHEAXI_MODULE_ENABLED
+#include "stm32n6xx_hal_cacheaxi.h"
+#endif /* HAL_CACHEAXI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32n6xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32n6xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_BSEC_MODULE_ENABLED
+#include "stm32n6xx_hal_bsec.h"
+#endif /* HAL_BSEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32n6xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32n6xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32n6xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DCMIPP_MODULE_ENABLED
+#include "stm32n6xx_hal_dcmipp.h"
+#endif /* HAL_DCMIPP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32n6xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+#include "stm32n6xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+#include "stm32n6xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32n6xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32n6xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+#include "stm32n6xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_GFXTIM_MODULE_ENABLED
+#include "stm32n6xx_hal_gfxtim.h"
+#endif /* HAL_GFXTIM_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32n6xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+#include "stm32n6xx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32n6xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32n6xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32n6xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32n6xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_I3C_MODULE_ENABLED
+#include "stm32n6xx_hal_i3c.h"
+#endif /* HAL_I3C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32n6xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32n6xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32n6xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+#include "stm32n6xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32n6xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32n6xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_MCE_MODULE_ENABLED
+#include "stm32n6xx_hal_mce.h"
+#endif /* HAL_MCE_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+#include "stm32n6xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+#include "stm32n6xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32n6xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32n6xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32n6xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32n6xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32n6xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32n6xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#include "stm32n6xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32n6xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32n6xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32n6xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32n6xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32n6xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32n6xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDIO_MODULE_ENABLED
+#include "stm32n6xx_hal_sdio.h"
+#endif /* HAL_SDIO_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#include "stm32n6xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32n6xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32n6xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+#include "stm32n6xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32n6xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32n6xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32n6xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32n6xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32n6xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32n6xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+#include "stm32n6xx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macros -----------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CONF_H */
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
index ae63afef3..0a2c47030 100644
--- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
@@ -1,11 +1,9 @@
+MCU_VARIANT = stm32u585xx
 CFLAGS += \
   -DSTM32U585xx \
 
 # All source paths should be relative to the top level.
 LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
-
-MCU_VARIANT = stm32u585xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u585zi
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
index 072c595fb..0aba57ce4 100644
--- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
@@ -1,11 +1,9 @@
+MCU_VARIANT = stm32u545xx
 CFLAGS += \
   -DSTM32U545xx \
 
 # All source paths should be relative to the top level.
 LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s
-
-MCU_VARIANT = stm32u545xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u545re
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index fee56f2ba..4bc9fea10 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -1,11 +1,9 @@
+MCU_VARIANT = stm32u575xx
 CFLAGS += \
   -DSTM32U575xx \
 
 # All source paths should be relative to the top level.
 LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
-
-MCU_VARIANT = stm32u575xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575ai
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
index c83ec3999..d09dc5c46 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -1,11 +1,9 @@
+MCU_VARIANT = stm32u575xx
 CFLAGS += \
   -DSTM32U575xx \
 
 # All source paths should be relative to the top level.
 LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
-
-MCU_VARIANT = stm32u575xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
index 4bebe3330..c9fdbac1a 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -1,3 +1,4 @@
+MCU_VARIANT = stm32u5a5xx
 CFLAGS += \
   -DSTM32U5A5xx \
   -DHSE_VALUE=16000000UL \
@@ -5,8 +6,5 @@ CFLAGS += \
 # All source paths should be relative to the top level.
 LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
-
-MCU_VARIANT = stm32u5a5xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 05fe4608a..3694b1ca0 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -1,5 +1,4 @@
 ST_FAMILY = u5
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
@@ -57,5 +56,12 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/$(BOARD_PATH)
 
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
+
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
index 916f11866..c16235586 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
@@ -3,21 +3,26 @@
 **
 **  File        : stm32wb55xx_flash_cm4.ld
 **
-**  Abstract    : System Workbench Minimal System calls file
+**  Author      : STM32CubeIDE
 **
-** 		          For more information about which c-functions
-**                need which of these lowlevel functions
-**                please consult the Newlib libc-manual
+**  Abstract    : Linker script for STM32WB55xx Device
+**                     1024Kbytes FLASH
+**                      128Kbytes RAM
 **
-**  Environment : System Workbench for MCU
+**                Set heap size, stack size and stack location according
+**                to application requirements.
 **
-**  Distribution: The file is distributed “as is,” without any warranty
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
 **                of any kind.
 **
 *****************************************************************************
 ** @attention
 **
-** Copyright (c) 2019 STMicroelectronics.
+** Copyright (c) 2019-2022 STMicroelectronics.
 ** All rights reserved.
 **
 ** This software is licensed under terms that can be found in the LICENSE file
@@ -33,7 +38,7 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = 0x20030000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x400;      /* required amount of heap  */
+_Min_Heap_Size  = 0x400;    /* required amount of heap  */
 _Min_Stack_Size = 0x1000;   /* required amount of stack */
 
 /* Specify the memory areas */
@@ -81,14 +86,17 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
   .ARM : {
     __exidx_start = .;
     *(.ARM.exidx*)
     __exidx_end = .;
   } >FLASH
 
-  .preinit_array     :
+  .preinit_array :
   {
     PROVIDE_HIDDEN (__preinit_array_start = .);
     KEEP (*(.preinit_array*))
@@ -124,7 +132,6 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM1 AT> FLASH
 
-
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -152,8 +159,6 @@ SECTIONS
     . = ALIGN(8);
   } >RAM1
 
-
-
   /* Remove information from the standard libraries */
   /DISCARD/ :
   {
@@ -163,7 +168,15 @@ SECTIONS
   }
 
   .ARM.attributes 0       : { *(.ARM.attributes) }
-   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
-   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
-   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+  MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+  MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+
+  /* used by the startup to initialize .MB_MEM2 data */
+  _siMB_MEM2 = LOADADDR(.MB_MEM2);
+  .MB_MEM2 :
+  {
+    _sMB_MEM2 = . ;
+    *(MB_MEM2) ;
+    _eMB_MEM2 = . ;
+  } >RAM_SHARED AT> FLASH
 }
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index ba37b7cc3..93aba02fa 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -184,8 +184,7 @@ void HardFault_Handler(void) {
   asm("bkpt 1");
 }
 
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
+// Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles.
+void _init(void);
 void _init(void) {
-
 }
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index de8372eea..a80ff6f5b 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -9,14 +9,12 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m4
 
 CFLAGS += \
-  -flto \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32WB
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align -Wno-unused-parameter
-
-LD_FILE ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld
+CFLAGS_GCC += \
+  -flto \
+  -nostdlib -nostartfiles \
+	-Wno-error=cast-align -Wno-unused-parameter
 
 LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
@@ -25,19 +23,26 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
 	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}_cm4.s
-
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_cm4.s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT)_cm4.s
+
+# Linker
+LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm4.icf
+
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index a1679a2f0..4eed7360a 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -1,8 +1,6 @@
 UF2_FAMILY_ID = 0x00
 SDK_DIR = hw/mcu/infineon/mtb-xmclib-cat3
 
-DEPS_SUBMODULES += ${SDK_DIR}
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m4
 
diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake
index 91ffc3a39..b60e97ef4 100644
--- a/hw/bsp/zephyr_board_aliases.cmake
+++ b/hw/bsp/zephyr_board_aliases.cmake
@@ -1 +1,2 @@
 set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840)
+set(stm32n657nucleo_BOARD_ALIAS nucleo_n657x0_q)
author	hathach <[email protected]>	2025-07-04 09:49:28 +0700
committer	hathach <[email protected]>	2025-07-04 09:49:28 +0700
commit	1b5f97ff23776279a011e2ab14a85f29e1aa6c10 (patch)
tree	0328289336a2b135cd8455dab70dd9bd77737590 /hw
parent	cd2b3a53217857930bd8519d074b355ae8933982 (diff)
parent	9d872d529ffa0aa53e735b24543c26156798fc64 (diff)