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authorzhiqiang-ch <[email protected]>2025-12-31 14:53:29 +0800
committerGitHub <[email protected]>2025-12-31 14:53:29 +0800
commit8544db8bf5e6b83527fb0e1d903a70f90cbb8873 (patch)
tree487ab3431a26acd95a889b3c9f1b126d71adafdb /src/common
parent239e20ba7399fc026325c4cd8c98c08a160a9773 (diff)
parent3eafddb02a3347873dc1816f53b428518eb97c61 (diff)
Merge branch 'hathach:master' into master
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_mcu.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index ce690acb8..72df0a6b3 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -245,13 +245,12 @@
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
- #include "stm32h7xx.h"
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
#define TUP_DCD_ENDPOINT_MAX 9
- #if __CORTEX_M == 7
+ #ifndef CORE_CM4
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE