summaryrefslogtreecommitdiff
path: root/src/host
diff options
context:
space:
mode:
authorHa Thach <[email protected]>2023-07-24 21:38:46 +0700
committerGitHub <[email protected]>2023-07-24 21:38:46 +0700
commitfda92fd34a8fe0d08e5c51fab4ea38f6849051e8 (patch)
tree93c878d68b05feae51aa672f5021005297997e30 /src/host
parentf295aaf1851eb270070af7292d1f100f7172daf4 (diff)
parent0b38941362b6ff2fe3fb7aba1507e82798cd9c16 (diff)
Merge branch 'master' into hcd-abort-xfer
Diffstat (limited to 'src/host')
-rw-r--r--src/host/hcd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 90bfd79db..50f1dcdcc 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -110,15 +110,15 @@ typedef struct
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
-void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
-void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
-void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
//--------------------------------------------------------------------+
// Controller API