Initial STM32WBARI eval support

Clean up includes definitions

Remove wait that is not required

Remove redundant settings

Clean up clock configuration to look like other modules

Remove MSP_Init that is not required

Clean up driver code

dhcp: Fix DHCP_OFFER/DHCP_ACK destinaton.

In RFC 2131, the destination of DHCP OFFER/ACK is defined in Section 4.1.
Fix the destination error by following the rule of RFC 2131.
TODO: We implement all rule but the last one. ARP table is required to associate client's macaddr.
Currently, fallback to broadcast.

Signed-off-by: Elwin Huang <[email protected]>

Fix compile error.

Fix goto indentation

Co-authored-by: Copilot <[email protected]>

Fix osal_spin_unlock for mynewt

Mynewt version for osal_spin_unlock() called
OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL.

Signed-off-by: Jerzy Kasenberg <[email protected]>

Add ESP32-C5 and ESP32-C61 definitions

fix(dcd/dwc2): Fix reset procedure for versions >=4.20a

Fix STM32L4 GPIOD clock enable for variants without GPIOD

Add weact blackpill support

Add to boards.rst file

Fix file

Small cleanups.

Insert small delay for LowSpeed device

Improve retry operation at NAK response.

Remove dynamic memory allocation

use tusb_time_millis_api() instead of board_millis()
make loopdelay() always inline

update at32f405 dwc2 info and phy width selection

add at32f415 dwc2 info

add some consumer page configs

remove duplicated enum

Initial plan

Fix obsolete cnt assignment in _tu_fifo_peek() overflow check

Co-authored-by: hathach <[email protected]>

Initial plan

Update STM32 CMSIS dependencies to fix HSITRIM register bug

Co-authored-by: hathach <[email protected]>

Remove accidentally committed dependency directories

Co-authored-by: hathach <[email protected]>

Update all STM32 HAL driver dependencies to latest versions

Co-authored-by: hathach <[email protected]>

fix linker h745 issue with clang

fix linker h745 issue with clang

Update all STM32 CMSIS device dependencies to latest versions

Co-authored-by: hathach <[email protected]>

update pio-usb

Create comprehensive GitHub Copilot instructions and fix pre-commit configuration for TinyUSB (#3234)

* Initial plan

* Create comprehensive GitHub Copilot instructions for TinyUSB

Co-authored-by: hathach <[email protected]>

* Remove accidentally committed dependencies, use tools/get_deps.py instead

Co-authored-by: hathach <[email protected]>

* Fix .gitignore: ignore vendor/ directory not ceedling script

Co-authored-by: hathach <[email protected]>

* Revert .gitignore changes and add README_processed.rst

Co-authored-by: hathach <[email protected]>

* Remove README_processed.rst and revert ceedling file permissions

Co-authored-by: hathach <[email protected]>

* Changes before error encountered

Co-authored-by: hathach <[email protected]>

* Remove redundant manual validation step, keep only pre-commit and build validation

Co-authored-by: hathach <[email protected]>

* fix pre-commit

---------

Co-authored-by: copilot-swe-agent[bot] <[email protected]>
Co-authored-by: hathach <[email protected]>

modified the bsp files of at32 to make them work better

the family name error of at32 has been corrected

fix pre-commit

STM32N6570-DK board is added. Build with DEBUG=1 (make BOARD=stm32n6570dk DEBUG=1 all), otherwise it does not work for now. Tested with examples/device/cdc_dual_ports

3 files changed, 34 insertions, 2 deletions

diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
index ccf31e035..01baf50ae 100644
--- a/src/portable/st/stm32_fsdev/fsdev_stm32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -148,6 +148,12 @@
   /* ST provided header has incorrect value of USB_PMAADDR */
   #define FSDEV_PMA_BASE USB1_PMAADDR
 
+#elif defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx)
+  // Available only on STM32WBA62/64/65xx devices
+  #include "stm32wbaxx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L4
   #include "stm32l4xx.h"
   #define FSDEV_PMA_SIZE (1024u)
@@ -289,6 +295,8 @@ static const IRQn_Type fsdev_irq[] = {
     USB_LP_IRQn,
   #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
     USB_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA
+    USB_OTG_HS_IRQn,
   #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
     USB_DRD_FS_IRQn,
   #else
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index d7d157149..f81cfceda 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -49,6 +49,11 @@ static void reset_core(dwc2_regs_t* dwc2) {
   uint32_t gsnpsid = dwc2->gsnpsid;
 
   // reset core
+
+  // On the STM32WBA peripheral, the device seems to get stuck in reset unless
+  // this shadow register is utilized.
+  uint32_t gsnpsid = dwc2->gsnpsid;
+
   dwc2->grstctl |= GRSTCTL_CSRST;
 
   if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 672891561..ca5ce5a7c 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,6 +113,22 @@ extern "C" {
     #define EP_MAX_HS                 9
     #define EP_FIFO_SIZE_HS           4096
   #endif
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WBA
+  #if defined(STM32WBA62xx)
+    #include "stm32wba62xx.h"
+  #elif defined(STM32WBA64xx)
+    #include "stm32wba64xx.h"
+  #elif defined(STM32WBA65xx)
+    #include "stm32wba65xx.h"
+  #else
+    #error "The selected STM32WBA series chip does not support OTG USB HS"
+  #endif
+
+  #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE_NS
+  #define OTG_HS_IRQn               USB_OTG_HS_IRQn
+  #define EP_MAX_HS                 9
+  #define EP_FIFO_SIZE_HS           4096
 #else
   #error "Unsupported MCUs"
 #endif
@@ -166,6 +182,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
 // MCU specific PHY init, called BEFORE core reset
 // - dwc2 3.30a (H5) use USB_HS_PHYC
 // - dwc2 4.11a (U5) use femtoPHY
+// - dwc2 x.xxx (WBA) use USB_OTG_HS
 static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
     // Enable on-chip FS PHY
@@ -194,11 +211,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
     #endif
 
   } else {
-#if CFG_TUSB_MCU != OPT_MCU_STM32U5
+#if CFG_TUSB_MCU != OPT_MCU_STM32U5 && CFG_TUSB_MCU != OPT_MCU_STM32WBA
     // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
 #endif
-
     // Enable on-chip HS PHY
     if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
       #ifdef USB_HS_PHYC
@@ -233,11 +249,14 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 
       // Enable PLL internal PHY
       USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+<<<<<<< HEAD
 
       // Wait ~2ms until the PLL is ready (there's no RDY bit to query)
       tusb_time_delay_ms_api(2);
       #else
 
+=======
+>>>>>>> 246a92c65 (It worksgit status!)
       #endif
     }
   }