support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phy

4 files changed, 230 insertions, 99 deletions

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 58305838f..0d2766c38 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,7 +31,7 @@
 #include "device/dcd_attr.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103, OPT_MCU_BCM2711) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
@@ -42,6 +42,8 @@
   #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711)
+  #include "dwc2_bcm.h"
 #else
   #error "Unsupported MCUs"
 #endif
@@ -185,7 +187,7 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -226,47 +228,6 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
   dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos);
 }
 
-#if defined(USB_HS_PHYC)
-static bool USB_HS_PHYCInit(void)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable LDO
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
-  {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(0);
-  }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
-
-  return true;
-}
-#endif
-
 static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
 {
   (void) rhport;
@@ -369,7 +330,7 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   TU_LOG_INT(1, hw_cfg3->synch_reset              );
   TU_LOG_INT(1, hw_cfg3->otg_adp_support          );
   TU_LOG_INT(1, hw_cfg3->otg_enable_hsic          );
-  TU_LOG_INT(1, hw_cfg3->otg_bc_support           );
+  TU_LOG_INT(1, hw_cfg3->battery_charger_support  );
   TU_LOG_INT(1, hw_cfg3->lpm_mode                 );
   TU_LOG_INT(1, hw_cfg3->total_fifo_size          );
 
@@ -395,56 +356,102 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   TU_LOG_INT(1, hw_cfg4->dma_dynamic               );
 }
 
+static void reset_core(dwc2_regs_t * dwc2)
+{
+  // reset core
+  dwc2->grstctl |= GRSTCTL_CSRST;
+
+  // wait for reset bit is cleared
+  // TODO version 4.20a should wait for RESET DONE mask
+  while (dwc2->grstctl & GRSTCTL_CSRST) { }
+
+  // wait for AHB master IDLE
+  while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { }
+
+  // wait for device mode ?
+}
+
 void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // Check Synopsys ID
-  uint32_t const gsnpsid = dwc2->gsnpsid & 0xffff0000u;
+  // Check Synopsys ID, failed if controller is not enabled
+  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
 
   print_dwc2_info(dwc2);
 
-  // No HNP/SRP (no OTG support), program timeout later.
-  if ( rhport == 1 )
+  // Force device mode
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+
+  uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type;
+
+  if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE)
   {
-    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
-    // deactivate internal PHY
+    // max speed is full or core does not support highspeed
+    TU_LOG2("Fullspeed PHY init\r\n");
+
+    // Select FS PHY
+    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+
+    // Reset core after selecting PHY
+    reset_core(dwc2);
+
+    #if defined(DCD_ATTR_DWC2_STM32)
+    // activate FS PHY on stm32
+    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+    #endif
+  }else
+  {
+    // Highspeed mode
+
+    #if defined(DCD_ATTR_DWC2_STM32)
+    // Disable STM32 FS PHY
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+    #endif
 
-    // Init The UTMI Interface
-    dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+    uint32_t gusbcfg = dwc2->gusbcfg;
 
-    // Select default internal VBUS Indicator and Drive for ULPI
-    dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-#else
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-#endif
+    // De-select FS PHY
+    gusbcfg &= ~GUSBCFG_PHYSEL;
 
-#if defined(USB_HS_PHYC)
-    // Highspeed with embedded UTMI PHYC
+    if (hs_phy_type == HS_PHY_TYPE_ULPI)
+    {
+      TU_LOG2("Highspeed ULPI PHY init\r\n");
 
-    // Select UTMI Interface
-    dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
-    dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+      // Select ULPI
+      gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 
-    // Enables control of a High Speed USB PHY
-    USB_HS_PHYCInit();
-#endif
-  } else
-  {
-    // Enable internal PHY
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-  }
+      // ULPI 8-bit interface, single data rate
+      gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 
-  // Reset core after selecting PHYst
-  // Wait AHB IDLE, reset then wait until it is cleared
-  while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {}
-  dwc2->grstctl |= GRSTCTL_CSRST;
-  while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
+      // default internal VBUS Indicator and Drive
+      gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+
+      // Disable FS/LS ULPI
+      gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+    }else
+    {
+      TU_LOG2("Highspeed UTMI+ PHY init\r\n");
+
+      // Select UTMI+ with 8-bit interface
+      gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
+
+      // Set 16-bit interface if supported
+      if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+
+      #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
+      dwc2_stm32_utmi_phy_init(dwc2);
+      #endif
+    }
+
+    dwc2->gusbcfg = gusbcfg;
+
+    // Reset core after selecting PHY
+    reset_core(dwc2);
+  }
 
   // Restart PHY clock
   dwc2->pcgctrl = 0;
@@ -463,9 +470,6 @@ void dcd_init (uint8_t rhport)
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
-  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
new file mode 100644
index 000000000..da1f23ae0
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DWC2_BCM_H_
+#define _TUSB_DWC2_BCM_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "broadcom/interrupts.h"
+
+#define DWC2_REG_BASE       0xFE980000UL
+#define DWC2_EP_MAX         8
+#define DWC2_EP_FIFO_SIZE   4096
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  BP_EnableIRQ(USB_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  BP_DisableIRQ(USB_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  // TODO implement later
+}
+
+static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+{
+  // TODO implement later
+  (void) core;
+  (void) speed;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 236936d66..b77cda2ca 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,14 +113,14 @@ static inline void dwc2_remote_wakeup_delay(void)
 }
 
 // Set turn-around timeout according to link speed
-static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed)
 {
-  core->gusbcfg &= ~GUSBCFG_TRDT;
+  dwc2->gusbcfg &= ~GUSBCFG_TRDT;
 
   if ( speed == TUSB_SPEED_HIGH )
   {
     // Use fixed 0x09 for Highspeed
-    core->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
+    dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
   }
   else
   {
@@ -149,11 +149,52 @@ static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
       turnaround = 0xFU;
 
     // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    core->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
+    dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
   }
 }
 
+#if defined(USB_HS_PHYC)
+static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2)
+{
+  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
+
+  // Enable UTMI HS PHY
+  dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+
+  // Enable LDO
+  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+  // Wait until LDO ready
+  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
 
+  uint32_t phyc_pll = 0;
+
+  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+  switch ( HSE_VALUE )
+  {
+    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
+    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
+    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
+    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
+    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
+    default:
+      TU_ASSERT(false, );
+  }
+  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
+
+  // Control the tuning interface of the High Speed PHY
+  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
+  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+  // Enable PLL internal PHY
+  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+
+  // Original ST code has 2 ms delay for PLL stabilization.
+  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
+}
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 113f99180..5ded366d7 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -58,6 +58,13 @@ typedef struct
 } HS_PHYC_GlobalTypeDef;
 #endif
 
+enum {
+  HS_PHY_TYPE_NONE = 0  ,
+  HS_PHY_TYPE_UTMI      , // internal PHY (mostly)
+  HS_PHY_TYPE_ULPI      , // external PHY
+  HS_PHY_TYPE_UTMI_ULPI ,
+};
+
 typedef struct TU_ATTR_PACKED
 {
   uint32_t op_mode                  : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
@@ -90,7 +97,7 @@ typedef struct TU_ATTR_PACKED
   uint32_t synch_reset              : 1;  // 0: async reset | 1: synch reset
   uint32_t otg_adp_support          : 1;  // ADP logic is present along with HSOTG controller
   uint32_t otg_enable_hsic          : 1;  // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
-  uint32_t otg_bc_support           : 1;  // support battery charger
+  uint32_t battery_charger_support  : 1;  // support battery charger
   uint32_t lpm_mode                 : 1;  // LPC mode
   uint32_t total_fifo_size          : 16; // DFIFO depth value in terms of 32-bit words
 }dwc2_ghwcfg3_t;
@@ -494,6 +501,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
 #define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
 
+#define GSNPSID_ID_MASK			             TU_GENMASK(31, 16)
+
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
 #define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
@@ -501,15 +510,16 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             // 0x00000001 */
 #define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             // 0x00000002 */
 #define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             // 0x00000004 */
-#define GUSBCFG_PHYIF_Pos                (3U)
-#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos)             // 0x00000008 */
-#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk                        // PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF16_Pos              (3U)
+#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
+#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
 #define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010 */
 #define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
 #define GUSBCFG_PHYSEL_Pos               (6U)
 #define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
 #define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_DDRSEL			             TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
 #define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
 #define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
@@ -587,6 +597,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
 #define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
 #define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
+#define GRSTCTL_CSFTRST_DONE_Pos		     (29)
+#define GRSTCTL_CSFTRST_DONE		         (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
 #define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
 #define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
@@ -898,6 +910,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000 */
 #define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits */
 
+#if 0
 /********************  Bit definition for OTG register  ********************/
 #define CHNUM_Pos                        (0U)
 #define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F */
@@ -939,6 +952,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000 */
 #define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000 */
 #define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000 */
+#endif
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
@@ -951,18 +965,18 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define NPTXFSA_Pos                      (0U)
-#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
-#define NPTXFSA                          NPTXFSA_Msk                              // Nonperiodic transmit RAM start address */
-#define NPTXFD_Pos                       (16U)
-#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
-#define NPTXFD                           NPTXFD_Msk                               // Nonperiodic TxFIFO depth               */
-#define TX0FSA_Pos                       (0U)
-#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
-#define TX0FSA                           TX0FSA_Msk                               // Endpoint 0 transmit RAM start address  */
-#define TX0FD_Pos                        (16U)
-#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
-#define TX0FD                            TX0FD_Msk                                // Endpoint 0 TxFIFO depth                */
+#define GNPTXFSIZ_NPTXFSA_Pos            (0U)
+#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
+#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address */
+#define GNPTXFSIZ_NPTXFD_Pos             (16U)
+#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
+#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth               */
+#define DIEPTXF0_TX0FSA_Pos              (0U)
+#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
+#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address  */
+#define DIEPTXF0_TX0FD_Pos               (16U)
+#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
+#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)