diff options
| author | HiFiPhile <[email protected]> | 2024-09-24 21:30:16 +0200 |
|---|---|---|
| committer | HiFiPhile <[email protected]> | 2024-09-24 21:30:16 +0200 |
| commit | e483c6a2ade2dbf2ec44d835134f62eab0cf9698 (patch) | |
| tree | 7a9831c30b135a841e0d80abb07ab93f2cec241a /src | |
| parent | 6a15e7875c6bc42247210fdcebdea1a4353c51ea (diff) | |
Add a note about data cache.
Diffstat (limited to 'src')
| -rw-r--r-- | src/tusb_option.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/tusb_option.h b/src/tusb_option.h index 0d118eef9..17de9cd72 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -243,6 +243,10 @@ //--------------------------------------------------------------------+ // DWC2 controller: use DMA for data transfer +// For processors with data cache enabled, USB endpoint buffer region +// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. +// For example, on Cortex-M7 the MPU region can be configured as normal +// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. #ifndef CFG_TUD_DWC2_DMA #define CFG_TUD_DWC2_DMA 0 #endif |