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Co-Authored-By: Claude Fable 5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01HeF2gZ1M7GWkz6Av4BpKPg
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* license: use SPDX identifiers for src/ headers
Replace the full ~20-line MIT license boilerplate on every src/ file with a
two-line SPDX tag (SPDX-FileCopyrightText + SPDX-License-Identifier), following
the REUSE convention used by CircuitPython and the Linux kernel. Removes ~3500
lines of duplicated boilerplate.
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The CH32 workaround only restored EP0 to CONTROL in edpt_xfer(). When
the stack rejects a control write with data (handle_ctr_setup having
already switched EP0 to BULK) it stalls EP0 via dcd_edpt_stall() without
ever calling dcd_edpt_xfer(), leaving EP0 typed BULK+STALL. As SETUP
recognition is tied to CONTROL-typed endpoints, the host's recovery
SETUP (which should auto-clear the stall) would be ignored, wedging EP0
until a bus reset.
Restore CONTROL for EP0 in the same exclusive write that sets the STALL
status. DFU download-in-wrong-state is a concrete trigger.
Co-Authored-By: Claude Fable 5 <[email protected]>
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edpt_xfer() restored EP0 to CONTROL at the top of the function, before
the OUT stage was armed (rx bufsize + STAT_RX=VALID written further
down, with interrupts enabled in between). That re-enabled the CH32
blind OUT ACK while STAT_RX was still NAK and the buffer size stale, so
a host-retried DATA OUT / status ZLP could be ACKed into the wrong
buffer in the gap.
Fold the CONTROL restore into the single exclusive write that programs
STAT_RX=VALID for the OUT direction, after the buffer size is set, so
type and arming go live together. The IN direction keeps the (now
atomic) early restore, where no pending OUT exists to be blind-ACKed.
Co-Authored-By: Claude Fable 5 <[email protected]>
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Parse the setup packet via tusb_control_request_t instead of hand-rolled byte
indexing; drop a stray blank line and fix indentation. No functional change.
Co-Authored-By: Claude Fable 5 <[email protected]>
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ep0_set_type() read the EP0 register outside any critical section and
only ep_write() masked the USB IRQ around the store. A USB interrupt
landing between the read and the write (e.g. a new SETUP whose handler
installs the BULK gate) was silently undone when the task resumed and
wrote back its pre-interrupt snapshot with the type forced to CONTROL,
re-exposing the unsolicited EP0 OUT ACK the workaround blocks.
Bracket the whole read-modify-write with fsdev_int_disable/enable when
called with need_exclusive (task context). ISR-context callers pass
false and are unaffected (the ISR cannot preempt itself).
Co-Authored-By: Claude Fable 5 <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Track EP0 control transfer state from SETUP (direction and wLength) and gate CH32 EP0 handshakes accordingly. Switch EP0 type away from control to bulk to block unsolicited OUT ACKs during control read/write gaps, then restore control type when EP0 transfer is explicitly armed.
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPHile <[email protected]>
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hathach/copilot/extract-hcd-pma-buffer-errata-workaround
Refactor STM32 FSDEV PMA errata delay into shared static inline helper and apply to DCD/HCD with overridable timing
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Signed-off-by: HiFiPhile <[email protected]>
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Agent-Logs-Url: https://github.com/hathach/tinyusb/sessions/3ec0d5b6-cb8e-48ff-8606-3371beb1efcb
Co-authored-by: HiFiPhile <[email protected]>
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- hcd_edpt_clear_stall: use ep_addr instead of hardcoded 0 (control endpoint)
- hcd: add TUP_USBIP_FSDEV_DRD define for MCUs with host support (C0, G0, H5,
U3, U5) and use it in hcd compile guard instead of enumerating MCUs
- dcd_edpt_close_all: use FSDEV_EP_COUNT instead of CFG_TUD_ENDPPOINT_MAX for
PMA btable offset to match handle_bus_reset
- midi host tuh_midi_stream_write: add missing cable_num to system messages,
SysEx, and real-time MIDI packets. Add 0xF mask for SysEx CIN checks.
Aligns with midi_device.c tud_midi_n_stream_write implementation.
Co-Authored-By: Claude Opus 4.6 (1M context) <[email protected]>
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`FSDEV_BUS_32BIT` with `CFG_TUSB_FSDEV_32BIT`, adjust data/address stride macros, and refactor register/PMU access for consistency across platforms.
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microcontrollers. Replace vendor-specific macros with unified `U_`-prefixed equivalents, ensuring consistency and reducing duplication across all platforms.
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read/write
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duplicated packet write/read for fsdev
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: Zixun LI <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Co-authored-by: Copilot <[email protected]>
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Co-authored-by: HiFiPhile <[email protected]>
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Signed-off-by: Mengsk <[email protected]>
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Controlled by the embedder defining CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP
in tusb_config.h. If hardware does have SBUF_ISO bit it will use only
one half of endpoint pair register.
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consistent
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improve hil test failed output
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EP0 OUT, which can incorrectly use queued_len of previous transfer. So reset total_len and queued_len to 0.
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without usbd consent
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