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path: root/src/portable/synopsys/dwc2/dwc2_stm32.h
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2026-07-02license: use SPDX identifiers for src/ headers (#3749)Ha Thach
* license: use SPDX identifiers for src/ headers Replace the full ~20-line MIT license boilerplate on every src/ file with a two-line SPDX tag (SPDX-FileCopyrightText + SPDX-License-Identifier), following the REUSE convention used by CircuitPython and the Linux kernel. Removes ~3500 lines of duplicated boilerplate.
2026-04-10fix DWC2 FIFO depth values for STM32 familieshathach
2026-04-10add dwc2_clock_init() to have nrf54 initial sequence. currently stub for ↵hathach
other ports. add board_uart_read() for nrf
2026-04-09rename ep_fifo_size (bytes) to otg_dfifo_depth (words)hathach
2026-03-05add hs_phy_type parameter to dwc2_phy_deinit for selective PHY ↵hathach
deinitialization across all MCUs
2026-03-04add PHY deinitialization support for DWC2 driver across all MCUshathach
2026-02-13add CFG_TUD_VBUS_SENSE, that could allow to skip tud_configure() for fixed ↵hathach
vbus sensing simplify dwc2_stm32_gccfg_cfg() using guid value
2026-01-31dwc2: add stm32n6 DMA regionsHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2026-01-31dwc2: add vbus sense configHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2025-11-26dwc2 stm32 check if dcache enabled before calling SCB DCache functionhathach
2025-11-04Fixed more alert found by PVS-Studiohathach
2025-09-10Bring up to date with masterDalton Caron
2025-09-10Initial STM32WBARI eval supportDalton Caron
Clean up includes definitions Remove wait that is not required Remove redundant settings Clean up clock configuration to look like other modules Remove MSP_Init that is not required Clean up driver code dhcp: Fix DHCP_OFFER/DHCP_ACK destinaton. In RFC 2131, the destination of DHCP OFFER/ACK is defined in Section 4.1. Fix the destination error by following the rule of RFC 2131. TODO: We implement all rule but the last one. ARP table is required to associate client's macaddr. Currently, fallback to broadcast. Signed-off-by: Elwin Huang <[email protected]> Fix compile error. Fix goto indentation Co-authored-by: Copilot <[email protected]> Fix osal_spin_unlock for mynewt Mynewt version for osal_spin_unlock() called OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL. Signed-off-by: Jerzy Kasenberg <[email protected]> Add ESP32-C5 and ESP32-C61 definitions fix(dcd/dwc2): Fix reset procedure for versions >=4.20a Fix STM32L4 GPIOD clock enable for variants without GPIOD Add weact blackpill support Add to boards.rst file Fix file Small cleanups. Insert small delay for LowSpeed device Improve retry operation at NAK response. Remove dynamic memory allocation use tusb_time_millis_api() instead of board_millis() make loopdelay() always inline update at32f405 dwc2 info and phy width selection add at32f415 dwc2 info add some consumer page configs remove duplicated enum Initial plan Fix obsolete cnt assignment in _tu_fifo_peek() overflow check Co-authored-by: hathach <[email protected]> Initial plan Update STM32 CMSIS dependencies to fix HSITRIM register bug Co-authored-by: hathach <[email protected]> Remove accidentally committed dependency directories Co-authored-by: hathach <[email protected]> Update all STM32 HAL driver dependencies to latest versions Co-authored-by: hathach <[email protected]> fix linker h745 issue with clang fix linker h745 issue with clang Update all STM32 CMSIS device dependencies to latest versions Co-authored-by: hathach <[email protected]> update pio-usb Create comprehensive GitHub Copilot instructions and fix pre-commit configuration for TinyUSB (#3234) * Initial plan * Create comprehensive GitHub Copilot instructions for TinyUSB Co-authored-by: hathach <[email protected]> * Remove accidentally committed dependencies, use tools/get_deps.py instead Co-authored-by: hathach <[email protected]> * Fix .gitignore: ignore vendor/ directory not ceedling script Co-authored-by: hathach <[email protected]> * Revert .gitignore changes and add README_processed.rst Co-authored-by: hathach <[email protected]> * Remove README_processed.rst and revert ceedling file permissions Co-authored-by: hathach <[email protected]> * Changes before error encountered Co-authored-by: hathach <[email protected]> * Remove redundant manual validation step, keep only pre-commit and build validation Co-authored-by: hathach <[email protected]> * fix pre-commit --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: hathach <[email protected]> modified the bsp files of at32 to make them work better the family name error of at32 has been corrected fix pre-commit STM32N6570-DK board is added. Build with DEBUG=1 (make BOARD=stm32n6570dk DEBUG=1 all), otherwise it does not work for now. Tested with examples/device/cdc_dual_ports
2025-09-10Merge pull request #3126 from salkinium/fix/phyc_pllHa Thach
[stm32] Wait until the PHYC PLL is stable
2025-09-10use tusb_time_delay_ms_api for delay, also move tusb_time api to common.hhathach
2025-07-07change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1hathach
use stock iar linker
2025-07-05Use DMA enable for DCache conditionHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2025-06-13Add STM32 DWC2 cache supportHiFiPhile
Signed-off-by: HiFiPhile <[email protected]>
2025-06-12merge n6 and h7rs (same config)hathach
2025-06-04chore: squash previous commits from other branchesJames Sandison
2025-05-17[stm32] Wait until the PHYC PLL is stableNiklas Hauser
2024-11-16Add support for STM32H7RSxxChintalagiri Shashank
2024-10-17get hpri triggeredhathach
2024-09-30update/rename ghwcfg registershathach
2024-01-10Disable ULPI clock during sleep on stm32f7 when using internal phyAlex Voinea
2023-11-22fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clockhathach
2023-10-31usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL sethathach
2023-10-30addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to ↵hathach
get passed otg clock reset
2023-10-18adding nulceo stm32u5a5, fix clock configure issuehathach
dwc2 core stuck at reset
2023-09-26Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chipsbac
2023-01-11dwc2: fix IAR warnings.MasterPhi
2022-12-04Fix typosBastien Nocera
2022-10-13Add support for STM32U5 mcuLynnL4
2022-09-13re-added code in pr 1438 to fix compile with h7 with 1 usb otghathach
2022-06-29fix buid_board.py scripthathach
2022-06-24add more warning option, also fix -Wconversion with rp2040hathach
-Wuninitialized, -Wunused, -Wredundant-decls
2022-06-06more ci fixhathach
2022-06-04update all dwc2 ports to support new dynamic controller supporthathach
2022-06-03make dwc2 stm32 rhport support dynamichathach
2022-04-20Update dwc2_stm32.hNikitarc
Add missing #endif
2022-04-19Update dwc2_stm32.hNikitarc
Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
2021-10-30add support for EFM32GGhathach
merge GG12 GG12 to simply OPT_MCU_EFM32GG
2021-10-29skip snpsid check for gd32, abstract phyfs turnaround, set max timeout ↵hathach
calibration. still has issue with gd32 with msc (does work with running with rtt as log).
2021-10-28support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phyhathach
2021-10-26add epin, epout to dwc2 regshathach
2021-10-26more renamehathach
2021-10-26update dwc2_typehathach
2021-10-25moving esp32s2 to dwc2, abstract dwc2_set_turnaround()hathach
2021-10-25update dwc int enable/disablehathach
2021-10-25switch gd32 and stm32f4 to use new dwc2 driverhathach
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-31 22:08:48 +0000