Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

Two fixes for R-Car Gen5 RSIP, one to surely build u-boot-elf.shdr and
one to make u-boot-elf.shdr compatible with tooling.

Two fixes for R-Car Gen4, which could hang in SPL without them.

4 files changed, 25 insertions, 24 deletions

diff --git a/Kconfig b/Kconfig
index 8428d039a1c..99b896b6cf1 100644
--- a/Kconfig
+++ b/Kconfig
@@ -548,7 +548,8 @@ config REMAKE_ELF
 
 config BUILD_TARGET
 	string "Build target special images"
-	default "u-boot-elf.srec" if RCAR_64
+	default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP
+	default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
 	default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4
index 2439501d07e..39814950b1a 100644
--- a/arch/arm/mach-renesas/Kconfig.rcar4
+++ b/arch/arm/mach-renesas/Kconfig.rcar4
@@ -11,12 +11,14 @@ config R8A779A0
 config R8A779F0
 	bool "Renesas SoC R8A779F0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	imply CLK_R8A779F0
 	imply PINCTRL_PFC_R8A779F0
 
 config R8A779G0
 	bool "Renesas SoC R8A779G0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	select BINMAN
 	select SUPPORT_SPL
 	imply SPL
@@ -33,6 +35,7 @@ config R8A779G0
 config R8A779H0
 	bool "Renesas SoC R8A779H0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	imply CLK_R8A779H0
 	imply PINCTRL_PFC_R8A779H0
 
diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile
index 83c576d6007..4c8dbc465a6 100644
--- a/arch/arm/mach-renesas/Makefile
+++ b/arch/arm/mach-renesas/Makefile
@@ -50,6 +50,8 @@ quiet_cmd_srec_cat = SRECCAT $@
 quiet_cmd_srec_shdr_cat = SRECCAT $@
       cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
 			-Output_Block_Size 16 \
+			-DISable Data_Count \
+			-Execution_Start_Address 0x18400000 \
 			-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
 			-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
 			-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c
index e4c1190eac7..5a0b0ebe115 100644
--- a/board/renesas/common/gen4-spl.c
+++ b/board/renesas/common/gen4-spl.c
@@ -18,6 +18,12 @@
 #include <mapmem.h>
 #include <spl.h>
 
+#define APMU_BASE			0xe6170000U
+#define CL0GRP3_BIT			BIT(3)
+#define CL1GRP3_BIT			BIT(7)
+#define RTGRP3_BIT			BIT(19)
+#define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
+
 #define CNTCR_EN	BIT(0)
 
 #ifdef CONFIG_SPL_BUILD
@@ -47,6 +53,18 @@ void board_init_f(ulong dummy)
 	struct udevice *dev;
 	int ret;
 
+	/* Unlock CPG access */
+	writel(0x5A5AFFFF, CPGWPR);
+	writel(0xA5A50000, CPGWPCR);
+	init_generic_timer();
+
+	/* Define for Work Around of APMU */
+	writel(0x00ff00ff, APMU_BASE + 0x10);
+	writel(0x00ff00ff, APMU_BASE + 0x14);
+	writel(0x00ff00ff, APMU_BASE + 0x18);
+	writel(0x00ff00ff, APMU_BASE + 0x1c);
+	clrbits_le32(APMU_BASE + 0x68, BIT(29));
+
 	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
 		ret = spl_early_init();
 		if (ret) {
@@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
 	return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
 }
 
-#define APMU_BASE 0xe6170000U
-#define CL0GRP3_BIT			BIT(3)
-#define CL1GRP3_BIT			BIT(7)
-#define RTGRP3_BIT			BIT(19)
-#define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
-
-int mach_cpu_init(void)
-{
-	/* Unlock CPG access */
-	writel(0x5A5AFFFF, CPGWPR);
-	writel(0xA5A50000, CPGWPCR);
-	init_generic_timer();
-
-	/* Define for Work Around of APMU */
-	writel(0x00ff00ff, APMU_BASE + 0x10);
-	writel(0x00ff00ff, APMU_BASE + 0x14);
-	writel(0x00ff00ff, APMU_BASE + 0x18);
-	writel(0x00ff00ff, APMU_BASE + 0x1c);
-	clrbits_le32(APMU_BASE + 0x68, BIT(29));
-
-	return 0;
-}
-
 void reset_cpu(void)
 {
 }