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| author | Hrushikesh Salunke <[email protected]> | 2026-02-16 15:58:33 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-03-16 08:24:04 -0600 |
| commit | 3c28bf7719130158c2acd86c45df95262b6b8fa1 (patch) | |
| tree | a58510b7c8e063b38c3d038c4c10bc6508774c76 | |
| parent | d83eefab8cfd58b8e4259734b2e19b30a8659461 (diff) | |
configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
Signed-off-by: Hrushikesh Salunke <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
| -rw-r--r-- | configs/j784s4_evm_a72_defconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index f440b18c6fc..7ca5e88276e 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -44,9 +44,16 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tispl.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y |