diff options
| author | Julien Stephan <[email protected]> | 2026-07-15 16:28:46 +0200 |
|---|---|---|
| committer | David Lechner <[email protected]> | 2026-07-29 10:10:10 -0500 |
| commit | 4b040cc0df1be6bc51617649d625a336bd41797d (patch) | |
| tree | bb9da3cbf60e0023134526ee6dcd871e759c42b1 | |
| parent | 3e50b3c680a17faac601eec036e82c6e13431285 (diff) | |
clk: mediatek: mt8183: use driver data to store the clock tree
Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8183 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-18-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index c2c8957c740..97e2aaddab4 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -794,16 +794,6 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24), }; -static int mt8183_apmixedsys_probe(struct udevice *dev) -{ - return mtk_common_clk_init(dev, &mt8183_apmixed_clk_tree); -} - -static int mt8183_topckgen_probe(struct udevice *dev) -{ - return mtk_common_clk_init(dev, &mt8183_topckgen_clk_tree); -} - static const struct mtk_clk_tree mt8183_infracfg_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -812,12 +802,18 @@ static const struct mtk_clk_tree mt8183_infracfg_tree = { }; static const struct udevice_id mt8183_apmixed_compat[] = { - { .compatible = "mediatek,mt8183-apmixedsys", }, + { + .compatible = "mediatek,mt8183-apmixedsys", + .data = (ulong)&mt8183_apmixed_clk_tree, + }, { } }; static const struct udevice_id mt8183_topckgen_compat[] = { - { .compatible = "mediatek,mt8183-topckgen", }, + { + .compatible = "mediatek,mt8183-topckgen", + .data = (ulong)&mt8183_topckgen_clk_tree, + }, { } }; @@ -834,7 +830,7 @@ U_BOOT_DRIVER(mt8183_clk_apmixedsys) = { .id = UCLASS_CLK, .of_match = mt8183_apmixed_compat, .bind = mtk_common_clk_parent_bind, - .probe = mt8183_apmixedsys_probe, + .probe = mt8183_clk_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_apmixedsys_ops, .flags = DM_FLAG_PRE_RELOC, @@ -845,7 +841,7 @@ U_BOOT_DRIVER(mt8183_clk_topckgen) = { .id = UCLASS_CLK, .of_match = mt8183_topckgen_compat, .bind = mtk_common_clk_parent_bind, - .probe = mt8183_topckgen_probe, + .probe = mt8183_clk_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, .flags = DM_FLAG_PRE_RELOC, |