diff options
| author | Balaji Selvanathan <[email protected]> | 2025-12-03 16:37:31 +0530 |
|---|---|---|
| committer | Casey Connolly <[email protected]> | 2026-04-27 12:33:30 +0200 |
| commit | 6de333b5caf035c38d7af9fa7596aeffcc49db42 (patch) | |
| tree | 5a411ba604d429d3c6bb96fa4cf3f2be95c7214d | |
| parent | c808ab5fed990e2aa8e4ca6a855db49a225edd64 (diff) | |
drivers: usb: dwc3: Add delay after core soft reset
Add a 100 ms delay after clearing the core soft reset bit to ensure
the DWC3 controller has sufficient time to complete its reset
sequence before subsequent register accesses.
Without this delay, USB initialization can fail on some Qualcomm
platforms, particularly when using super-speed capable PHYs like
the QMP USB3-DP Combo PHY on SC7280/QCM6490.
Taken from Linux commit f88359e1588b ("usb: dwc3: core: Do core softreset when switch mode")
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
| -rw-r--r-- | drivers/usb/dwc3/core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 65c4d1a4e6f..0dee14c8b59 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -106,6 +106,8 @@ done: if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) mdelay(50); + mdelay(100); + return 0; } |