diff options
| author | Andre Przywara <[email protected]> | 2025-02-10 00:25:29 +0000 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-04-28 12:45:44 -0600 |
| commit | 1d26da5a6abaa9ef9cecce2df382d564458de6d8 (patch) | |
| tree | 2024e3214e6b769b2a7f9d7a0c791b7fde51dab4 /arch/arm/include | |
| parent | 5a9014a8ea3823c469f421df3d3ba667326f8a2c (diff) | |
sunxi: armv8: FEL: save and restore SP_IRQ
Thanks for Jernej's JTAG debugging effort, it turns out that the BROM
expects SP_IRQ to be saved and restored, when we want to enter back into
FEL after the SPL's AArch64 stint.
Save and restore SP_IRQ as part of the FEL state handling. The banked
MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was
introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8
cores used in the A10/A13s or older F1C100s SoCs would not support that,
but this code here is purely in the ARMv8/AArch64 code path, so it's
safe to use unconditionally.
Reported-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/boot0.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 9baedc2e9af..d79aea97a40 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -26,6 +26,8 @@ .word 0xe580e004 // str lr, [r0, #4] .word 0xe10fe000 // mrs lr, CPSR .word 0xe580e008 // str lr, [r0, #8] + .word 0xe101e300 // mrs lr, SP_irq + .word 0xe580e014 // str lr, [r0, #20] .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} .word 0xe580e00c // str lr, [r0, #12] .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} @@ -35,9 +37,9 @@ .word 0xe31e0001 // tst lr, #1 .word 0x0a000003 // beq cc <start32+0x48> .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} - .word 0xe580e014 // str lr, [r0, #20] - .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} .word 0xe580e018 // str lr, [r0, #24] + .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} + .word 0xe580e01c // str lr, [r0, #28] #endif .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE |