Merge branch 'next'

12 files changed, 293 insertions, 2 deletions

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 1af9778f8ce..25d0f205fde 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -79,6 +79,7 @@
 #define MXC_CPU_IMX95		0x1C1 /* dummy ID */
 
 #define MXC_CPU_IMX94		0x1C2 /* dummy ID */
+#define MXC_CPU_IMX952		0x1C3 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
diff --git a/arch/arm/include/asm/arch-rk3506/boot0.h b/arch/arm/include/asm/arch-rk3506/boot0.h
new file mode 100644
index 00000000000..8ae46f25a87
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3506/boot0.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3506/gpio.h b/arch/arm/include/asm/arch-rk3506/gpio.h
new file mode 100644
index 00000000000..5516e649b80
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3506/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 3c204501f70..95b08bfd046 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -215,6 +215,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
 int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
 			    u32 reg_offset, u32 reg_number);
 /*
+ * rk3506_reset_bind_lut() - Bind soft reset device as child of clock device
+ *			     using dedicated RK3506 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+/*
  * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
  *			     using dedicated RK3528 lookup table
  *
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3506.h b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h
new file mode 100644
index 00000000000..2f79e5eaf09
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <[email protected]>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3506_H
+#define _ASM_ARCH_CRU_RK3506_H
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+
+/* RK3506 pll id */
+enum rk3506_pll_id {
+	GPLL,
+	V0PLL,
+	V1PLL,
+	PLL_COUNT,
+};
+
+struct rk3506_clk_priv {
+	unsigned long gpll_hz;
+	unsigned long gpll_div_hz;
+	unsigned long gpll_div_100mhz;
+	unsigned long v0pll_hz;
+	unsigned long v0pll_div_hz;
+	unsigned long v1pll_hz;
+	unsigned long v1pll_div_hz;
+};
+
+struct pll_rate_table {
+	unsigned long rate;
+	unsigned int fbdiv;
+	unsigned int postdiv1;
+	unsigned int refdiv;
+	unsigned int postdiv2;
+	unsigned int dsmpd;
+	unsigned int frac;
+};
+
+#define RK3506_CRU_BASE			0xff9a0000
+#define RK3506_MODE_CON			0x0280
+#define RK3506_CLKSEL_CON(x)		(RK3506_CRU_BASE + 0x0300 + (x) * 0x4)
+#define RK3506_SOFTRST_CON0		0x0a00
+#define RK3506_GLB_SRST_FST		0x0c08
+#define RK3506_GLB_SRST_SND		0x0c0c
+#define RK3506_PLL_CON(x)		(0x10000 + (x) * 0x4)
+#define RK3506_SCRU_BASE		0xff9a8000
+#define RK3506_PMU_CRU_BASE		0xff9b0000
+#define RK3506_PMU_CLKSEL_CON(x)	(RK3506_PMU_CRU_BASE + 0x0300 + (x) * 0x4)
+
+enum {
+	/* CRU_CLKSEL_CON00 */
+	CLK_GPLL_DIV_MASK		= GENMASK(9, 6),
+	CLK_GPLL_DIV_100M_MASK		= GENMASK(13, 10),
+
+	/* CRU_CLKSEL_CON01 */
+	CLK_V0PLL_DIV_MASK		= GENMASK(3, 0),
+	CLK_V1PLL_DIV_MASK		= GENMASK(7, 4),
+
+	/* CRU_CLKSEL_CON15 */
+	CLK_CORE_SRC_DIV_MASK		= GENMASK(4, 0),
+	CLK_CORE_SRC_SEL_MASK		= GENMASK(6, 5),
+	CLK_CORE_SEL_GPLL		= 0,
+	CLK_CORE_SEL_V0PLL,
+	CLK_CORE_SEL_V1PLL,
+
+	ACLK_CORE_DIV_MASK		= GENMASK(12, 9),
+
+	/* CRU_CLKSEL_CON16 */
+	PCLK_CORE_DIV_MASK		= GENMASK(3, 0),
+
+	/* CRU_CLKSEL_CON21 */
+	ACLK_BUS_DIV_MASK		= GENMASK(4, 0),
+	ACLK_BUS_SEL_MASK		= GENMASK(6, 5),
+	ACLK_BUS_SEL_GPLL_DIV		= 0,
+	ACLK_BUS_SEL_V0PLL_DIV,
+	ACLK_BUS_SEL_V1PLL_DIV,
+
+	HCLK_BUS_DIV_MASK		= GENMASK(11, 7),
+	HCLK_BUS_SEL_MASK		= GENMASK(13, 12),
+
+	/* CRU_CLKSEL_CON22 */
+	PCLK_BUS_DIV_MASK		= GENMASK(4, 0),
+	PCLK_BUS_SEL_MASK		= GENMASK(6, 5),
+
+	/* CRU_CLKSEL_CON29 */
+	HCLK_LSPERI_DIV_MASK		= GENMASK(4, 0),
+	HCLK_LSPERI_SEL_MASK		= GENMASK(6, 5),
+
+	/* CRU_CLKSEL_CON32 */
+	CLK_I2C0_DIV_MASK		= GENMASK(3, 0),
+	CLK_I2C0_SEL_MASK		= GENMASK(5, 4),
+	CLK_I2C_SEL_GPLL		= 0,
+	CLK_I2C_SEL_V0PLL,
+	CLK_I2C_SEL_V1PLL,
+	CLK_I2C1_DIV_MASK		= GENMASK(9, 6),
+	CLK_I2C1_SEL_MASK		= GENMASK(11, 10),
+
+	/* CRU_CLKSEL_CON33 */
+	CLK_I2C2_DIV_MASK		= GENMASK(3, 0),
+	CLK_I2C2_SEL_MASK		= GENMASK(5, 4),
+	CLK_PWM1_DIV_MASK		= GENMASK(9, 6),
+	CLK_PWM1_SEL_MASK		= GENMASK(11, 10),
+	CLK_PWM1_SEL_GPLL_DIV		= 0,
+	CLK_PWM1_SEL_V0PLL_DIV,
+	CLK_PWM1_SEL_V1PLL_DIV,
+
+	/* CRU_CLKSEL_CON34 */
+	CLK_SPI0_DIV_MASK		= GENMASK(7, 4),
+	CLK_SPI0_SEL_MASK		= GENMASK(9, 8),
+	CLK_SPI_SEL_24M			= 0,
+	CLK_SPI_SEL_GPLL_DIV,
+	CLK_SPI_SEL_V0PLL_DIV,
+	CLK_SPI_SEL_V1PLL_DIV,
+	CLK_SPI1_DIV_MASK		= GENMASK(13, 10),
+	CLK_SPI1_SEL_MASK		= GENMASK(15, 14),
+
+	/* CRU_CLKSEL_CON49 */
+	ACLK_HSPERI_DIV_MASK		= GENMASK(4, 0),
+	ACLK_HSPERI_SEL_MASK		= GENMASK(6, 5),
+	ACLK_HSPERI_SEL_GPLL_DIV	= 0,
+	ACLK_HSPERI_SEL_V0PLL_DIV,
+	ACLK_HSPERI_SEL_V1PLL_DIV,
+
+	CCLK_SDMMC_DIV_MASK		= GENMASK(12, 7),
+	CCLK_SDMMC_SEL_MASK		= GENMASK(14, 13),
+	CCLK_SDMMC_SEL_24M		= 0,
+	CCLK_SDMMC_SEL_GPLL,
+	CCLK_SDMMC_SEL_V0PLL,
+	CCLK_SDMMC_SEL_V1PLL,
+
+	/* CRU_CLKSEL_CON50 */
+	SCLK_FSPI_DIV_MASK		= GENMASK(4, 0),
+	SCLK_FSPI_SEL_MASK		= GENMASK(6, 5),
+	SCLK_FSPI_SEL_24M		= 0,
+	SCLK_FSPI_SEL_GPLL,
+	SCLK_FSPI_SEL_V0PLL,
+	SCLK_FSPI_SEL_V1PLL,
+	CLK_MAC_DIV_MASK		= GENMASK(11, 7),
+
+	/* CRU_CLKSEL_CON54 */
+	CLK_SARADC_DIV_MASK		= GENMASK(3, 0),
+	CLK_SARADC_SEL_MASK		= GENMASK(5, 4),
+	CLK_SARADC_SEL_24M		= 0,
+	CLK_SARADC_SEL_400K,
+	CLK_SARADC_SEL_32K,
+
+	/* CRU_CLKSEL_CON60 */
+	DCLK_VOP_DIV_MASK		= GENMASK(7, 0),
+	DCLK_VOP_SEL_MASK		= GENMASK(10, 8),
+	DCLK_VOP_SEL_24M		= 0,
+	DCLK_VOP_SEL_GPLL,
+	DCLK_VOP_SEL_V0PLL,
+	DCLK_VOP_SEL_V1PLL,
+	DCLK_VOP_SEL_FRAC_VOIC1,
+	DCLK_VOP_SEL_FRAC_COMMON0,
+	DCLK_VOP_SEL_FRAC_COMMON1,
+	DCLK_VOP_SEL_FRAC_COMMON2,
+
+	/* CRU_CLKSEL_CON61 */
+	CLK_TSADC_DIV_MASK		= GENMASK(7, 0),
+	CLK_TSADC_TSEN_DIV_MASK		= GENMASK(10, 8),
+
+	/* PMUCRU_CLKSEL_CON00 */
+	CLK_PWM0_DIV_MASK		= GENMASK(9, 6),
+	CLK_MAC_OUT_DIV_MASK		= GENMASK(15, 10),
+
+	/* SCRU_CLKSEL_CON104 */
+	CLK_PKA_CRYPTO_DIV_MASK		= GENMASK(11, 7),
+	CLK_PKA_CRYPTO_SEL_MASK		= GENMASK(13, 12),
+	CLK_PKA_CRYPTO_SEL_GPLL		= 0,
+	CLK_PKA_CRYPTO_SEL_V0PLL,
+	CLK_PKA_CRYPTO_SEL_V1PLL,
+};
+
+#endif /* _ASM_ARCH_CRU_RK3506_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
index a5fc6ad3656..01f2214cd15 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
@@ -205,6 +205,8 @@ struct dram_para {
 	uint32_t mr12;
 	uint32_t mr13;
 	uint32_t mr14;
+	uint32_t mr22;
+	uint32_t tpr0;
 	uint32_t tpr1;
 	uint32_t tpr2;
 	uint32_t tpr3;
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index a399c94213b..8c38c71c93a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -68,6 +68,7 @@ struct timerus {
 
 /* These are the available SKUs (product types) for Tegra */
 enum {
+	SKU_ID_T20_A04		= 0x4, /* Sony Tablet P value */
 	SKU_ID_AP20		= 0x7,
 	SKU_ID_T20		= 0x8,
 	SKU_ID_AP20H		= 0xf,
diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h
index 439e43c2d01..762f00e6900 100644
--- a/arch/arm/include/asm/bootm.h
+++ b/arch/arm/include/asm/bootm.h
@@ -8,8 +8,6 @@
 #ifndef ARM_BOOTM_H
 #define ARM_BOOTM_H
 
-extern void udc_disconnect(void);
-
 #ifdef CONFIG_SUPPORT_PASSING_ATAGS
 # define BOOTM_ENABLE_TAGS		1
 #else
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index 4e1afc42bd8..04e7f20a2a6 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -49,6 +49,7 @@
 #define ELE_ATTEST_REQ (0xDB)
 #define ELE_RELEASE_PATCH_REQ (0xDC)
 #define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+#define ELE_SET_GMID_REQ (0xE4)
 #define ELE_WRITE_SHADOW_REQ (0xF2)
 #define ELE_READ_SHADOW_REQ (0xF3)
 
@@ -162,6 +163,7 @@ int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
 int ele_start_rng(void);
 int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response);
 int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response);
+int ele_set_gmid(u32 *response);
 int ele_volt_change_start_req(void);
 int ele_volt_change_finish_req(void);
 #endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 46da7a1eff5..ab573413128 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -99,6 +99,7 @@ struct bd_info;
 
 #define is_imx94() (is_cpu_type(MXC_CPU_IMX94))
 #define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+#define is_imx952() (is_cpu_type(MXC_CPU_IMX952))
 
 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
 #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
@@ -254,6 +255,43 @@ struct scmi_rom_passover_get_out {
 	u32 passover[(sizeof(rom_passover_t) + 8) / 4];
 };
 
+/**
+ * struct scmi_ddr_info_out - Get DDR memory region info
+ * @status: Error code
+ * @attributes: Region attributes:
+ *              Bit[31] ECC enable.
+ *              Set to 1 if ECC enabled.
+ *              Set to 0 if ECC disabled or not configured.
+ *              Bits[30:18] Reserved, must be zero.
+ *              Bits[17:16] Number of DDR memory regions.
+ *              Bits[15:11] Reserved, must be zero.
+ *              Bits[10:8] Width.
+ *              Bus width is 16 << this field.
+ *              So 0=16, 1=32, 2=64, etc.
+ *              Bits[7:5] Reserved, must be zero.
+ *              Bits[4:0] DDR type.
+ *              Set to 0 if LPDDR5.
+ *              Set to 1 if LPDDR5X.
+ *              Set to 2 if LPDDR4.
+ *              Set to 3 if LPDDR4X
+ * @mts: DDR speed in megatransfers per second
+ * @startlow: The lower 32 bits of the physical start address of the region
+ * @starthigh: The upper 32 bits of the physical start address of the region
+ * @endlow: The lower 32 bits of the physical end address of the region. This
+ *          excludes any DDR used to store ECC data
+ * @endhigh: The upper 32 bits of the physical end address of the region. This
+ *           excludes any DDR used to store ECC data
+ */
+struct scmi_ddr_info_out {
+	s32 status;
+	u32 attributes;
+	u32 mts;
+	u32 startlow;
+	u32 starthigh;
+	u32 endlow;
+	u32 endhigh;
+};
+
 #endif
 
 /* For i.MX ULP */
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index ee79a19c05c..dd462ea6ad8 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -30,6 +30,7 @@ enum {
 	BOOT_DEVICE_XIP,
 	BOOT_DEVICE_BOOTROM,
 	BOOT_DEVICE_SMH,
+	BOOT_DEVICE_UFS,
 	BOOT_DEVICE_NONE
 };
 #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 4c1b81483c9..9e3ad57073d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -171,6 +171,12 @@ static inline unsigned int current_el(void)
 	return 3 & (el >> 2);
 }
 
+static inline unsigned int current_pl(void)
+{
+	/* Aarch32 compatibility */
+	return current_el();
+};
+
 static inline unsigned long get_sctlr(void)
 {
 	unsigned int el;
@@ -466,6 +472,39 @@ static inline int is_hyp(void)
 #endif
 }
 
+static inline int is_usr(void)
+{
+	return (get_cpsr() & 0x1f) == 0x10;
+}
+
+static inline unsigned int current_pl(void)
+{
+	/*
+	 * ARM DDI 0406C.d ID040418 , page 140 chapter A3.6.1 "Processor
+	 * privilege levels, execution privilege, and access privilege",
+	 * clarifies the PLx levels as follows (abbreviated):
+	 * The characteristics of the privilege levels are:
+	 * - PL0 - The privilege level of application software, that
+	 *         executes in User mode.
+	 * - PL1 - Software execution in all modes other than User mode
+	 *         and Hyp mode is at PL1.
+	 * - PL2 - Software executing in Hyp mode executes at PL2.
+	 */
+	if (is_hyp())	/* HYP */
+		return 2;
+
+	if (is_usr())	/* USR */
+		return 0;
+
+	return 1;	/* The rest */
+}
+
+static inline unsigned int current_el(void)
+{
+	/* Aarch64 compatibility */
+	return current_pl();
+};
+
 static inline unsigned int get_cr(void)
 {
 	unsigned int val;