riscv: lib: Split out support for T-Head cache management operations

Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.

This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.

Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>

3 files changed, 1 insertions, 46 deletions

diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
index 7225b1210c5..57f724ae043 100644
--- a/arch/riscv/cpu/cv1800b/Kconfig
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -6,6 +6,7 @@ config SOPHGO_CV1800B
 	bool
 	select ARCH_EARLY_INIT_R
 	select SYS_CACHE_SHIFT_6
+	select SYS_CACHE_THEAD_CMO
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index 95beb34b51a..da12e0f64e1 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,4 +4,3 @@
 
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
deleted file mode 100644
index b8051e29e02..00000000000
--- a/arch/riscv/cpu/cv1800b/cache.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024, Kongyang Liu <[email protected]>
- */
-
-#include <cpu_func.h>
-
-/*
- * dcache.ipa rs1 (invalidate)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- *   0000001    01010      rs1       000      00000  0001011
- *
- * dcache.cpa rs1 (clean)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- *   0000001    01001      rs1       000      00000  0001011
- *
- * dcache.cipa rs1 (clean then invalidate)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- *   0000001    01011      rs1       000      00000  0001011
- *
- * sync.s
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- *   0000000    11001     00000      000      00000  0001011
- */
-#define DCACHE_IPA_A0	".long 0x02a5000b"
-#define DCACHE_CPA_A0	".long 0x0295000b"
-#define DCACHE_CIPA_A0	".long 0x02b5000b"
-
-#define SYNC_S		".long 0x0190000b"
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
-	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
-	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
-		__asm__ __volatile__(DCACHE_IPA_A0);
-	__asm__ __volatile__(SYNC_S);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
-	register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
-	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
-		__asm__ __volatile__(DCACHE_CPA_A0);
-	__asm__ __volatile__(SYNC_S);
-}