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Age	Commit message (Expand)	Author
2026-03-17	eeprom: starfive: Simplify get_ddr_size_from_eeprom()	Hal Feng
2026-03-13	riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist	Heinrich Schuchardt
2026-03-13	sifive: switch to OF_UPSTREAM	Andreas Schwab
2026-02-17	treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage	Peng Fan
2026-01-20	riscv: Update linker scripts to ensure appended device tree is aligned	Tom Rini
2025-12-08	riscv: mpfs: move SoC level options to the CPU Kconfig	Conor Dooley
2025-12-08	riscv: create a custom CPU implementation for PolarFire SoC	Conor Dooley
2025-12-08	riscv: cpu: Beautify the warning message	Leo Yu-Chi Liang
2025-10-16	Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S"	Yao Zi
2025-09-19	riscv: Add a Zalrsc-only alternative for synchronization in start.S	Yao Zi
2025-09-19	dts: th1520: Switch to upstream devicetree	Yao Zi
2025-08-14	riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef	Michal Simek
2025-07-17	riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB	Yao Zi
2025-07-03	riscv: cpu: th1520: Enable pinctrl by default	Yao Zi
2025-07-03	riscv: cpu: th1520: Add a routine to bring up secondary cores	Yao Zi
2025-07-03	riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init	Yao Zi
2025-06-09	riscv: cpu: th1520: Support cache enabling/disabling in M mode only	Yao Zi
2025-06-09	riscv: cpu: th1520: Build spl.c for SPL only	Yao Zi
2025-05-21	riscv: cpu: th1520: Select clock driver	Yao Zi
2025-05-21	riscv: cpu: th1520: Initialize IOPMPs in SPL	Yao Zi
2025-05-21	riscv: cpu: Add TH1520 CPU support	Yao Zi
2025-05-21	riscv: lib: Split out support for T-Head cache management operations	Yao Zi
2025-05-21	riscv: Access gd with inline assembly when building with LTO or Clang	Yao Zi
2025-04-25	riscv: Provide __image_copy_{start_end} symbols in linkerscript	Yao Zi
2025-03-25	Add reset config options for k1	Huan Zhou
2025-03-13	spl: Use CONFIG_VAL() to obtain the SPL stack	Simon Glass
2025-03-13	spl: Add an SPL_HAVE_INIT_STACK option	Simon Glass
2025-02-03	riscv: cpu: jh7110: fallback to generic cleanup_before_linux()	Yao Zi
2025-02-03	riscv: cpu: generic: fallback to generic cleanup_before_linux()	Yao Zi
2025-02-03	riscv: add a generic implementation for cleanup_before_linux()	Yao Zi
2025-02-03	riscv: spacemit: k1: probe dram size during boot phase.	Huan Zhou
2025-01-16	riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC	Junhui Liu
2025-01-16	riscv: Fallback to riscv,isa	Mayuresh Chitale
2025-01-16	riscv: Enhance extension probing	Mayuresh Chitale
2024-12-18	riscv: spacemit: bananapi_f3: initial support added	Kongyang Liu
2024-12-18	riscv: cpu: jh7110: Sort the list of imply statements	Hal Feng
2024-12-18	dts: starfive: Switch to using upstream DT	Hal Feng
2024-10-11	arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD	Simon Glass
2024-09-11	riscv: Add AST2700 SoC initial platform support	Chia-Wei Wang
2024-09-11	riscv: u-boot-spl.lds: Remove _image_binary_end alignment	Chia-Wei Wang
2024-05-30	andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND	Leo Yu-Chi Liang
2024-05-30	riscv: remove cache enablement in start.S	Leo Yu-Chi Liang
2024-05-14	andes: Unify naming policy for Andes related source	Leo Yu-Chi Liang
2024-05-02	board: starfive: Rename spl_soc_init() to spl_dram_init()	Lukas Funke
2024-05-02	board: sifive: Rename spl_soc_init() to spl_dram_init()	Lukas Funke
2024-05-01	riscv: andesv5: Set default cache line size to 64-bytes	Yu Chien Peter Lin
2024-04-09	riscv: support extension probing using riscv, isa-extensions	Conor Dooley
2024-04-09	riscv: don't read riscv, isa in the riscv cpu's get_desc()	Conor Dooley
2024-04-09	riscv: cache: Implement dcache for cv1800b	Kongyang Liu
2024-04-09	riscv: cpu: cv1800b: Add support for cv1800b SoC	Kongyang Liu