diff options
| author | Sean Anderson <[email protected]> | 2019-12-25 00:27:44 -0500 |
|---|---|---|
| committer | Andes <[email protected]> | 2020-02-10 14:51:08 +0800 |
| commit | fd1f6e9a0bc7ba536c19478b2fd8619ecda6ec3b (patch) | |
| tree | cf45bbb908850abc89bf9b23cba29ed561e3f547 /arch/riscv/cpu | |
| parent | d9f1cee286c8d039e290f624baeeb133b8d47a21 (diff) | |
riscv: Add option to print registers on exception
When debugging, it can be helpful to see more information about an
unhandled exception. This patch adds an option to view the registers at
the time of the trap, similar to the linux output on a kernel panic.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Diffstat (limited to 'arch/riscv/cpu')
| -rw-r--r-- | arch/riscv/cpu/mtrap.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 407ecfa9c07..e40c7bd3f4f 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -64,7 +64,8 @@ trap_entry: SREG x31, 31 * REGBYTES(sp) csrr a0, MODE_PREFIX(cause) csrr a1, MODE_PREFIX(epc) - mv a2, sp + csrr a2, MODE_PREFIX(tval) + mv a3, sp jal handle_trap csrw MODE_PREFIX(epc), a0 |