Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SKIP_LOWLEVEL_INIT
   CONFIG_SKIP_LOWLEVEL_INIT_ONLY

In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.

Signed-off-by: Tom Rini <[email protected]>

30 files changed, 121 insertions, 59 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 25f4a15b19f..507ebf75f05 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -351,6 +351,63 @@ config SYS_DISABLE_DCACHE_OPS
 	 Note that, its up to the individual architectures to implement
 	 this functionality.
 
+config SKIP_LOWLEVEL_INIT
+	bool "Skip the calls to certain low level initialization functions"
+	depends on ARM || NDS32 || MIPS || RISCV
+	help
+	  If enabled, then certain low level initializations (like setting up
+	  the memory controller) are omitted and/or U-Boot does not relocate
+	  itself into RAM.
+	  Normally this variable MUST NOT be defined. The only exception is
+	  when U-Boot is loaded (to RAM) by some other boot loader or by a
+	  debugger which performs these initializations itself.
+
+config SPL_SKIP_LOWLEVEL_INIT
+	bool "Skip the calls to certain low level initialization functions"
+	depends on SPL && (ARM || NDS32 || MIPS || RISCV)
+	help
+	  If enabled, then certain low level initializations (like setting up
+	  the memory controller) are omitted and/or U-Boot does not relocate
+	  itself into RAM.
+	  Normally this variable MUST NOT be defined. The only exception is
+	  when U-Boot is loaded (to RAM) by some other boot loader or by a
+	  debugger which performs these initializations itself.
+
+config TPL_SKIP_LOWLEVEL_INIT
+	bool "Skip the calls to certain low level initialization functions"
+	depends on SPL && ARM
+	help
+	  If enabled, then certain low level initializations (like setting up
+	  the memory controller) are omitted and/or U-Boot does not relocate
+	  itself into RAM.
+	  Normally this variable MUST NOT be defined. The only exception is
+	  when U-Boot is loaded (to RAM) by some other boot loader or by a
+	  debugger which performs these initializations itself.
+
+config SKIP_LOWLEVEL_INIT_ONLY
+	bool "Skip the call to lowlevel_init during early boot ONLY"
+	depends on ARM
+	help
+	  This allows just the call to lowlevel_init() to be skipped. The
+	  normal CP15 init (such as enabling the instruction cache) is still
+	  performed.
+
+config SPL_SKIP_LOWLEVEL_INIT_ONLY
+	bool "Skip the call to lowlevel_init during early boot ONLY"
+	depends on SPL && ARM
+	help
+	  This allows just the call to lowlevel_init() to be skipped. The
+	  normal CP15 init (such as enabling the instruction cache) is still
+	  performed.
+
+config TPL_SKIP_LOWLEVEL_INIT_ONLY
+	bool "Skip the call to lowlevel_init during early boot ONLY"
+	depends on TPL && ARM
+	help
+	  This allows just the call to lowlevel_init() to be skipped. The
+	  normal CP15 init (such as enabling the instruction cache) is still
+	  performed.
+
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index da7278e59fa..4bc27f63736 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -39,7 +39,7 @@ reset:
 	msr	cpsr,r0
 
 	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl  cpu_init_crit
 #endif
 
@@ -62,7 +62,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -81,7 +81,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	/*
 	 * Jump to board specific initialization... The Mask ROM will have already initialized
 	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -91,4 +91,4 @@ cpu_init_crit:
 	mov	lr, ip		/* restore link */
 #endif
 	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index ecb4e44fd8d..9ad1f031429 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -37,8 +37,8 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	bl	cpu_init_crit
 #endif
 
@@ -62,8 +62,8 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 cpu_init_crit:
 
 	mov	ip, lr
@@ -76,4 +76,4 @@ cpu_init_crit:
 	mov	lr, ip
 
 	mov	pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index e2b5f2bff4a..02cbda9d224 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -53,7 +53,7 @@ copyex:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl	cpu_init_crit
 #endif
 
@@ -78,7 +78,7 @@ c_runtime_cpu_setup:
  */
 
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -97,7 +97,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
@@ -109,4 +109,4 @@ cpu_init_crit:
 	mov	lr, ip
 #endif
 	mov	pc, lr
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index ff592ba8101..0afcc47aad7 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -46,7 +46,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl	cpu_init_crit
 #endif
 
@@ -69,7 +69,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 cpu_init_crit:
 	/*
 	 * flush D cache before disabling it
@@ -100,7 +100,7 @@ flush_dcache:
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
@@ -109,4 +109,4 @@ flush_dcache:
 	mov	lr, r4		/* restore link */
 #endif
 	mov	pc, lr		/* back to my caller */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 0ec340b1a6e..2d5186774a7 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -45,7 +45,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl	cpu_init_crit
 #endif
 
@@ -70,7 +70,7 @@ c_runtime_cpu_setup:
  */
 
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -89,7 +89,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0e83e394d52..bfbd85ae64e 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
 obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
 endif
 
-ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
+ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index dcb4195d7b4..87329d26e10 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -80,11 +80,11 @@ switch_to_hypervisor_ret:
 #endif
 
 	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 #ifdef CONFIG_CPU_V7A
 	bl	cpu_init_cp15
 #endif
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	bl	cpu_init_crit
 #endif
 #endif
@@ -320,8 +320,8 @@ skip_errata_801819:
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9ca61b3f59e..b10b56d2d30 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1012A
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
 	select GICV2
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE
@@ -62,6 +63,7 @@ config ARCH_LS1043A
 	select FSL_LSCH2
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -96,6 +98,7 @@ config ARCH_LS1046A
 	select FSL_LSCH2
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -134,6 +137,7 @@ config ARCH_LS1088A
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -181,6 +185,7 @@ config ARCH_LS2080A
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -296,6 +301,7 @@ config ARCH_LX2160A
 
 config FSL_LSCH2
 	bool
+	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 575abac09c2..896e05f1fda 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -45,7 +45,7 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl  cpu_init_crit
 #endif
 
@@ -92,7 +92,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -111,7 +111,7 @@ cpu_init_crit:
 	mcr	p15, 0, r0, c1, c0, 0
 
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
 
 /*
  * Enable MMU to use DCache as DRAM.
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 8eb005309e0..2f84f20575c 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -39,7 +39,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	bl	cpu_init_crit
 #endif
 
@@ -95,7 +95,7 @@ cpu_init_crit:
 	ldr	r1, cpuspeed
 	str	r1, [r0, #PPCR]
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h
index 493be643116..e423c9d071f 100644
--- a/arch/arm/include/asm/arch-am33xx/chilisom.h
+++ b/arch/arm/include/asm/arch-am33xx/chilisom.h
@@ -6,7 +6,7 @@
 #ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
 #define __ARCH_ARM_MACH_CHILISOM_SOM_H__
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 void chilisom_enable_pin_mux(void);
 void chilisom_spl_board_init(void);
 #endif
diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index de99c616ac8..5e3cce03b7e 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
@@ -10,7 +10,7 @@
 
 #include <config.h>
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_mc.h>
@@ -148,4 +148,4 @@ SMRDATA1:
 	.word CONFIG_SYS_SDRAM_VAL
 SMRDATA1E:
 	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index fda25ba66a3..6f9a30bb5f4 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -224,7 +224,7 @@ const struct rproc_att hostmap[] = {
 };
 #endif
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 /* enable all periherial can be accessed in nosec mode */
 static void init_csu(void)
 {
diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c
index 6dfed365d29..7c02e199a38 100644
--- a/arch/arm/mach-imx/syscounter.c
+++ b/arch/arm/mach-imx/syscounter.c
@@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
 	return usec;
 }
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 int timer_init(void)
 {
 	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index 80d0a85ec1c..6ecd394a533 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -27,10 +27,6 @@
 
 #define CONFIG_SYS_L2_PL310
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
-#endif
-
 /*
  * By default the generated mvebu kwbimage.cfg is used
  * If for some board, different configuration file need to be used,
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 08639653b79..dfb63df9a19 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -120,6 +120,7 @@ config AM33XX
 	select SPECIFY_CONSOLE_INDEX
 	imply NAND_OMAP_ELM
 	imply NAND_OMAP_GPMC
+	imply SKIP_LOWLEVEL_INIT
 	imply SPL_NAND_AM33XX_BCH
 	imply SPL_NAND_SUPPORT
 	imply SYS_I2C_OMAP24XX
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 61c76d045f3..4e4f98ea903 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -13,7 +13,7 @@ endif
 obj-$(CONFIG_TI816X)	+= clock_ti816x.o
 obj-y	+= sys_info.o
 obj-y	+= ddr.o
-ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),)
+ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
 obj-y	+= emif4.o
 endif
 obj-$(CONFIG_TI816X)	+= ti816x_emif4.o
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index d390f2e1f3e..c44667668e9 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	sdram_init();
 #endif
 
@@ -351,7 +351,7 @@ int arch_misc_init(void)
 
 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
@@ -599,7 +599,7 @@ void board_init_f(ulong dummy)
 int arch_cpu_init_dm(void)
 {
 	hw_data_init();
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	early_system_init();
 #endif
 	return 0;
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
index 15b6b35ae7c..459bac13e05 100644
--- a/arch/arm/mach-omap2/am33xx/chilisom.c
+++ b/arch/arm/mach-omap2/am33xx/chilisom.c
@@ -22,7 +22,7 @@
 #include <power/tps65217.h>
 #include <spl.h>
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
@@ -182,4 +182,4 @@ void sdram_init(void)
 		   &ddr3_chilisom_emif_reg_data, 0);
 }
 
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 363af528450..8b70251457e 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -76,8 +76,8 @@ void early_system_init(void)
 	hw_data_init();
 }
 
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 
 /******************************************************************************
  * Routine: secure_unlock
diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index 4fa89418a11..ab7cdcf3d42 100644
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -170,8 +170,8 @@ pll_div_val5:
 go_to_speed_end:
 #endif
 
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
-	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
+	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
 ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash ip register */
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 606153e407c..a8b87f6d710 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -11,7 +11,7 @@ obj-y	= cpu.o
 obj-y	+= dram.o
 obj-y	+= timer.o
 
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b164afb5290..d617c4bc89c 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -100,6 +100,7 @@ config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
 	select CPU_V7A
 	select OF_BOARD_SETUP
+	select SKIP_LOWLEVEL_INIT_ONLY
 	select SUPPORT_SPL
 	select SPL
 	select SUPPORT_TPL
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 311266400df..6998a500453 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON
 	select CPU_V7A
 	select SPL
 	select SPL_BOARD_INIT if SPL
+	select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
 	select SUPPORT_SPL
 	select TEGRA_CLKRST
 	select TEGRA_COMMON
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 335aafa6a8d..47251a5b92a 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -233,7 +233,7 @@ wr_done:
 # endif
 #endif
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 	/* Initialize any external memory */
 	PTR_LA	t9, lowlevel_init
@@ -254,7 +254,7 @@ wr_done:
 	 nop
 #endif
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 	/* Initialize any external memory */
 	PTR_LA	t9, lowlevel_init
diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
index e4a6c035808..83cd8fa9b6b 100644
--- a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
+++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
@@ -28,7 +28,7 @@
 	.set noreorder
 
 LEAF(mips_sram_init)
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	/* Setup CPU PLL */
 	li	t0, DELAY_USEC(1000000)
 	li	t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
@@ -116,7 +116,7 @@ _cpu_pll_done:
 	sub	a1, CONFIG_SYS_DCACHE_LINE_SIZE
 	bnez	a1, 3b
 	 nop
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
 
 	jr	ra
 	 nop
diff --git a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
index 507d79e77b8..25ec185d69d 100644
--- a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
@@ -94,7 +94,7 @@ mem_init:
 	move	  $lp, $r11
 	ret
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 .globl	lowlevel_init
 lowlevel_init:
 	move	$r10, $lp
@@ -144,4 +144,4 @@ enable_fpu:
 	ret
 #endif
 
-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
index 73f1f52056a..ce5fefda765 100644
--- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -164,7 +164,7 @@ sdram_b0_cr:
 	ret
 
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 
 .globl	lowlevel_init
 lowlevel_init:
@@ -314,4 +314,4 @@ show_led:
     li      $r8, (CONFIG_DEBUG_LED)
     swi     $r7, [$r8]
     ret
-#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
+#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 3395721552a..f02508f04f6 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -174,7 +174,7 @@ set_ivb:
 
 	jal mem_init
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 	jal	lowlevel_init
 /*
  *  gp = ~VMA          for burn mode