Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/28674

- riscv: Implement private GCC library
- mpfs: Add MPFS CPU Implementation
- andes: Stop disabling device tree relocation and some minor fixes
- sifive: Stop disabling device tree relocation
- starfive: Cleanup size types and typos

12 files changed, 293 insertions, 5 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 3133f892f94..4af0da2485f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -159,6 +159,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_PRIVATE_LIBGCC if 64BIT
 	select HAVE_SETJMP
 	select HAVE_INITJMP
 	select SUPPORT_ACPI
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 265b5320777..79867656b15 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -126,6 +126,7 @@ source "arch/riscv/cpu/cv1800b/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/ast2700/Kconfig"
+source "arch/riscv/cpu/mpfs/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 source "arch/riscv/cpu/jh7110/Kconfig"
 source "arch/riscv/cpu/k1/Kconfig"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d5123e4b7d9..bbadd0c9a46 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -463,7 +463,7 @@ static void riscv_parse_isa_string(const char *isa)
 		switch (*ext) {
 		case 'x':
 		case 'X':
-			log_warning("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
+			log_warning("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.\n");
 			/*
 			 * To skip an extension, we find its end.
 			 * As multi-letter extensions must be split from other multi-letter
diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig
new file mode 100644
index 00000000000..bcf1ede818b
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config MICROCHIP_MPFS
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CLINT if RISCV_MMODE
+	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	imply REGMAP
+	imply SYSCON
+	imply CLK_CCF
+	imply CLK_MPFS
+	imply SYS_NS16550
+	imply MACB
+	imply MII
+	imply CMD_I2C
+	imply DM_I2C
+	imply SYS_I2C_MICROCHIP
+	imply MMC
+	imply MMC_WRITE
+	imply MMC_SDHCI
+	imply MMC_SDHCI_CADENCE
+	imply MMC_SDHCI_ADMA
+	imply MMC_HS200_SUPPORT
+	imply SPI
+	imply DM_SPI
+	imply MICROCHIP_QSPI
diff --git a/arch/riscv/cpu/mpfs/Makefile b/arch/riscv/cpu/mpfs/Makefile
new file mode 100644
index 00000000000..e2f62ff7711
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/mpfs/dram.c b/arch/riscv/cpu/mpfs/dram.c
new file mode 100644
index 00000000000..4398d3e36c8
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <[email protected]>
+ */
+
+#include <asm/global_data.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_TOP_OF_CACHED (SZ_2G + SZ_1G)
+#define MPFS_HSS_RESERVATION (SZ_4M)
+
+int dram_init(void) {
+    return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void) {
+    return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size) {
+    /*
+     * Ensure that if we run from 32-bit memory that all memory used by
+     * U-Boot is cached addresses, but also account for the reservation at
+     * the top of 32 bit cached DDR used by the HSS.
+     */
+    if (gd->ram_top >= MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION)
+        return MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION - 1;
+    /*
+     * If we don't find a 32 bit region just return the top of memory.
+     * If the address is a 32-bit region, but fits beneath the HSS'
+     * reservation, ram_top is adequate also.
+     */
+    return gd->ram_top;
+}
\ No newline at end of file
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465e..cf2d429c7c0 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -17,8 +17,8 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
-		stdout-path = "uart0:38400n8";
+		bootargs = "console=ttyS0,115200n8 debug loglevel=7";
+		stdout-path = "uart0:115200n8";
 	};
 
 	cpus {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 8c7db29b4f2..1928221fa3c 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -17,8 +17,8 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
-		stdout-path = "uart0:38400n8";
+		bootargs = "console=ttyS0,115200n8 debug loglevel=7";
+		stdout-path = "uart0:115200n8";
 	};
 
 	cpus {
diff --git a/arch/riscv/include/asm/arch-mpfs/clk.h b/arch/riscv/include/asm/arch-mpfs/clk.h
new file mode 100644
index 00000000000..fbb1399f3c8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-mpfs/clk.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_RISCV_ARCH_MPFS_CLK_H
+#define __ASM_RISCV_ARCH_MPFS_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index f1f50918eff..a527b3e9ae3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -6,6 +6,8 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <[email protected]>
 
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += clz.o ctz.o
+
 obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o
 obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o
 obj-$(CONFIG_CMD_GO) += boot.o
diff --git a/arch/riscv/lib/clz.c b/arch/riscv/lib/clz.c
new file mode 100644
index 00000000000..7b173d3c858
--- /dev/null
+++ b/arch/riscv/lib/clz.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count leading bits
+ *
+ * Copyright 2025, Heinrich Schuchardt <[email protected]>
+ */
+
+#include <linux/types.h>
+
+/**
+ * __clzti2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzti2(long long x)
+{
+	int ret = 64;
+
+	if (!x)
+		return 64;
+
+	if (x & 0xFFFFFFFF00000000LL) {
+		ret -= 32;
+		x >>= 32;
+	}
+	if (x & 0xFFFF0000LL) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00LL) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0LL) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xCLL) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2LL) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzsi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzsi2(int x)
+{
+	int ret = 32;
+
+	if (!x)
+		return 32;
+
+	if (x & 0xFFFF0000) {
+		ret -= 16;
+		x >>= 16;
+	}
+	if (x & 0xFF00) {
+		ret -= 8;
+		x >>= 8;
+	}
+	if (x & 0xF0) {
+		ret -= 4;
+		x >>= 4;
+	}
+	if (x & 0xC) {
+		ret -= 2;
+		x >>= 2;
+	}
+	if (x & 0x2) {
+		ret -= 1;
+		x >>= 1;
+	}
+	if (x)
+		ret -= 1;
+
+	return ret;
+}
+
+/**
+ * __clzdi2() - count number of leading zero bits
+ *
+ * @x:		number to check
+ * Return:	number of leading zero bits
+ */
+int __clzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __clzti2(x);
+#else
+	return __clzsi2(x);
+#endif
+}
diff --git a/arch/riscv/lib/ctz.c b/arch/riscv/lib/ctz.c
new file mode 100644
index 00000000000..6c875e39f0e
--- /dev/null
+++ b/arch/riscv/lib/ctz.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * libgcc replacement - count trailing bits
+ */
+
+#include <linux/types.h>
+
+/**
+ * __ctzti2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzti2(long long x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 64;
+
+	if (!(x & 0xFFFFFFFFLL)) {
+		ret += 32;
+		x >>= 32;
+	}
+	if (!(x & 0xFFFFLL)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFFLL)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xFLL)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3LL)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1ll))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzsi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzsi2(int x)
+{
+	int ret = 0;
+
+	if (!x)
+		return 32;
+
+	if (!(x & 0xFFFF)) {
+		ret += 16;
+		x >>= 16;
+	}
+	if (!(x & 0xFF)) {
+		ret += 8;
+		x >>= 8;
+	}
+	if (!(x & 0xF)) {
+		ret += 4;
+		x >>= 4;
+	}
+	if (!(x & 0x3)) {
+		ret += 2;
+		x >>= 2;
+	}
+	if (!(x & 0x1))
+		ret += 1;
+
+	return ret;
+}
+
+/**
+ * __ctzdi2() - count number of trailing zero bits
+ *
+ * @x:		number to check
+ * Return:	number of trailing zero bits
+ */
+int __ctzdi2(long x)
+{
+#if BITS_PER_LONG == 64
+	return __ctzti2(x);
+#else
+	return __ctzsi2(x);
+#endif
+}