Merge branch '2024-03-19-assorted-updates' into next

- TI J7200 updates, GIC-600 support, 2 more tests, fix parsing
  ccsidr_el1 register in some cases, prepare for allowing remoteproc to
  use fs_loader and make the binary_size_check rule not require 'bc'.

9 files changed, 51 insertions, 4 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d978c06d5a..a0842e19330 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -124,6 +124,15 @@ config GIC_V3_ITS
 	  ARM GICV3 has limitation, once the LPI table is enabled, LPI
 	  configuration table can not be re-programmed, unless GICV3 reset.
 
+config GICV3_SUPPORT_GIC600
+	bool "ARM GICV3 GIC600 SUPPORT"
+	help
+	  ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
+	  implements a power control register in the Redistributor frame.This
+	  register must be programmed to mark the frame as powered on, before
+	  accessing other registers in the frame. Rest of initialization sequence
+	  remains the same.
+
 config STATIC_RELA
 	bool
 	default y if ARM64
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 3fe935cf283..c9e46859b4f 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -20,6 +20,7 @@
  *
  * x0: cache level
  * x1: 0 clean & invalidate, 1 invalidate only
+ * x16: FEAT_CCIDX
  * x2~x9: clobbered
  */
 .pushsection .text.__asm_dcache_level, "ax"
@@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level)
 	isb				/* sync change of cssidr_el1 */
 	mrs	x6, ccsidr_el1		/* read the new cssidr_el1 */
 	ubfx	x2, x6,  #0,  #3	/* x2 <- log2(cache line size)-4 */
+	cbz	x16, 3f			/* check for FEAT_CCIDX */
+	ubfx	x3, x6,  #3, #21	/* x3 <- number of cache ways - 1 */
+	ubfx	x4, x6, #32, #24	/* x4 <- number of cache sets - 1 */
+	b	4f
+3:
 	ubfx	x3, x6,  #3, #10	/* x3 <- number of cache ways - 1 */
 	ubfx	x4, x6, #13, #15	/* x4 <- number of cache sets - 1 */
+4:
 	add	x2, x2, #4		/* x2 <- log2(cache line size) */
 	clz	w5, w3			/* bit position of #ways */
 	/* x12 <- cache level << 1 */
@@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all)
 	ubfx	x11, x10, #24, #3	/* x11 <- loc */
 	cbz	x11, finished		/* if loc is 0, exit */
 	mov	x15, lr
+	mrs	x16, s3_0_c0_c7_2	/* read value of id_aa64mmfr2_el1*/
+	ubfx	x16, x16, #20, #4	/* save FEAT_CCIDX identifier in x16 */
 	mov	x0, #0			/* start flush at cache level 0 */
 	/* x0  <- cache level */
 	/* x10 <- clidr_el1 */
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 60ca6d21abb..c9fee0ea99b 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -195,6 +195,10 @@
 
 &ospi0 {
 	bootph-all;
+
+	flash@0 {
+		bootph-all;
+	};
 };
 
 &serdes_ln_ctrl {
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 018faaa13b6..fb7e2e50239 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -52,7 +52,7 @@
 };
 
 &mcu_timer0 {
-	clock-frequency = <25000000>;
+	clock-frequency = <250000000>;
 	bootph-pre-ram;
 };
 
@@ -83,3 +83,16 @@
 &wkup_vtm0 {
 	bootph-pre-ram;
 };
+
+&ospi0 {
+    reg = <0x0 0x47040000 0x0 0x100>,
+          <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&mcu_ringacc {
+    ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+    ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80cdf70..fb64ba076d7 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -57,6 +57,7 @@
 #define GICR_TYPER		0x0008
 #define GICR_STATUSR		0x0010
 #define GICR_WAKER		0x0014
+#define GICR_PWRR              0x0024
 #define GICR_SETLPIR		0x0040
 #define GICR_CLRLPIR		0x0048
 #define GICR_SEIR		0x0068
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index 86cd882fc75..7fa48648d9d 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu)
 	add	x9, x9, #(2 << 16)
 	b	1b
 
+2:
+#if defined(CONFIG_GICV3_SUPPORT_GIC600)
+        mov     w10, #0x0               /* Power on redistributor */
+        str     w10, [x9, GICR_PWRR]
+5:      ldr     w10, [x9, GICR_PWRR]    /* Wait until the power on state is reflected */
+        tbnz    w10, #1, 5b             /* If RDPD == 0 then powered on */
+#endif
+
 	/* x9: ReDistributor Base Address of Current CPU */
-2:	mov	w10, #~0x2
+	mov	w10, #~0x2
 	ldr	w11, [x9, GICR_WAKER]
 	and	w11, w11, w10		/* Clear ProcessorSleep */
 	str	w11, [x9, GICR_WAKER]
diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c
index 7309573a3fa..c02f8d33099 100644
--- a/arch/arm/mach-k3/r5/common.c
+++ b/arch/arm/mach-k3/r5/common.c
@@ -70,7 +70,7 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
 	char *name = NULL;
 	int size = 0;
 
-	if (!IS_ENABLED(CONFIG_FS_LOADER))
+	if (!CONFIG_IS_ENABLED(FS_LOADER))
 		return 0;
 
 	*loadaddr = 0;
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 57917da25cf..aa0ab13d5fb 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -190,7 +190,7 @@ int load_firmware(char *name_fw, u32 *loadaddr)
 	struct udevice *fsdev;
 	int size = 0;
 
-	if (!IS_ENABLED(CONFIG_FS_LOADER))
+	if (!CONFIG_IS_ENABLED(FS_LOADER))
 		return 0;
 
 	if (!*loadaddr)
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 1b5339993f8..54fb93aeb53 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -35,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU
 config GICV3
 	def_bool y
 
+config GICV3_SUPPORT_GIC600
+	def_bool y
+
 config SYS_MALLOC_LEN
 	default 0x2000000