diff options
| author | Tom Rini <[email protected]> | 2026-06-14 15:35:00 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-06-14 15:35:00 -0600 |
| commit | 1e80ee41441c612f05787a93bbef4e6e422e29d1 (patch) | |
| tree | 390e9cd03dff4770795d5a99d309a7ba4c93a146 /board | |
| parent | 5ca1a73c7d3064582498a8aa96c29e714402a6d3 (diff) | |
| parent | cc5d760ace890b57d78b23aafb47ba220e63ae4f (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Two fixes for R-Car Gen5 RSIP, one to surely build u-boot-elf.shdr and
one to make u-boot-elf.shdr compatible with tooling.
Two fixes for R-Car Gen4, which could hang in SPL without them.
Diffstat (limited to 'board')
| -rw-r--r-- | board/renesas/common/gen4-spl.c | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index e4c1190eac7..5a0b0ebe115 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -18,6 +18,12 @@ #include <mapmem.h> #include <spl.h> +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + #define CNTCR_EN BIT(0) #ifdef CONFIG_SPL_BUILD @@ -47,6 +53,18 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); + if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = spl_early_init(); if (ret) { @@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -#define APMU_BASE 0xe6170000U -#define CL0GRP3_BIT BIT(3) -#define CL1GRP3_BIT BIT(7) -#define RTGRP3_BIT BIT(19) -#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) - -int mach_cpu_init(void) -{ - /* Unlock CPG access */ - writel(0x5A5AFFFF, CPGWPR); - writel(0xA5A50000, CPGWPCR); - init_generic_timer(); - - /* Define for Work Around of APMU */ - writel(0x00ff00ff, APMU_BASE + 0x10); - writel(0x00ff00ff, APMU_BASE + 0x14); - writel(0x00ff00ff, APMU_BASE + 0x18); - writel(0x00ff00ff, APMU_BASE + 0x1c); - clrbits_le32(APMU_BASE + 0x68, BIT(29)); - - return 0; -} - void reset_cpu(void) { } |