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| author | Jernej Skrabec <[email protected]> | 2023-04-10 10:21:10 +0200 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2023-04-12 00:17:21 +0100 |
| commit | 7230bebfe3b9a7ce97ac3b3aef2d26ded08b6224 (patch) | |
| tree | c15beaeae63fa80f07512a6d979486a13719851d /doc/develop/python_cq.rst | |
| parent | f0500692972ad6981d0a669e02707044dc224483 (diff) | |
sunxi: Fix write to H616 DRAM CR register
Vendor DRAM code actually writes to whole CR register and not just sets
bit 31 in mctl_ctrl_init().
Just to be safe, do that here too.
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions