Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

- A new driver in the misc to register setting from device tree. This
  also provides user a clean interface and all register settings are
  centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
  new files are created for board, dts, configs and makefile to create
  the base for Agilex5.

Build-tested on SoC64 boards, boot tested on some of them.

8 files changed, 95 insertions, 15 deletions

diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index 1d641a78cf8..bc6d5246694 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -92,9 +92,9 @@ Assuming the uSD card is `/dev/mmcblk0`:
 To boot from a micro SD card on a HSFS device simply copy the following
 artifacts to the FAT partition:
 
-* tiboot3.bin from R5 build as tiboot3.bin
-* tispl.bin_unsigned from Cortex-A build as tispl.bin
-* u-boot.img_unsigned from Cortex-A build as u-boot.img
+* tiboot3.bin from R5 build
+* tispl.bin from Cortex-A build
+* u-boot.img from Cortex-A build
 
 Boot
 ----
diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst
index ede880d248c..5ad4e59c838 100644
--- a/doc/develop/commands.rst
+++ b/doc/develop/commands.rst
@@ -88,7 +88,7 @@ The command function pointer has to be of type
 
 .. code-block:: c
 
-    int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]);
+    int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
 
 cmdtp
     Table entry describing the command (see above).
diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
new file mode 100644
index 00000000000..cf40fdd2da8
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
@@ -0,0 +1,80 @@
+* Firewall and privilege register settings in device tree
+
+Required properties:
+--------------------
+
+- compatible: should contain "intel,socfpga-dtreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+			 followed by 32-bit value settings and
+			 the masking bits, only masking bit
+			 set to 1 allows modification.
+
+The device tree node which describes secure and privilege register access
+configuration in compile time.
+
+Most of these registers are expected to work except for the case which some
+registers configuration are required for granting access to some other
+registers, for example CCU registers have to be properly configured before
+allowing register configuration access to fpga2sdram firewall as shown in
+below example.
+
+Some registers depend on runtime data for proper configuration are expected
+to be part of driver that generating these data for example configuration for
+soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from
+memory device tree node.
+
+Please refer details of tested examples below for both fpga2sdram and QoS
+configuration with default reset value and the comments.
+
+Example:
+--------
+
+Configuration for multiple dtreg node support in device tree:
+
+	socfpga_dtreg0: socfpga-dtreg0 {
+		compatible = "intel,socfpga-dtreg";
+						#address-cells = <1>;
+                        #size-cells = <1>;
+		        bootph-all;
+
+                        coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+							reg = <0xf7100200 0x00000014>;
+                                intel,offset-settings =
+										/*
+										 * Disable ocram security at CCU for
+										 * non secure access
+										 */
+                                        <0x0000004 0x8000ffff 0xe007ffff>,
+                                        <0x0000008 0x8000ffff 0xe007ffff>,
+                                        <0x000000c 0x8000ffff 0xe007ffff>,
+                                        <0x0000010 0x8000ffff 0xe007ffff>;
+                                bootph-all;
+                        };
+					};
+
+	socfpga_dtreg1: socfpga-dtreg1 {
+		compatible = "intel,socfpga-dtreg";
+						#address-cells = <1>;
+                        #size-cells = <1>;
+						bootph-all;
+
+                        soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+                                reg = <0xf8020000 0x0000001c>;
+                                intel,offset-settings =
+                                        /* Disable MPFE firewall for SMMU */
+                                        <0x00000000 0x00010101 0x00010101>,
+                                        /*
+										 * Disable MPFE firewall for HMC
+										 * adapter
+										 */
+                                        <0x00000004 0x00000001 0x00010101>;
+								bootph-all;
+                        };
+					};
+
+To call the nodes use:
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev);
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev);
+
diff --git a/doc/sphinx/cdomain.py b/doc/sphinx/cdomain.py
index 014a5229e57..491a7ed5f47 100644
--- a/doc/sphinx/cdomain.py
+++ b/doc/sphinx/cdomain.py
@@ -93,7 +93,7 @@ def markup_ctype_refs(match):
 #
 RE_expr = re.compile(r':c:(expr|texpr):`([^\`]+)`')
 def markup_c_expr(match):
-    return '\ ``' + match.group(2) + '``\ '
+    return '\\ ``' + match.group(2) + '``\\ '
 
 #
 # Parse Sphinx 3.x C markups, replacing them by backward-compatible ones
diff --git a/doc/sphinx/kernel_abi.py b/doc/sphinx/kernel_abi.py
index f3da859c987..32c50e496b5 100644
--- a/doc/sphinx/kernel_abi.py
+++ b/doc/sphinx/kernel_abi.py
@@ -147,7 +147,7 @@ class KernelCmd(Directive):
                 code_block += "\n    " + l
             lines = code_block + "\n\n"
 
-        line_regex = re.compile("^#define LINENO (\S+)\#([0-9]+)$")
+        line_regex = re.compile(r"^#define LINENO (\S+)\#([0-9]+)$")
         ln = 0
         n = 0
         f = fname
diff --git a/doc/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py
index 01a55429c57..bc8bb9e5125 100644
--- a/doc/sphinx/kerneldoc.py
+++ b/doc/sphinx/kerneldoc.py
@@ -130,7 +130,7 @@ class KernelDocDirective(Directive):
             result = ViewList()
 
             lineoffset = 0;
-            line_regex = re.compile("^#define LINENO ([0-9]+)$")
+            line_regex = re.compile(r"^#define LINENO ([0-9]+)$")
             for line in lines:
                 match = line_regex.search(line)
                 if match:
diff --git a/doc/sphinx/maintainers_include.py b/doc/sphinx/maintainers_include.py
index dc8fed48d3c..13557d3d3c2 100755
--- a/doc/sphinx/maintainers_include.py
+++ b/doc/sphinx/maintainers_include.py
@@ -78,8 +78,8 @@ class MaintainersInclude(Include):
             # Drop needless input whitespace.
             line = line.rstrip()
 
-            # Linkify all non-wildcard refs to ReST files in Documentation/.
-            pat = '(Documentation/([^\s\?\*]*)\.rst)'
+            # Linkify all non-wildcard refs to ReST files in doc/.
+            pat = r'(doc/([^\s\?\*]*)\.rst)'
             m = re.search(pat, line)
             if m:
                 # maintainers.rst is in a subdirectory, so include "../".
@@ -92,11 +92,11 @@ class MaintainersInclude(Include):
                 output = "| %s" % (line.replace("\\", "\\\\"))
                 # Look for and record field letter to field name mappings:
                 #   R: Designated *reviewer*: FullName <address@domain>
-                m = re.search("\s(\S):\s", line)
+                m = re.search(r"\s(\S):\s", line)
                 if m:
                     field_letter = m.group(1)
                 if field_letter and not field_letter in fields:
-                    m = re.search("\*([^\*]+)\*", line)
+                    m = re.search(r"\*([^\*]+)\*", line)
                     if m:
                         fields[field_letter] = m.group(1)
             elif subsystems:
@@ -114,7 +114,7 @@ class MaintainersInclude(Include):
                     field_content = ""
 
                     # Collapse whitespace in subsystem name.
-                    heading = re.sub("\s+", " ", line)
+                    heading = re.sub(r"\s+", " ", line)
                     output = output + "%s\n%s" % (heading, "~" * len(heading))
                     field_prev = ""
                 else:
@@ -177,11 +177,11 @@ class MaintainersInclude(Include):
         if not self.state.document.settings.file_insertion_enabled:
             raise self.warning('"%s" directive disabled.' % self.name)
 
-        # Walk up source path directories to find Documentation/../
+        # Walk up source path directories to find doc/../
         path = self.state_machine.document.attributes['source']
         path = os.path.realpath(path)
         tail = path
-        while tail != "Documentation" and tail != "":
+        while tail != "doc" and tail != "":
             (path, tail) = os.path.split(path)
 
         # Append "MAINTAINERS"
diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst
index a859e32798c..a7e21693a67 100644
--- a/doc/usage/cmd/env.rst
+++ b/doc/usage/cmd/env.rst
@@ -350,7 +350,7 @@ edit
 exists
     CONFIG_CMD_ENV_EXISTS
 
-flsgs
+flags
     CONFIG_CMD_ENV_FLAGS
 
 erase