Merge branch 'next'

4 files changed, 55 insertions, 184 deletions

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index ef1663f3450..65d9bf533cb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -73,6 +73,7 @@ config RTC_DS1307
 
 config RTC_DS1337
 	bool "Enable DS1337 driver"
+	depends on DM_RTC
 	help
 	  Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible
 	  Real Time Clock devices.
@@ -81,15 +82,9 @@ config RTC_DS1337_NOOSC
 	bool "Enable support for no oscillator output in DS1337 driver"
 	depends on RTC_DS1337
 
-config RTC_DS1338
-	bool "Enable DS1338 driver"
-	help
-	  Support for Dallas Semiconductor (now Maxim) DS1338 and compatible
-	  Real Time Clock devices.
-
 config RTC_DS1374
 	bool "Enable DS1374 driver"
-	depends on !DM_RTC
+	depends on !DM_RTC && !DM_I2C
 	help
 	  Support for Dallas Semiconductor (now Maxim) DS1374 and compatible
 	  Real Time Clock devices.
@@ -171,12 +166,14 @@ config RTC_PCF85063
 
 config RTC_PCF8563
 	bool "Philips PCF8563"
+	depends on DM_RTC
 	help
 	  If you say yes here you get support for the Philips PCF8563 RTC
 	  and compatible chips.
 
 config RTC_PT7C4338
 	bool "Enable Pericom Technology PT7C4338 RTC driver"
+	depends on DM_RTC
 
 config RTC_RV3028
 	bool "Enable RV3028 driver"
@@ -240,13 +237,14 @@ config RTC_MV
 
 config RTC_S35392A
 	bool "Enable S35392A driver"
+	depends on DM_RTC
 	select BITREVERSE
 	help
 	  Enable s35392a driver which provides rtc get and set function.
 
 config RTC_MC13XXX
 	bool "Enable MC13XXX RTC driver"
-	depends on !DM_RTC
+	depends on !DM_RTC && POWER_LEGACY
 
 config RTC_MC146818
 	bool "Enable MC146818 driver"
@@ -258,6 +256,7 @@ config RTC_MC146818
 
 config MCFRTC
 	bool "Use common CF RTC driver"
+	depends on DM_RTC
 	depends on M68K
 
 config SYS_MCFRTC_BASE
@@ -267,9 +266,11 @@ config SYS_MCFRTC_BASE
 config RTC_MXS
 	bool "Enable i.MXS RTC driver"
 	depends on ARCH_MX23 || ARCH_MX28
+	depends on !DM_RTC
 
 config RTC_M41T62
 	bool "Enable M41T62 driver"
+	depends on DM_RTC
 	help
 	  Enable driver for ST's M41T62 compatible RTC devices (like RV-4162).
 	  It is a serial (I2C) real-time clock (RTC) with alarm.
@@ -310,6 +311,7 @@ config RTC_ABX80X
 config RTC_DAVINCI
 	bool "Enable TI OMAP RTC driver"
 	depends on ARCH_DAVINCI || ARCH_OMAP2PLUS
+	depends on DM_RTC
 	help
 	  Say "yes" here to support the on chip real time clock
 	  present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx.
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 9df373d5148..782f5a3bc3d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o
 obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o
 obj-$(CONFIG_RTC_DAVINCI) += davinci.o
 obj-$(CONFIG_RTC_DS1307) += ds1307.o
-obj-$(CONFIG_RTC_DS1338) += ds1307.o
 obj-$(CONFIG_RTC_DS1337) += ds1337.o
 obj-$(CONFIG_RTC_DS1374) += ds1374.o
 obj-$(CONFIG_RTC_DS1672) += ds1672.o
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 77544298d8a..e9db6220c55 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -21,7 +21,6 @@
 /*
  * RTC register addresses
  */
-#if defined CONFIG_RTC_DS1337
 #define RTC_SEC_REG_ADDR	0x0
 #define RTC_MIN_REG_ADDR	0x1
 #define RTC_HR_REG_ADDR		0x2
@@ -32,18 +31,6 @@
 #define RTC_CTL_REG_ADDR	0x0e
 #define RTC_STAT_REG_ADDR	0x0f
 #define RTC_TC_REG_ADDR		0x10
-#elif defined CONFIG_RTC_DS1388
-#define RTC_SEC_REG_ADDR	0x1
-#define RTC_MIN_REG_ADDR	0x2
-#define RTC_HR_REG_ADDR		0x3
-#define RTC_DAY_REG_ADDR	0x4
-#define RTC_DATE_REG_ADDR	0x5
-#define RTC_MON_REG_ADDR	0x6
-#define RTC_YR_REG_ADDR		0x7
-#define RTC_CTL_REG_ADDR	0x0c
-#define RTC_STAT_REG_ADDR	0x0b
-#define RTC_TC_REG_ADDR		0x0a
-#endif
 
 /*
  * RTC control register bits
@@ -62,132 +49,6 @@
 #define RTC_STAT_BIT_A2F	0x2	/* Alarm 2 flag			*/
 #define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag		*/
 
-#if !CONFIG_IS_ENABLED(DM_RTC)
-static uchar rtc_read (uchar reg);
-static void rtc_write (uchar reg, uchar val);
-
-/*
- * Get the current time from the RTC
- */
-int rtc_get (struct rtc_time *tmp)
-{
-	int rel = 0;
-	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
-
-	control = rtc_read (RTC_CTL_REG_ADDR);
-	status = rtc_read (RTC_STAT_REG_ADDR);
-	sec = rtc_read (RTC_SEC_REG_ADDR);
-	min = rtc_read (RTC_MIN_REG_ADDR);
-	hour = rtc_read (RTC_HR_REG_ADDR);
-	wday = rtc_read (RTC_DAY_REG_ADDR);
-	mday = rtc_read (RTC_DATE_REG_ADDR);
-	mon_cent = rtc_read (RTC_MON_REG_ADDR);
-	year = rtc_read (RTC_YR_REG_ADDR);
-
-	/* No century bit, assume year 2000 */
-#ifdef CONFIG_RTC_DS1388
-	mon_cent |= 0x80;
-#endif
-
-	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
-		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
-		year, mon_cent, mday, wday, hour, min, sec, control, status);
-
-	if (status & RTC_STAT_BIT_OSF) {
-		printf ("### Warning: RTC oscillator has stopped\n");
-		/* clear the OSF flag */
-		rtc_write (RTC_STAT_REG_ADDR,
-			   rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
-		rel = -1;
-	}
-
-	tmp->tm_sec  = bcd2bin (sec & 0x7F);
-	tmp->tm_min  = bcd2bin (min & 0x7F);
-	tmp->tm_hour = bcd2bin (hour & 0x3F);
-	tmp->tm_mday = bcd2bin (mday & 0x3F);
-	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
-	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
-	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
-	tmp->tm_yday = 0;
-	tmp->tm_isdst= 0;
-
-	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
-	return rel;
-}
-
-/*
- * Set the RTC
- */
-int rtc_set (struct rtc_time *tmp)
-{
-	uchar century;
-
-	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
-	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
-
-	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
-	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
-
-	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
-	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
-	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
-	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
-	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
-
-	return 0;
-}
-
-/*
- * Reset the RTC.  We also enable the oscillator output on the
- * SQW/INTB* pin and program it for 32,768 Hz output. Note that
- * according to the datasheet, turning on the square wave output
- * increases the current drain on the backup battery from about
- * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
- * off the OSC output.
- */
-
-#ifdef CONFIG_RTC_DS1337_NOOSC
- #define RTC_DS1337_RESET_VAL \
-	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
-#else
- #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
-#endif
-void rtc_reset (void)
-{
-#ifdef CONFIG_RTC_DS1337
-	rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
-#elif defined CONFIG_RTC_DS1388
-	rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
-#endif
-#ifdef CONFIG_RTC_DS1339_TCR_VAL
-	rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
-#endif
-#ifdef CONFIG_RTC_DS1388_TCR_VAL
-	rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
-#endif
-}
-
-/*
- * Helper functions
- */
-
-static
-uchar rtc_read (uchar reg)
-{
-	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
-}
-
-static void rtc_write (uchar reg, uchar val)
-{
-	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
-}
-#else
 static uchar rtc_read(struct udevice *dev, uchar reg)
 {
 	return dm_i2c_reg_read(dev, reg);
@@ -213,11 +74,6 @@ static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp)
 	mon_cent = rtc_read(dev, RTC_MON_REG_ADDR);
 	year = rtc_read(dev, RTC_YR_REG_ADDR);
 
-	/* No century bit, assume year 2000 */
-#ifdef CONFIG_RTC_DS1388
-	mon_cent |= 0x80;
-#endif
-
 	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n",
 	      year, mon_cent, mday, wday);
 	debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
@@ -278,17 +134,8 @@ static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
 #endif
 static int ds1337_rtc_reset(struct udevice *dev)
 {
-#ifdef CONFIG_RTC_DS1337
 	rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
-#elif defined CONFIG_RTC_DS1388
-	rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */
-#endif
-#ifdef CONFIG_RTC_DS1339_TCR_VAL
-	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
-#endif
-#ifdef CONFIG_RTC_DS1388_TCR_VAL
-	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
-#endif
+
 	return 0;
 }
 
@@ -311,4 +158,3 @@ U_BOOT_DRIVER(rtc_ds1337) = {
 	.of_match = ds1337_rtc_ids,
 	.ops    = &ds1337_rtc_ops,
 };
-#endif
diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c
index 15122a04838..4fee75bf9cf 100644
--- a/drivers/rtc/zynqmp_rtc.c
+++ b/drivers/rtc/zynqmp_rtc.c
@@ -5,26 +5,30 @@
 
 #define LOG_CATEGORY UCLASS_RTC
 
+#include <clk.h>
 #include <dm.h>
 #include <rtc.h>
 #include <asm/io.h>
+#include <dm/device_compat.h>
 
 /* RTC Registers */
 #define RTC_SET_TM_WR		0x00
 #define RTC_SET_TM_RD		0x04
 #define RTC_CALIB_WR		0x08
+#define RTC_CALIB_RD		0x0C
 #define RTC_CUR_TM		0x10
 #define RTC_INT_STS		0x20
 #define RTC_CTRL		0x40
 
 #define RTC_INT_SEC		BIT(0)
 #define RTC_BATT_EN		BIT(31)
-#define RTC_CALIB_DEF		0x198233
+#define RTC_CALIB_DEF		0x7FFF
+#define RTC_FREQ_MAX		0x10000
 #define RTC_CALIB_MASK		0x1FFFFF
 
 struct zynqmp_rtc_priv {
 	fdt_addr_t	base;
-	unsigned int	calibval;
+	unsigned long	calibval;
 };
 
 static int zynqmp_rtc_get(struct udevice *dev, struct rtc_time *tm)
@@ -70,13 +74,6 @@ static int zynqmp_rtc_set(struct udevice *dev, const struct rtc_time *tm)
 		 */
 		new_time = rtc_mktime(tm) + 1;
 
-	/*
-	 * Writing into calibration register will clear the Tick Counter and
-	 * force the next second to be signaled exactly in 1 second period
-	 */
-	priv->calibval &= RTC_CALIB_MASK;
-	writel(priv->calibval, (priv->base + RTC_CALIB_WR));
-
 	writel(new_time, priv->base + RTC_SET_TM_WR);
 
 	/*
@@ -107,15 +104,6 @@ static int zynqmp_rtc_init(struct udevice *dev)
 	rtc_ctrl |= RTC_BATT_EN;
 	writel(rtc_ctrl, priv->base + RTC_CTRL);
 
-	/*
-	 * Based on crystal freq of 33.330 KHz
-	 * set the seconds counter and enable, set fractions counter
-	 * to default value suggested as per design spec
-	 * to correct RTC delay in frequency over period of time.
-	 */
-	priv->calibval &= RTC_CALIB_MASK;
-	writel(priv->calibval, (priv->base + RTC_CALIB_WR));
-
 	return 0;
 }
 
@@ -128,8 +116,44 @@ static int zynqmp_rtc_probe(struct udevice *dev)
 	if (priv->base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->calibval = dev_read_u32_default(dev, "calibration",
-					      RTC_CALIB_DEF);
+	ret = readl(priv->base + RTC_CALIB_RD);
+	if (!ret) {
+		struct clk rtc_clk;
+		unsigned long clk_rate;
+
+		/* Get the RTC clock rate */
+		ret = clk_get_by_name_optional(dev, "rtc", &rtc_clk);
+		if (!ret) {
+			clk_rate = clk_get_rate(&rtc_clk);
+			/* Use clock frequency if valid, fallback to calibration value */
+			if (clk_rate > 0 && clk_rate <= RTC_FREQ_MAX) {
+				/* Valid clock frequency */
+				priv->calibval = clk_rate - 1;
+			} else if (clk_rate == 0) {
+				priv->calibval = dev_read_u32_default(dev, "calibration",
+								      RTC_CALIB_DEF);
+			} else {
+				dev_err(dev, "Invalid clock frequency 0x%lx\n",
+					clk_rate);
+				return -EINVAL;
+			}
+		} else {
+			/* Clock framework unavailable, use DT calibration */
+			priv->calibval = dev_read_u32_default(dev, "calibration",
+							      RTC_CALIB_DEF);
+		}
+
+		/* Validate final calibration value */
+		if (priv->calibval > RTC_FREQ_MAX) {
+			dev_err(dev, "Invalid calibration 0x%lx\n",
+				priv->calibval);
+			return -EINVAL;
+		}
+
+		writel(priv->calibval, (priv->base + RTC_CALIB_WR));
+	} else {
+		priv->calibval = ret & RTC_CALIB_MASK;
+	}
 
 	ret = zynqmp_rtc_init(dev);