Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.

DDR and memory handling

  * Add DRAM size checking support for Arria10.
  * Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
  * Assign unit address to memory node for improved memory
    representation and consistency.

Agilex / Agilex5 updates

  * Restore multi-DTB support for NAND boot and fix NAND clock handling.
  * Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
  * Fix DT property naming conventions for Agilex5.
  * Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
    to avoid unintended clock control.

New board support

  * Add support for CoreCourse Cyclone V boards:
     * AC501
     * AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.

Fixes and cleanup

  * Fix GEN5 handoff script path.
  * Remove incorrect CONFIG_SPL_LDSCRIPT settings.
  * Replace legacy TARGET namespace and perform related cleanup across
    SoCFPGA code.
  * General Kconfig, build and SoCFPGA maintenance updates.

Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.

[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <[email protected]>

17 files changed, 84 insertions, 43 deletions

diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 858f828e537..693446b3d89 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -3,9 +3,9 @@
 # Copyright (C) 2018-2021 Marek Vasut <[email protected]>
 #
 
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
-obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += clk-agilex.o
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index fdbf834bb2f..e5be43b6317 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -657,6 +657,7 @@ static int bitmask_from_clk_id(struct clk *clk)
 		plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
 		break;
 	case AGILEX_L4_MP_CLK:
+	case AGILEX_NAND_X_CLK:
 		plat->pllgrp = CLKMGR_MAINPLL_EN;
 		plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
 		break;
@@ -728,6 +729,8 @@ static int bitmask_from_clk_id(struct clk *clk)
 		plat->pllgrp = CLKMGR_PERPLL_EN;
 		plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
 		break;
+	case AGILEX_L4_SYS_FREE_CLK:
+		return -EOPNOTSUPP;
 	default:
 		return -ENXIO;
 	}
@@ -742,6 +745,9 @@ static int socfpga_clk_enable(struct clk *clk)
 	int ret;
 
 	ret = bitmask_from_clk_id(clk);
+	if (ret == -EOPNOTSUPP)
+		return 0;
+
 	if (ret)
 		return ret;
 
@@ -757,6 +763,9 @@ static int socfpga_clk_disable(struct clk *clk)
 	int ret;
 
 	ret = bitmask_from_clk_id(clk);
+	if (ret == -EOPNOTSUPP)
+		return 0;
+
 	if (ret)
 		return ret;
 
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 4660d20deff..615e0421abf 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
 config SPL_ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver in SPL"
 	depends on SPL
-	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
-	select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
-	select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
+	depends on ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 || ARCH_SOCFPGA_SOC64
+	select RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64
+	select SPL_RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 7ed43965be5..8259ab04a7e 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -7,11 +7,11 @@
 # Copyright (C) 2014-2025 Altera Corporation <www.altera.com>
 
 ifdef CONFIG_$(PHASE_)ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
-obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o
-obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o
+obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o
+obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o
+obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o
 endif
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
index 2a2f86a650e..3156cb9d4b6 100644
--- a/drivers/ddr/altera/iossm_mailbox.c
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -86,7 +86,7 @@
 #define INTF_DDR_TYPE_MASK		GENMASK(2, 0)
 
 /* offset info of MEM_TOTAL_CAPACITY_INTF */
-#define INTF_CAPACITY_GBITS_MASK	GENMASK(7, 0)
+#define INTF_CAPACITY_GBITS_MASK	GENMASK(31, 0)
 
 /* offset info of ECC_ENABLE_INTF */
 #define INTF_ECC_ENABLE_TYPE_MASK	GENMASK(1, 0)
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index d3305a6c82d..c281f711fdf 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -8,6 +8,7 @@
 #include <fdtdec.h>
 #include <init.h>
 #include <log.h>
+#include <hang.h>
 #include <malloc.h>
 #include <wait_bit.h>
 #include <watchdog.h>
@@ -667,6 +668,22 @@ static int of_sdram_firewall_setup(const void *blob)
 	return 0;
 }
 
+static void sdram_size_check(void)
+{
+	phys_size_t ram_check = 0;
+
+	debug("DDR: Running SDRAM size sanity check\n");
+
+	ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start,
+				 gd->bd->bi_dram[0].size);
+	if (ram_check != gd->bd->bi_dram[0].size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+
+	debug("DDR: SDRAM size check passed!\n");
+}
+
 int ddr_calibration_sequence(void)
 {
 	schedule();
@@ -702,11 +719,26 @@ int ddr_calibration_sequence(void)
 	/* setup the dram info within bd */
 	dram_init_banksize();
 
+	if (gd->ram_size != gd->bd->bi_dram[0].size) {
+		printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n",
+		       gd->bd->bi_dram[0].size >> 20);
+		printf(" mismatch with hardware (%ld MiB).\n",
+		       gd->ram_size >> 20);
+	}
+
+	if (gd->bd->bi_dram[0].size > gd->ram_size) {
+		printf("DDR: Error: DRAM size from device tree is greater\n");
+		printf(" than hardware size.\n");
+		hang();
+	}
+
 	if (of_sdram_firewall_setup(gd->fdt_blob))
 		puts("FW: Error Configuring Firewall\n");
 
 	if (sdram_is_ecc_enabled())
 		sdram_init_ecc_bits(gd->ram_size);
 
+	sdram_size_check();
+
 	return 0;
 }
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 2d0093c591c..8ee7049b164 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -32,7 +32,7 @@
 #define SINGLE_RANK_CLAMSHELL	0xc3c3
 #define DUAL_RANK_CLAMSHELL	0xa5a5
 
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
 	return readl(plat->iomhc + reg);
@@ -106,7 +106,7 @@ int emif_reset(struct altera_sdram_plat *plat)
 }
 #endif
 
-#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+#if !(IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))
 int poll_hmc_clock_status(void)
 {
 	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
@@ -347,7 +347,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)
 	}
 }
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 static void sdram_set_firewall_f2sdram(struct bd_info *bd)
 {
 	u32 i, lower, upper;
@@ -397,22 +397,22 @@ void sdram_set_firewall(struct bd_info *bd)
 {
 	sdram_set_firewall_non_f2sdram(bd);
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 	sdram_set_firewall_f2sdram(bd);
 #endif
 }
 
 static int altera_sdram_of_to_plat(struct udevice *dev)
 {
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 	struct altera_sdram_plat *plat = dev_get_plat(dev);
 	fdt_addr_t addr;
 #endif
 
 	/* These regs info are part of DDR handoff in bitstream */
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 	return 0;
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 	addr = dev_read_addr_index(dev, 0);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 6fe0653922c..e8090f91002 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -15,13 +15,13 @@ struct altera_sdram_priv {
 	struct reset_ctl_bulk resets;
 };
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 struct altera_sdram_plat {
 	fdt_addr_t mpfe_base_addr;
 	bool dualport;
 	bool dualemif;
 };
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 enum memory_type {
 	DDR_MEMORY = 0,
 	HBM_MEMORY
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index e2593057fac..1658c73bca4 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -46,7 +46,7 @@ config FPGA_CYCLON2
 
 config FPGA_INTEL_SDM_MAILBOX
 	bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
-	depends on TARGET_SOCFPGA_SOC64
+	depends on ARCH_SOCFPGA_SOC64
 	select FPGA_ALTERA
 	help
 	  Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index f22d3b3d86e..ccfed94717e 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -21,6 +21,6 @@ obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
+obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += socfpga_arria10.o
 endif
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 4a9aa74357e..822183c5785 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,8 +12,8 @@
 /*
  *  Altera FPGA support
  */
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
 #include <asm/arch/misc.h>
 #endif
 #include <errno.h>
@@ -48,8 +48,8 @@ static const struct altera_fpga {
 #endif
 };
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
 int fpga_is_partial_data(int devnum, size_t img_len)
 {
 	/*
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 6219284df3e..c8da6ead0ea 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -58,8 +58,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
 	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
 			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
-	if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
-	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) {
+	if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
+	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
 		/* Disable SDMMC clock. */
 		clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
 			     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
@@ -95,8 +95,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
 		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 #endif
 
-	if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
-	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) {
+	if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
+	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
 		/* Enable SDMMC clock */
 		setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
 			     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 306175873fa..2999e6b1710 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -217,7 +217,7 @@ config NAND_DENALI
 	bool
 	select DEVRES
 	select SYS_NAND_SELF_INIT
-	select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64
+	select SYS_NAND_ONFI_DETECTION if ARCH_SOCFPGA_SOC64
 	imply CMD_NAND
 
 config NAND_DENALI_DT
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index fce8004e134..d3ef050d1a1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -194,7 +194,7 @@ config DWC_ETH_XGMAC_SOCFPGA
 	select SYSCON
 	select DWC_ETH_XGMAC
 	depends on ARCH_SOCFPGA
-	default y if TARGET_SOCFPGA_AGILEX5
+	default y if ARCH_SOCFPGA_AGILEX5
 	help
 	  The Synopsys Designware Ethernet XGMAC IP block with specific
 	  configuration used in Intel SoC FPGA chip.
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 935f282d6c5..2f63a8e54e5 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -20,7 +20,7 @@ config APPLE_PMGR_POWER_DOMAIN
 
 config AGILEX5_PMGR_POWER_DOMAIN
 	bool "Enable the Agilex5 PMGR power domain driver"
-	depends on SPL_POWER_DOMAIN && TARGET_SOCFPGA_SOC64
+	depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64
 	help
 	  Enable support for power gating peripherals' SRAM specified in
 	  the handoff data values obtained from the bitstream to reduce
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index e57729f0ef9..36a205f9fca 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev)
 	if (socfpga_reset_keep_enabled()) {
 		puts("Deasserting all peripheral resets\n");
 		writel(0, data->modrst_base + 4);
-		if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10))
+		if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10))
 			writel(0, data->modrst_base + 8);
 	}
 
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 120e7510f15..16ef434a8d9 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -196,14 +196,14 @@ config SYSRESET_SBI
 
 config SYSRESET_SOCFPGA
 	bool "Enable support for Intel SOCFPGA family"
-	depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
+	depends on ARCH_SOCFPGA && (ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10)
 	help
 	  This enables the system reset driver support for Intel SOCFPGA SoCs
 	  (Cyclone 5, Arria 5 and Arria 10).
 
 config SYSRESET_SOCFPGA_SOC64
 	bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
-	depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64
+	depends on ARCH_SOCFPGA && ARCH_SOCFPGA_SOC64
 	help
 	  This enables the system reset driver support for Intel SOCFPGA
 	  SoC64 SoCs.