Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05-rc2

- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
  and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates

6 files changed, 66 insertions, 18 deletions

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 4ef8662af56..d0d6c898bc5 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -702,6 +702,7 @@ static struct clk_ops zynqmp_clk_ops = {
 };
 
 static const struct udevice_id zynqmp_clk_ids[] = {
+	{ .compatible = "xlnx,zynqmp-clk" },
 	{ .compatible = "xlnx,zynqmp-clkc" },
 	{ }
 };
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 57a4e6c88e7..43e8b2520e3 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -11,6 +11,7 @@
 #include <zynqmppl.h>
 #include <linux/sizes.h>
 #include <asm/arch/sys_proto.h>
+#include <memalign.h>
 
 #define DUMMY_WORD	0xffffffff
 
@@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 		     bitstream_type bstype)
 {
+	ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
 	u32 swap;
 	ulong bin_buf;
 	int ret;
@@ -205,25 +207,37 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 		return FPGA_FAIL;
 
 	bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+	bsizeptr = (u32 *)&bsize;
 
 	debug("%s called!\n", __func__);
 	flush_dcache_range(bin_buf, bin_buf + bsize);
-
-	if (bsize % 4)
-		bsize = bsize / 4 + 1;
-	else
-		bsize = bsize / 4;
+	flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
 
 	buf_lo = (u32)bin_buf;
 	buf_hi = upper_32_bits(bin_buf);
-	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
-			 bstype, ret_payload);
+	bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
+	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+			 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
 	if (ret)
 		debug("PL FPGA LOAD fail\n");
 
 	return ret;
 }
 
+static int zynqmp_pcap_info(xilinx_desc *desc)
+{
+	int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+			 0, ret_payload);
+	if (!ret)
+		printf("PCAP status\t0x%x\n", ret_payload[1]);
+
+	return ret;
+}
+
 struct xilinx_fpga_op zynqmp_op = {
 	.load = zynqmp_load,
+	.info = zynqmp_pcap_info,
 };
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 2ff716c2522..db9bd12992f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -17,6 +17,7 @@
 #include <asm/arch/sys_proto.h>
 
 #define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
+#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK	0x00001000
 #define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV		0x00040000
@@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
 		/* Setting PCFG_PROG_B signal to high */
 		control = readl(&devcfg_base->ctrl);
 		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+		/*
+		 * Delay is required if AES efuse is selected as
+		 * key source.
+		 */
+		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+			mdelay(5);
+
 		/* Setting PCFG_PROG_B signal to low */
 		writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 
+		/*
+		 * Delay is required if AES efuse is selected as
+		 * key source.
+		 */
+		if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+			mdelay(5);
+
 		/* Polling the PCAP_INIT status for Reset */
 		ts = get_timer(0);
 		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 9c82c7db33f..3be66efb73f 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK		0x70000000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT		28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK		0xFFFF0000
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK		0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT	16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK		0xFF
@@ -796,7 +796,7 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 	writel(reg_val, &arasan_nand_base->cmd_reg);
 
 	page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
-		ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
+		ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
 	       &arasan_nand_base->memadr_reg1);
diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 3f80f0495e8..7142a99ce58 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -105,7 +105,7 @@ static int xilinxphy_of_init(struct phy_device *phydev)
 
 	debug("%s\n", __func__);
 	phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
-				 "phy-type", -1);
+				 "xlnx,phy-type", -1);
 	if (phytype == XAE_PHY_TYPE_1000BASE_X)
 		phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
 
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 70a2e95a8ec..80ed06ac66c 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -78,9 +78,10 @@ static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
 struct axidma_reg {
 	u32 control; /* DMACR */
 	u32 status; /* DMASR */
-	u32 current; /* CURDESC */
-	u32 reserved;
-	u32 tail; /* TAILDESC */
+	u32 current; /* CURDESC low 32 bit */
+	u32 current_hi; /* CURDESC high 32 bit */
+	u32 tail; /* TAILDESC low 32 bit */
+	u32 tail_hi; /* TAILDESC high 32 bit */
 };
 
 /* Private driver structures */
@@ -168,6 +169,22 @@ static inline int mdio_wait(struct axi_regs *regs)
 	return 0;
 }
 
+/**
+ * axienet_dma_write -	Memory mapped Axi DMA register Buffer Descriptor write.
+ * @bd:		pointer to BD descriptor structure
+ * @desc:	Address offset of DMA descriptors
+ *
+ * This function writes the value into the corresponding Axi DMA register.
+ */
+static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
+{
+#if defined(CONFIG_PHYS_64BIT)
+	writeq(bd, desc);
+#else
+	writel((u32)bd, desc);
+#endif
+}
+
 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 		   u16 *val)
 {
@@ -465,7 +482,7 @@ static int axiemac_start(struct udevice *dev)
 	writel(temp, &priv->dmarx->control);
 
 	/* Start DMA RX channel. Now it's ready to receive data.*/
-	writel((u32)&rx_bd, &priv->dmarx->current);
+	axienet_dma_write(&rx_bd, &priv->dmarx->current);
 
 	/* Setup the BD. */
 	memset(&rx_bd, 0, sizeof(rx_bd));
@@ -485,7 +502,7 @@ static int axiemac_start(struct udevice *dev)
 	writel(temp, &priv->dmarx->control);
 
 	/* Rx BD is ready - start */
-	writel((u32)&rx_bd, &priv->dmarx->tail);
+	axienet_dma_write(&rx_bd, &priv->dmarx->tail);
 
 	/* Enable TX */
 	writel(XAE_TC_TX_MASK, &regs->tc);
@@ -527,7 +544,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 
 	if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 		u32 temp;
-		writel((u32)&tx_bd, &priv->dmatx->current);
+		axienet_dma_write(&tx_bd, &priv->dmatx->current);
 		/* Start the hardware */
 		temp = readl(&priv->dmatx->control);
 		temp |= XAXIDMA_CR_RUNSTOP_MASK;
@@ -535,7 +552,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 	}
 
 	/* Start transfer */
-	writel((u32)&tx_bd, &priv->dmatx->tail);
+	axienet_dma_write(&tx_bd, &priv->dmatx->tail);
 
 	/* Wait for transmission to complete */
 	debug("axiemac: Waiting for tx to be done\n");
@@ -626,7 +643,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 	flush_cache((u32)&rxframe, sizeof(rxframe));
 
 	/* Rx BD is ready - start again */
-	writel((u32)&rx_bd, &priv->dmarx->tail);
+	axienet_dma_write(&rx_bd, &priv->dmarx->tail);
 
 	debug("axiemac: RX completed, framelength = %d\n", length);