patch - arm - define SYS_CACHELINE_SIZE for mx5

mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards

Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too

Signed-off-by: Chris Kuethe <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Matthew Starr <[email protected]>
Cc: Andrej Rosano <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Chris Kuethe <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>

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