Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.

DDR and memory handling

  * Add DRAM size checking support for Arria10.
  * Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
  * Assign unit address to memory node for improved memory
    representation and consistency.

Agilex / Agilex5 updates

  * Restore multi-DTB support for NAND boot and fix NAND clock handling.
  * Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
  * Fix DT property naming conventions for Agilex5.
  * Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
    to avoid unintended clock control.

New board support

  * Add support for CoreCourse Cyclone V boards:
     * AC501
     * AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.

Fixes and cleanup

  * Fix GEN5 handoff script path.
  * Remove incorrect CONFIG_SPL_LDSCRIPT settings.
  * Replace legacy TARGET namespace and perform related cleanup across
    SoCFPGA code.
  * General Kconfig, build and SoCFPGA maintenance updates.

Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.

[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <[email protected]>

4 files changed, 33 insertions, 7 deletions

diff --git a/include/configs/socfpga_ac501soc.h b/include/configs/socfpga_ac501soc.h
new file mode 100644
index 00000000000..703520e7cb8
--- /dev/null
+++ b/include/configs/socfpga_ac501soc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Brian Sune <[email protected]>
+ */
+#ifndef __CONFIG_CORESOURCE_AC501SOC_H__
+#define __CONFIG_CORESOURCE_AC501SOC_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_CORESOURCE_AC501SOC_H__ */
diff --git a/include/configs/socfpga_ac550soc.h b/include/configs/socfpga_ac550soc.h
new file mode 100644
index 00000000000..48e02d61dc5
--- /dev/null
+++ b/include/configs/socfpga_ac550soc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Brian Sune <[email protected]>
+ */
+#ifndef __CONFIG_CORESOURCE_AC550SOC_H__
+#define __CONFIG_CORESOURCE_AC550SOC_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_CORESOURCE_AC550SOC_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2acfdc7df4a..36d6bfb3d03 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -11,10 +11,10 @@
  * Memory configurations
  */
 #define PHYS_SDRAM_1			0x0
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #define CFG_SYS_INIT_RAM_ADDR	0xFFFF0000
 #define CFG_SYS_INIT_RAM_SIZE	SOCFPGA_PHYS_OCRAM_SIZE
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #define CFG_SYS_INIT_RAM_ADDR	0xFFE00000
 /* SPL memory allocation configuration, this is for FAT implementation */
 #define CFG_SYS_INIT_RAM_SIZE	(SOCFPGA_PHYS_OCRAM_SIZE - \
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 3d09a06f63e..4d333c63ad9 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -41,7 +41,7 @@
 /*
  * U-Boot run time memory configurations
  */
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define CFG_SYS_INIT_RAM_ADDR	0x0
 #define CFG_SYS_INIT_RAM_SIZE	0x80000
 #else
@@ -118,7 +118,7 @@
 
 #include <config_distro_bootcmd.h>
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	"kernel_addr_r=0x82000000\0" \
@@ -182,7 +182,7 @@
 	"smc_fid_wr=0xC2000008\0" \
 	"smc_fid_upd=0xC2000009\0 " \
 	BOOTENV
-#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/
+#endif /*#IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)*/
 
 #else
 
@@ -245,7 +245,7 @@
 /*
  * External memory configurations
  */
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
 #define CFG_SYS_SDRAM_BASE		0x80000000
@@ -270,7 +270,7 @@
 /*
  * L4 Watchdog
  */
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#ifdef CONFIG_ARCH_SOCFPGA_STRATIX10
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CFG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)