Merge patch series "This series introduces initial U-Boot support for mach-axiado AX3005 SCM3005 board, a quad-core ARM Cortex-A53 (ARMv8/ARM64) platform."

Siu Ming Tong <[email protected]> says:

Patch 1 adds the device tree files: an SoC-level DTSI describing
GIC-v3, Cadence/Zynq UART, a fixed reference clock, and spin-table
secondary CPU boot, plus a board-level DTS setting the console to
uart3 at 115200 baud with 2 GB DRAM at 0x80000000.

Patch 2 adds mach-axiado to support Axiado SoC-based boards, Kconfig
plumbing (AXIADO_AX3005 and TARGET_SCM3005), defconfig, board source
with ft_board_setup() and a MAINTAINERS entry.

Tested on SCM3005 EVK hardware

Link: https://lore.kernel.org/r/[email protected]

1 files changed, 29 insertions, 0 deletions

diff --git a/include/configs/ax3005-scm3005.h b/include/configs/ax3005-scm3005.h
new file mode 100644
index 00000000000..4eead2910c8
--- /dev/null
+++ b/include/configs/ax3005-scm3005.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
+ */
+
+#ifndef __AX3005_SCM3005_H
+#define __AX3005_SCM3005_H
+
+#include <linux/sizes.h>
+
+#define GICD_BASE		0x40400000
+#define GICR_BASE		0x40500000
+
+#define SYS_TIMER_CTRL		0x48016000
+#define SYS_TIMER_ENABLE	0x1
+#define SYS_TIMER_DISABLE	0x0
+
+/* DRAM: 2 GB at 0x80000000 */
+#define CFG_SYS_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_SIZE	SZ_2G
+#define CFG_SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + SZ_1M)
+
+#define CFG_SYS_MAXARGS		64
+#define CFG_SYS_BARGSIZE	CFG_SYS_CBSIZE
+
+#define CFG_SYS_BAUDRATE_TABLE	\
+	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+
+#endif /* __AX3005_SCM3005_H */