diff options
| author | Tom Rini <[email protected]> | 2022-07-06 09:15:36 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-07-06 09:15:36 -0400 |
| commit | 4b7d0b24c7047c70d13db953b950a549accb8e14 (patch) | |
| tree | d3b1ad18c27f5c8239fbb8dd3a6a70291db6eca4 /include | |
| parent | e1d3e637c78790e18d64733fae913d088c4c3c76 (diff) | |
| parent | 432243cee100e1d8f60399f0ae8f76cf7c83975f (diff) | |
Merge branch '2022-07-05-more-Kconfig-migrations' into next
- Migrate more CONFIG symbols to Kconfig, remove some dead code and
clean-up arch/Kconfig.nxp slightly more.
Diffstat (limited to 'include')
87 files changed, 18 insertions, 551 deletions
diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 3922241be00..380c906ba83 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -10,10 +10,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - /* * Control should not reach back to uboot after validation of images * for secure boot flow and therefore bootscript should have @@ -21,43 +17,22 @@ * after validating images, core should just spin. */ -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - #ifdef CONFIG_USE_BOOTARGS -#define CONFIG_SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" +#define SET_BOOTARGS "setenv bootargs \'" CONFIG_BOOTARGS" \';" #else -#define CONFIG_SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ +#define SET_BOOTARGS "setenv bootargs \'root=/dev/ram " \ "rw console=ttyS0,115200 ramdisk_size=600000\';" #endif - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ +#define SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - CONFIG_SET_BOOTARGS \ - CONFIG_EXTRA_ENV \ + SET_BOOTARGS \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt\0" -#endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ +#define BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ @@ -68,33 +43,28 @@ /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \ defined(CONFIG_SD_BOOT) -#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT) -#define CONFIG_BS_COPY_CMD \ +#if defined(CONFIG_NAND_BOOT) +#define BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "nand read $bs_ram $bs_device $bs_size ;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ "mmc read $bs_ram $bs_device $bs_size ;" #endif #else -#define CONFIG_BS_COPY_CMD \ +#define BS_COPY_CMD \ "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ "cp.b $bs_device $bs_ram $bs_size ;" #endif +#else /* !CONFIG_BOOTSCRIPT_COPY_RAM */ +#define BS_COPY_ENV +#define BS_COPY_CMD #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT +#define CHAIN_BOOT_CMD BS_COPY_ENV \ + BS_COPY_CMD \ + SECBOOT #endif #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 8e75d779c41..3e4d66874df 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -198,43 +198,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ /* * TSEC diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d8ffa2e28a9..2eb33812f76 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,10 +16,6 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#undef CONFIG_PCI2 - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ @@ -34,7 +30,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -264,8 +259,6 @@ */ #if !CONFIG_IS_ENABLED(DM_I2C) #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 #endif /* EEPROM */ @@ -319,10 +312,6 @@ #endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #define CONFIG_TSEC1 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ad78dba865b..aea744c826c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -53,7 +53,6 @@ #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif @@ -64,9 +63,6 @@ /* High Level Configuration Options */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -98,8 +94,6 @@ #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif #define CONFIG_HWCONFIG @@ -108,12 +102,7 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ - -#define CONFIG_ENABLE_36BIT_PHYS - /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -353,8 +342,7 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -472,9 +460,7 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index df16319de4a..e019c168434 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -33,9 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ @@ -43,11 +40,6 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - #ifndef __ASSEMBLY__ #include <linux/stringify.h> #endif @@ -58,8 +50,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -91,7 +81,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -332,10 +321,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 6063113634c..bc8aa3ce054 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -9,8 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_SRIO diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 6615dd091e2..6375c65d483 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -9,8 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index 6e6e5bec66b..fb73f0b9539 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -9,7 +9,6 @@ */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ -#define CONFIG_PCIE3 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 8114373655f..e42e6d56532 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index b70829c09d5..8926c26b0bd 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -9,10 +9,6 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - /* * NS16550 Configuration */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bd458ff35e9..a519b5a9355 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,7 +15,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS @@ -127,11 +126,9 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif @@ -355,9 +352,6 @@ * General PCIe * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ @@ -383,8 +377,6 @@ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 505bae931e6..3a7c643cfc9 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -61,18 +61,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_NAND -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -#endif /* * These can be toggled for performance analysis, otherwise use default. @@ -83,8 +71,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -108,7 +94,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -377,8 +362,6 @@ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ /* diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2db2b07fb4b..eff22c18bb7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS @@ -96,7 +95,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -370,10 +368,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -397,10 +391,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 07e1108f0f0..ba9bfdd72f7 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,7 +17,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS @@ -91,7 +90,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -323,10 +321,6 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull @@ -350,10 +344,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN #define CONFIG_SYS_BMAN_NUM_PORTALS 18 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 526d40fa034..12b479f9c77 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,8 +12,6 @@ #include <linux/stringify.h> -#define CONFIG_PCIE4 - #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL @@ -44,9 +42,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ /* * These can be toggled for performance analysis, otherwise use default. @@ -56,8 +51,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ @@ -145,10 +138,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - /* * Environment */ @@ -180,7 +169,6 @@ /* * DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index a362282a291..6a4092a83e2 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -19,9 +19,6 @@ #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" -/* PCI host support */ -#undef CONFIG_PCI_SCAN_SHOW - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e3350282bcf..e418edddfbe 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -22,8 +22,6 @@ /* LCD */ #define LCD_BPP LCD_COLOR8 -/* Let board_init_f handle the framebuffer allocation */ -#undef CONFIG_FB_ADDR /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 9969269bf2a..9c9e9506dc6 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -28,9 +28,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index bb1595f9611..5da2778b67b 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -17,9 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* * Environment Configuration */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f563a5f3816..2252bf89543 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -15,17 +15,8 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_NAND -#endif -#define CONFIG_BOOTSCRIPT_COPY_RAM -#else -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -45,13 +36,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif /* * These can be toggled for performance analysis, otherwise use default. @@ -62,8 +46,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -94,7 +76,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -333,10 +314,6 @@ #define CONFIG_SYS_DPAA_PME #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 6912f39d32d..b9d03d253d9 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -14,9 +14,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 3b3a7abd281..bba2b607aa8 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -17,9 +17,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 715a6d7a9e7..7b305955c96 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -21,9 +21,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* NAND */ /* diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 7e3f657e31c..f8273a92f11 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -19,9 +19,6 @@ /* I2C */ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/durian.h b/include/configs/durian.h index c224511832f..7971df8c1d3 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,9 +13,6 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* PCI CONFIG */ -#define CONFIG_PCI_SCAN_SHOW - /* BOOT */ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 79860212f40..246aa9b7ab9 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -18,9 +18,6 @@ /* select serial console configuration */ -/* PWM */ -#define CONFIG_PWM - /* Miscellaneous configurable options */ #endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 625a2d8dc18..054cb5309e7 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index c50ecf27e44..49f57dda58f 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,9 +21,6 @@ "stdout=serial\0" \ "stderr=serial\0" -/* 10/100M Ethernet support */ -#define CONFIG_DW_ALTDESCRIPTOR - /* Environment configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d813c6c22e7..ad00769bdee 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -109,7 +109,4 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 47a72fc8fce..4a0aaf4da58 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -31,9 +31,6 @@ /* * PCI express */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX -#endif /* * PMIC diff --git a/include/configs/helios4.h b/include/configs/helios4.h index ff2c5064432..fc32487e1c7 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -28,9 +28,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7430185666e..a12923386a5 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ @@ -174,7 +173,6 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index e58a69501b3..01482d53199 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -23,7 +23,6 @@ /* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_HOSTNAME "km_kirkwood" -#define CONFIG_KM_DISABLE_PCIE /* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) @@ -34,7 +33,6 @@ /* KM_KIRKWOOD_128M16 */ #elif defined(CONFIG_KM_KIRKWOOD_128M16) #define CONFIG_HOSTNAME "km_kirkwood_128m16" -#define CONFIG_KM_DISABLE_PCIE /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) @@ -44,7 +42,6 @@ /* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_HOSTNAME "kmcoge5un" -#define CONFIG_KM_DISABLE_PCIE /* KM_SUSE2 */ #elif defined(CONFIG_KM_SUSE2) @@ -118,8 +115,4 @@ MVGBE_SET_MII_SPEED_TO_100) #endif -#ifdef CONFIG_KM_DISABLE_PCIE -#undef CONFIG_KIRKWOOD_PCIE_INIT -#endif - #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 4de5736d8ce..ed24733abf5 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -140,7 +140,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 @@ -152,8 +151,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - /* POST memory regions test */ #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS @@ -173,7 +170,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 19201a735f0..0c194ee575b 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -15,9 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -/* CSU */ -#define CONFIG_LAYERSCAPE_NS_ACCESS - /*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 7f083c597e3..a0ff3b89790 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -25,10 +25,6 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5992366cf4..b124ce52620 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -82,10 +82,6 @@ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ DSPI_CTAR_DT(0)) -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c57b598d70d..4f77acdaede 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,10 +36,6 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 6a0ccbf836f..ec688741a07 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -97,18 +97,9 @@ #define TSEC2_PHYIDX 0 #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e17bdcad6d0..1a46f72a735 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -23,11 +23,6 @@ #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE @@ -306,16 +301,7 @@ #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index b06394c3003..e5754c94e0f 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -80,14 +80,7 @@ #define FSL_QSPI_FLASH_NUM 2 /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d85a776daa1..09dce21aec5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -171,16 +171,7 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8363969d557..ed32e20dbf4 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -108,17 +108,6 @@ /* I2C */ -/* PCIe */ -#ifndef SPL_NO_PCIE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif -#endif - /* DSPI */ /* FMan ucode */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 75d655c50d6..15c3ff53fe8 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -8,12 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index edb4e64ee41..6c33847b27b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -8,14 +8,9 @@ #include "ls1043a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - #ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index e139aa93e1f..94118c420e6 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -76,15 +76,6 @@ /* I2C */ -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* SATA */ #ifndef SPL_NO_SATA #define CONFIG_SYS_SATA AHCI_BASE_ADDR diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index e663fa0f6c7..43717cdd4e6 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,8 +8,6 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - #define CONFIG_SYS_UBOOT_BASE 0x40100000 /* diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 6271135db9f..36c64db8f5d 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -8,12 +8,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 4ad62b43f8c..382d5c76461 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,12 +9,9 @@ #include "ls1046a_common.h" -#define CONFIG_LAYERSCAPE_NS_ACCESS - /* Physical Memory Map */ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index e532c343f48..debb60d25ce 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -16,7 +16,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -306,10 +305,6 @@ #define CONFIG_FSL_MEMAC -/* MMC */ -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - #define COMMON_ENV \ "kernelheader_addr_r=0x80200000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index c69003018bf..c0567c3fe58 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,13 +15,8 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#ifdef CONFIG_EMU -#define CONFIG_SYS_FSL_DDR_EMU -#else #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f9eb829cda2..d2978713e6b 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,10 +16,6 @@ /* Link Definitions */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 21ca4afa51c..9ba7258572f 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -24,10 +24,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -243,14 +239,6 @@ #define FSL_QIXIS_BRDCFG9_QSPI 0x1 /* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - -/* * RTC configuration */ #define RTC @@ -263,10 +251,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 43bcc5a9b11..a504a0ea462 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -29,10 +29,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) @@ -242,10 +238,6 @@ #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1669ecd2aba..77e25822dcd 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -31,7 +31,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ @@ -90,11 +89,6 @@ /* Qixis */ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* USB */ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index e7aec6bc596..585aab26bff 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -11,16 +11,6 @@ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* MAC/PHY configuration */ /* EEPROM */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 729c2707e99..d1ae4034731 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -13,16 +13,6 @@ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - /* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 diff --git a/include/configs/malta.h b/include/configs/malta.h index 225ed7cd5cd..affee006940 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -13,9 +13,6 @@ #define CONFIG_MEMSIZE_IN_BYTES -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_MSC01 - #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 /* diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index ef255aa360e..16f8858abb8 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 7bbc500ae12..58d550fee9e 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -129,8 +129,6 @@ #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 72a9f4ec24f..2007b48868f 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -97,12 +97,4 @@ /* Environment organization */ -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/novena.h b/include/configs/novena.h index ee39b3c297c..1696aa28520 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -39,7 +39,6 @@ /* I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ @@ -49,8 +48,6 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 6be214753f1..97f47ea5b71 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -66,7 +66,6 @@ BOOTENV /* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 2a24236c111..f4bf2ab830a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -102,23 +102,16 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_L2_CACHE -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) @@ -348,8 +341,6 @@ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } #endif -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - /* * I2C2 EEPROM */ @@ -393,8 +384,6 @@ #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -421,9 +410,7 @@ /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index c3fef0de173..451ae0e1e6d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -11,8 +11,6 @@ #define CONFIG_SYS_RAMBOOT -#define CONFIG_ENABLE_36BIT_PHYS - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ @@ -27,10 +25,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -/* Virtual address range for PCI region maps */ -#define CONFIG_SYS_PCI_MAP_START 0x80000000 -#define CONFIG_SYS_PCI_MAP_END 0xe0000000 - /* Virtual address to a temporary map if we need it (max 128MB) */ #define CONFIG_SYS_TMPVIRT 0xe8000000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ae712629df3..409d5af0241 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -25,9 +25,4 @@ */ #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ -/* - * SuperH PCI Bridge Configration - */ -#define CONFIG_SH7751_PCI - #endif /* __CONFIG_H */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 8b7e2e5dc9e..712a47a4956 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -21,9 +21,6 @@ /* MMC */ #define SDHCI_MAX_HOSTS 4 -/* PWM */ -#define CONFIG_PWM 1 - /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -129,10 +126,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xB0000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index ab4fe6b4602..137537d65f6 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -87,12 +87,8 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a7b0ce9f975..1395b8dfe38 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -24,9 +24,6 @@ * select serial console configuration */ -/* PWM */ -#define CONFIG_PWM 1 - #define COMMON_BOOT "console=ttySAC0,115200n8" \ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT @@ -89,22 +86,10 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#endif - /*----------------------------------------------------------------------- * Boot configuration */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 #define CONFIG_SYS_ONENAND_BASE 0xE7100000 /* diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index bb0f5473030..0b1f0c5f54c 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -10,8 +10,6 @@ #include "exynos4-common.h" -#undef CONFIG_USB_GADGET_DWC2_OTG_PHY - /* High Level Configuration Options */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 10ba2d22ffa..4a7da76e51e 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -52,13 +52,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * Ethernet on SoC (EMAC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_DW_ALTDESCRIPTOR -#endif - -/* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER @@ -73,7 +66,6 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 /* diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index c388ae9a816..a3e8d549291 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -89,15 +89,9 @@ * Flash configurations */ -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DW_ALTDESCRIPTOR -#endif /* CONFIG_CMD_NET */ - /* * L4 Watchdog */ -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3309779118a..6a78cb1f264 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 /* * sysclk for MPC85xx @@ -119,15 +118,11 @@ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - /* * General PCI * Memory space is mapped 1-1. */ -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 05ac900f3c3..df05ee4892a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -20,9 +20,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) -#define CONFIG_DW_ALTDESCRIPTOR - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 2195feeb658..797d9bbb4af 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK #define CONFIG_PRAM 2048 /* 2048 KB */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index c57b1ad8a06..567aa1ffe43 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -20,10 +20,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */ -/* GMAC related configs */ - -#define CONFIG_DW_ALTDESCRIPTOR - /* Misc configuration */ #endif /* __CONFIG_H */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index dd2c5d77445..c93df00d58d 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -26,8 +26,6 @@ /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif diff --git a/include/configs/trats.h b/include/configs/trats.h index bca239ae817..53f5a6996bd 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -149,7 +149,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 20bd116c9e3..b7449dab8bd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -139,7 +139,6 @@ #define LCD_BPP LCD_COLOR16 /* LCD */ -#define CONFIG_FB_ADDR 0x52504000 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 7f4bfb5124a..32d9df0a00c 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -26,7 +26,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_SPD_BUS_NUM 0 /* * We do have 128MB of memory on the Vybrid Tower board. Leave the last diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 9cc8fc5ff53..6eb022f26c5 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -45,8 +45,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif diff --git a/include/configs/x530.h b/include/configs/x530.h index 1f1b4e1449e..cb126837b9c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,9 +47,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#define CONFIG_PCI_SCAN_SHOW - /* NAND */ #include <asm/arch/config.h> diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b45d2bbd626..4109af7d851 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,18 +12,6 @@ #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f28fafe15c6..1366f623aa2 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -45,11 +45,6 @@ */ /*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE - -/*----------------------------------------------------------------------- * USB configuration */ diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index fb838db0b53..3092a0ea62a 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -23,8 +23,6 @@ #define sec_mon_in16(a) in_be16(a) #define sec_mon_clrbits32 clrbits_be32 #define sec_mon_setbits32 setbits_be32 -#else -#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined #endif struct ccsr_sec_mon_regs { diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 613814d9057..e7674c1bff2 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -24,8 +24,6 @@ #define sfp_in32(a) in_be32(a) #define sfp_out32(a, v) out_be32(a, v) #define sfp_in16(a) in_be16(a) -#else -#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined #endif /* Number of SRKH registers */ diff --git a/include/i2c.h b/include/i2c.h index 22add0b5282..e0ee94e5504 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -647,9 +647,6 @@ void i2c_early_init_f(void); #if !defined(CONFIG_SYS_RTC_BUS_NUM) #define CONFIG_SYS_RTC_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, |