Merge tag 'xilinx-for-v2024.10-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx changes for v2024.10-rc2

amd/xilinx:
- Enable CONFIG_MMC_SPEED_MODE_SET

env:
- support overriding spi dev from board code

clk:
- Add set_rate support for display clocks

spi:
- Describe is25lp01gg flash

zynq:
- Add support for 7z010_lr and 7z020_lr

zynqmp:
- Add support for zu1eg_lr
- Enable NFS for Kria
- DT changes
- Cleanup firmware handling in board_init()

versal-net:
- Setup spi seq number based on boot device
- dt-schema update for mini configurations

versal2:
- Disable uartlite driver
- Add support for mini configurations
- Enable NFS

3 files changed, 28 insertions, 0 deletions

diff --git a/include/configs/amd_versal2_mini.h b/include/configs/amd_versal2_mini.h
new file mode 100644
index 00000000000..97e8f673a83
--- /dev/null
+++ b/include/configs/amd_versal2_mini.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for AMD Versal Gen2 MINI configuration
+ *
+ * Copyright (C) 2023 - 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <[email protected]>
+ */
+
+#ifndef __CONFIG_VERSAL2_MINI_H
+#define __CONFIG_VERSAL2_MINI_H
+
+#define CFG_EXTRA_ENV_SETTINGS
+
+#include <configs/amd_versal2.h>
+
+/* Undef unneeded configs */
+#undef CFG_EXTRA_ENV_SETTINGS
+
+#endif /* __CONFIG_VERSAL2_MINI_H */
diff --git a/include/spi.h b/include/spi.h
index 7e38cc2a2ad..9e9851284c8 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -743,4 +743,6 @@ int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep,
 #define spi_get_ops(dev)	((struct dm_spi_ops *)(dev)->driver->ops)
 #define spi_emul_get_ops(dev)	((struct dm_spi_emul_ops *)(dev)->driver->ops)
 
+int spi_get_env_dev(void);
+
 #endif	/* _SPI_H_ */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index d7dc064585e..08d067d8757 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -20,9 +20,11 @@ extern struct xilinx_fpga_op zynq_op;
 
 #define XILINX_ZYNQ_XC7Z007S	0x3
 #define XILINX_ZYNQ_XC7Z010	0x2
+#define XILINX_ZYNQ_XC7Z010_LR	0x4
 #define XILINX_ZYNQ_XC7Z012S	0x1c
 #define XILINX_ZYNQ_XC7Z014S	0x8
 #define XILINX_ZYNQ_XC7Z015	0x1b
+#define XILINX_ZYNQ_XC7Z020_LR	0x9
 #define XILINX_ZYNQ_XC7Z020	0x7
 #define XILINX_ZYNQ_XC7Z030	0xc
 #define XILINX_ZYNQ_XC7Z035	0x12
@@ -32,9 +34,11 @@ extern struct xilinx_fpga_op zynq_op;
 /* Device Image Sizes */
 #define XILINX_XC7Z007S_SIZE	16669920/8
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z010_LR_SIZE	16669920/8
 #define XILINX_XC7Z012S_SIZE	28085344/8
 #define XILINX_XC7Z014S_SIZE	32364512/8
 #define XILINX_XC7Z015_SIZE	28085344/8
+#define XILINX_XC7Z020_LR_SIZE	32364512/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
 #define XILINX_XC7Z035_SIZE	106571232/8
@@ -44,9 +48,11 @@ extern struct xilinx_fpga_op zynq_op;
 /* Device Names */
 #define XILINX_XC7Z007S_NAME	"7z007s"
 #define XILINX_XC7Z010_NAME	"7z010"
+#define XILINX_XC7Z010_LR_NAME	"xc7z010_lr"
 #define XILINX_XC7Z012S_NAME	"7z012s"
 #define XILINX_XC7Z014S_NAME	"7z014s"
 #define XILINX_XC7Z015_NAME	"7z015"
+#define XILINX_XC7Z020_LR_NAME	"xa7z020_lr"
 #define XILINX_XC7Z020_NAME	"7z020"
 #define XILINX_XC7Z030_NAME	"7z030"
 #define XILINX_XC7Z035_NAME	"7z035"