Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga

This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.

Highlights:

- Agilex7 M-series bring-up:
  - Basic DT support and board initialization for Agilex7 M-series SoC and
    SoCDK.
  - New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
  - Clock driver support for Agilex7 M-series.
  - New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
  - Improved SPL support: ASYNC interrupt enabling, system manager init
    refactor, and cold scratch register usage.
  - Updated firewall probing and watchdog support in SPL.
  - Cleaned up DDR code, added secure region support for ATF, and improved warm
    reset handling.
- Device Tree and config updates:
  - Migration to upstream Linux DT layout for Agilex platforms.
  - Consolidated socfpga_agilex_defconfig and removed deprecated configs.
  - Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
  - dwc_eth_xgmac and clk-agilex cleanup and improvements.
  - Several coverity and style fixes.

Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody.  This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.

Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318

2 files changed, 34 insertions, 0 deletions

diff --git a/include/configs/socfpga_agilex7m_socdk.h b/include/configs/socfpga_agilex7m_socdk.h
new file mode 100644
index 00000000000..deff70ee67a
--- /dev/null
+++ b/include/configs/socfpga_agilex7m_socdk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX7M_H__
+#define __CONFIG_SOCFGPA_AGILEX7M_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_AGILEX7M_H__ */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 83b600c7fcc..3d09a06f63e 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -19,6 +19,20 @@
 #define CPU_RELEASE_ADDR		0xFFD12210
 
 /*
+ * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR
+ * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3.
+ */
+#define L2_RESET_DONE_REG		0xFFD12218
+
+/* sysmgr.boot_scratch_cold8 bit 17 (1bit) will be used to check whether CPU0
+ * is being powered off/on from kernel
+ */
+#define BOOT_SCRATCH_COLD8		0xFFD12220
+
+/* Magic word to indicate L2 reset is completed */
+#define L2_RESET_DONE_STATUS		0x1228E5E7
+
+/*
  * U-Boot console configurations
  */
 
@@ -39,6 +53,9 @@
  * U-Boot environment configurations
  */
 
+#define CFG_SYS_NAND_U_BOOT_SIZE	(1 * 1024 * 1024)
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+
 /*
  * Environment variable
  */
@@ -159,6 +176,7 @@
 		" ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
 	"scriptaddr=0x05FF0000\0" \
 	"scriptfile=boot.scr\0" \
+	"nandroot=ubi0:rootfs\0" \
 	"socfpga_legacy_reset_compat=1\0" \
 	"smc_fid_rd=0xC2000007\0" \
 	"smc_fid_wr=0xC2000008\0" \
@@ -214,6 +232,10 @@
 	"scriptfile=u-boot.scr\0" \
 	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
 		   "then source ${scriptaddr}:script; fi\0" \
+	"nandfitboot=setenv bootargs " CONFIG_BOOTARGS \
+			" root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \
+			"bootm ${loadaddr}\0" \
+	"nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \
 	"socfpga_legacy_reset_compat=1\0" \
 	"smc_fid_rd=0xC2000007\0" \
 	"smc_fid_wr=0xC2000008\0" \