diff options
| author | Tom Rini <[email protected]> | 2025-05-21 08:59:10 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-05-21 09:00:21 -0600 |
| commit | 8f85a7345ed5df70a155f0630da72970eb01d87a (patch) | |
| tree | 10acf511e4f955f5874d9e64331c841609b4804a /include | |
| parent | 0a87352281ade2b822ce0360e1f105f6e43a96e1 (diff) | |
| parent | ff6e20c32ff33c6963f7d0a79a0914681461f4fa (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259
- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/starfive-visionfive2.h | 2 | ||||
| -rw-r--r-- | include/configs/th1520_lpi4a.h | 1 | ||||
| -rw-r--r-- | include/image.h | 3 |
3 files changed, 5 insertions, 1 deletions
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 049b0a06301..e7001b26abf 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -39,4 +39,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" +#define CFG_SYS_NS16550_CLK 24000000 + #endif /* _STARFIVE_VISIONFIVE2_H */ diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h index 87496a52c4c..7a9b70a3678 100644 --- a/include/configs/th1520_lpi4a.h +++ b/include/configs/th1520_lpi4a.h @@ -9,6 +9,7 @@ #include <linux/sizes.h> +#define CFG_SYS_NS16550_CLK 100000000 #define CFG_SYS_SDRAM_BASE 0x00000000 #define UART_BASE 0xffe7014000 diff --git a/include/image.h b/include/image.h index c1db8383459..4620782c069 100644 --- a/include/image.h +++ b/include/image.h @@ -138,7 +138,8 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ - IH_ARCH_RISCV, /* RISC-V */ + IH_ARCH_RISCV, /* RISC-V 32 bit*/ + IH_ARCH_RISCV64, /* RISC-V 64 bit*/ IH_ARCH_COUNT, }; |