diff options
| author | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
| commit | 93f84ee022a8401421cdaab84fe7d106d83fdb4a (patch) | |
| tree | fb15a4af876e8faf9893fd86c1c0e127265dbe9a /include | |
| parent | 88dc2788777babfd6322fa655df549a019aa1e69 (diff) | |
| parent | e2138cf1e6088f12ffa874e87cc8f4b198378635 (diff) | |
Merge branch 'next'
Diffstat (limited to 'include')
53 files changed, 2599 insertions, 511 deletions
diff --git a/include/bootcount.h b/include/bootcount.h index 847c0f02d98..86474569d36 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/byteorder.h> #include <env.h> +#include <linux/bitops.h> #ifdef CONFIG_DM_BOOTCOUNT @@ -59,6 +60,10 @@ int dm_bootcount_set(struct udevice *dev, u32 bootcount); #endif +/* Bit masks for magic and count parts in single word scheme */ +#define BOOTCOUNT_MAGIC_MASK GENMASK(31, 16) +#define BOOTCOUNT_COUNT_MASK GENMASK(15, 0) + /** bootcount_store() - store the current bootcount */ void bootcount_store(ulong); diff --git a/include/bootm.h b/include/bootm.h index 4060cec7fc0..f6958be751a 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -321,4 +321,14 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); */ int bootm_boot_start(ulong addr, const char *cmdline); +/** + * bootm_final() - Announce and do cleanup before boot + * + * This performs the common pre-boot steps: printing the "Starting kernel" + * message, recording bootstage data, and removing active devices. + * + * @flag: Boot state flags (BOOTM_STATE_OS_FAKE_GO prints a fake-run message) + */ +void bootm_final(int flag); + #endif diff --git a/include/bootstage.h b/include/bootstage.h index 528d0ca0614..62fb99110f0 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -435,6 +435,14 @@ static inline uint32_t bootstage_accum(enum bootstage_id id) return 0; } +static inline void bootstage_report(void) +{ +} + +static inline void bootstage_fdt_add_report(void) +{ +} + static inline int bootstage_stash(void *base, int size) { return 0; /* Pretend to succeed */ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 404af2cd4c6..38d0bfc315b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -108,7 +108,8 @@ #define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) #define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + "bootcmd_" #devtypel "=devnum=" #instance "; " \ + #devtypel " init $devnum; run scsi_boot\0" #define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ "ufs " diff --git a/include/configs/beaglev_fire.h b/include/configs/beaglev_fire.h new file mode 100644 index 00000000000..e3ee0f02f2d --- /dev/null +++ b/include/configs/beaglev_fire.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Microchip Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func)\ + BOOT_TARGET_DEVICES_DHCP(func) + +#define BOOTENV_DESIGN_OVERLAYS \ + "design_overlays=" \ + "if test -n ${no_of_overlays}; then " \ + "setenv inc 1; " \ + "setenv idx 0; " \ + "fdt resize ${dtbo_size}; " \ + "while test $idx -ne ${no_of_overlays}; do " \ + "setenv dtbo_name dtbo_image${idx}; " \ + "setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \ + "run fdt_cmd; " \ + "setexpr idx $inc + $idx; " \ + "done; " \ + "fi;\0 " \ + +#include <config_distro_bootcmd.h> + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x80200000\0" \ + "fdt_addr_r=0x8a000000\0" \ + "fdtoverlay_addr_r=0x8a080000\0" \ + "ramdisk_addr_r=0x8aa00000\0" \ + "scriptaddr=0x8e000000\0" \ + BOOTENV_DESIGN_OVERLAYS \ + BOOTENV \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 7120a44d186..ee13d2ab950 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -38,6 +38,19 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV +#ifdef CONFIG_ENV_WRITEABLE_LIST +#define CFG_ENV_FLAGS_LIST_STATIC \ + "bootcount:dw," \ + "bootdelay:sw," \ + "bootlimit:dw," \ + "partitionset_active:sw," \ + "rastate:dw," \ + "sig_a:sw,sig_b:sw," \ + "target_env:sw," \ + "upgrade_available:dw," \ + "ustate:dw" +#endif + /* Default location for tftp and bootm */ /* On CCP board, USDHC1 is for eMMC */ diff --git a/include/configs/imx952_evk.h b/include/configs/imx952_evk.h new file mode 100644 index 00000000000..4ff56eb8adf --- /dev/null +++ b/include/configs/imx952_evk.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025-2026 NXP + */ + +#ifndef __IMX952_EVK_H +#define __IMX952_EVK_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 + +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */ + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx91_93.h index 07364dff403..02fa1d9b274 100644 --- a/include/configs/phycore_imx93.h +++ b/include/configs/phycore_imx91_93.h @@ -6,8 +6,8 @@ * Copyright (C) 2024 Mathieu Othacehe <[email protected]> */ -#ifndef __PHYCORE_IMX93_H -#define __PHYCORE_IMX93_H +#ifndef __PHYCORE_IMX91_93_H +#define __PHYCORE_IMX91_93_H #include <linux/sizes.h> #include <asm/arch/imx-regs.h> @@ -25,4 +25,4 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -#endif /* __PHYCORE_IMX93_H */ +#endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/rk3506_common.h b/include/configs/rk3506_common.h new file mode 100644 index 00000000000..5e4ef67289f --- /dev/null +++ b/include/configs/rk3506_common.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __CONFIG_RK3506_COMMON_H +#define __CONFIG_RK3506_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0xfff80000 + +#define CFG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xc0000000 + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "kernel_addr_r=0x02080000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_size=0x2000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3506_COMMON_H */ diff --git a/include/configs/socfpga_ac501soc.h b/include/configs/socfpga_ac501soc.h new file mode 100644 index 00000000000..703520e7cb8 --- /dev/null +++ b/include/configs/socfpga_ac501soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune <[email protected]> + */ +#ifndef __CONFIG_CORESOURCE_AC501SOC_H__ +#define __CONFIG_CORESOURCE_AC501SOC_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_CORESOURCE_AC501SOC_H__ */ diff --git a/include/configs/socfpga_ac550soc.h b/include/configs/socfpga_ac550soc.h new file mode 100644 index 00000000000..48e02d61dc5 --- /dev/null +++ b/include/configs/socfpga_ac550soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune <[email protected]> + */ +#ifndef __CONFIG_CORESOURCE_AC550SOC_H__ +#define __CONFIG_CORESOURCE_AC550SOC_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_CORESOURCE_AC550SOC_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2acfdc7df4a..36d6bfb3d03 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -11,10 +11,10 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3d09a06f63e..4d333c63ad9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -41,7 +41,7 @@ /* * U-Boot run time memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_SYS_INIT_RAM_ADDR 0x0 #define CFG_SYS_INIT_RAM_SIZE 0x80000 #else @@ -118,7 +118,7 @@ #include <config_distro_bootcmd.h> -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ @@ -182,7 +182,7 @@ "smc_fid_wr=0xC2000008\0" \ "smc_fid_upd=0xC2000009\0 " \ BOOTENV -#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ +#endif /*#IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)*/ #else @@ -245,7 +245,7 @@ /* * External memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0x80000000 @@ -270,7 +270,7 @@ /* * L4 Watchdog */ -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 5e89cd6937a..00610e76869 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -7,256 +7,22 @@ * Configuration settings for the TQ-Systems TQMa6<Q,D,DL,S> module. */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* place code in last 4 MiB of RAM */ +#ifndef __TQMA6_CONFIG_H +#define __TQMA6_CONFIG_H #include "mx6_common.h" -#if defined(CONFIG_TQMA6S) -#define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_TQMA6DL) -#define PHYS_SDRAM_SIZE (SZ_1G) -#elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (SZ_1G) -#endif - -/* SPI Flash */ - -#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K - -#if !defined(CONFIG_DM_PMIC) -#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 -#define TQMA6_PFUZE100_I2C_BUS 2 -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#if defined(CONFIG_TQMA6X_MMC_BOOT) - -#define TQMA6_UBOOT_OFFSET SZ_1K -#define TQMA6_UBOOT_SECTOR_START 0x2 -#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe - -#define TQMA6_FDT_OFFSET (2 * SZ_1M) -#define TQMA6_FDT_SECTOR_START 0x1000 -#define TQMA6_FDT_SECTOR_COUNT 0x800 - -#define TQMA6_KERNEL_SECTOR_START 0x2000 -#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "loadimage=mmc dev ${mmcdev}; " \ - "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ - "loadfdt=mmc dev ${mmcdev}; " \ - "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_kernel=run kernel_name; " \ - "if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${kernel_size}; then " \ - "mmc write ${loadaddr} " \ - "${kernel_start} ${blkc}; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${fdt_size}; then " \ - "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - -#elif defined(CONFIG_TQMA6X_SPI_BOOT) - -#define TQMA6_UBOOT_OFFSET 0x400 -#define TQMA6_UBOOT_SECTOR_START 0x0 -/* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define TQMA6_UBOOT_SECTOR_COUNT 0x8 -#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ - TQMA6_UBOOT_SECTOR_COUNT) - -#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ - CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) - -#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ -#define TQMA6_FDT_SECTOR_COUNT 0x01 - -#define TQMA6_KERNEL_SECTOR_START 0x10 -#define TQMA6_KERNEL_SECTOR_COUNT 0x60 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "mmcblkdev=0\0" \ - "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ - "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr blkc ${filesize} + " \ - __stringify(TQMA6_UBOOT_OFFSET) "; " \ - "setexpr size ${uboot_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${blkc} <= ${size}; then " \ - "sf probe; " \ - "sf erase 0 ${size}; " \ - "sf write ${loadaddr} ${uboot_offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv blkc; setenv size \0" \ - "update_kernel=run kernel_name; if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "loadimage=sf probe; " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${loadaddr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - "loadfdt=sf probe; " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${fdt_addr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" -#else - -#error "need to define boot source" - -#endif - /* 128 MiB offset as in ARM related docu for linux suggested */ #define TQMA6_FDT_ADDRESS 0x18000000 -/* set to a resonable value, changeable by user */ -#define TQMA6_CMA_SIZE 160M +/* 256KiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_256K) */ +#define TQMA6_FDT_OVERLAY_ADDR 0x18040000 -#define CFG_EXTRA_ENV_SETTINGS \ - "board=tqma6\0" \ - "uimage=uImage\0" \ - "zimage=zImage\0" \ - "boot_type=bootz\0" \ - "kernel_name=if test \"${boot_type}\" != bootz; then " \ - "setenv kernel ${uimage}; " \ - "else setenv kernel ${zimage}; fi\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ - "initrd_high=0xffffffff\0" \ - "rootfsmode=ro\0" \ - "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ - "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "addfb=setenv bootargs ${bootargs} " \ - "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ - "mmcpart=2\0" \ - "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb addcma\0" \ - "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ - "rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "setenv bootargs; " \ - "run mmcargs; " \ - "run loadimage; " \ - "if run loadfdt; then " \ - "echo boot device tree kernel ...; " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "${boot_type}; " \ - "fi;\0" \ - "setenv bootargs \0" \ - "netdev=eth0\0" \ - "rootpath=/srv/nfs/tqma6\0" \ - "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb addcma\0" \ - "addnfs=setenv bootargs ${bootargs} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ - "addip_static=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test \"${ipmode}\" != static; then " \ - "run addip_dynamic; else run addip_static; fi\0" \ - "set_getcmd=if test \"${ipmode}\" != static; then " \ - "setenv getcmd dhcp; setenv autoload yes; " \ - "else setenv getcmd tftp; setenv autoload no; fi\0" \ - "netboot=echo Booting from net ...; " \ - "run kernel_name; " \ - "run set_getcmd; " \ - "setenv bootargs; " \ - "run netargs; " \ - "if ${getcmd} ${kernel}; then " \ - "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "fi; " \ - "fi; " \ - "echo ... failed\0" \ - "panicboot=echo No boot device !!! reset\0" \ - TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ +/* 16MiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_16M) */ +#define TQMA6_INITRD_ADDRESS 0x19000000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -265,19 +31,11 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* - * All the defines above are for the TQMa6 SoM - * - * Now include the baseboard specific configuration - */ -#ifdef CONFIG_MBA6 -#include "tqma6_mba6.h" -#elif CONFIG_WRU4 -#include "tqma6_wru4.h" -#else -#error "No baseboard for the TQMa6 defined!" -#endif +#define TQMA6_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6_MMC_UBOOT_SECTOR_COUNT 0x7fe -/* Support at least the sensor on TQMa6 SOM */ +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6_SPI_UBOOT_START 0x400 +#define TQMA6_SPI_UBOOT_SIZE 0xc0000 -#endif /* __CONFIG_H */ +#endif /* __TQMA6_CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 9b9f4150951..c30aeae4f29 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,9 +11,8 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CFG_FEC_MXC_PHYADDR 0x03 +#include "tqma6.h" #define CFG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 110bd895a8a..b35e471bd95 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_TQMA6_WRU4_H #define __CONFIG_TQMA6_WRU4_H +#include "tqma6.h" + /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0x01 diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h new file mode 100644 index 00000000000..ffbc1814f28 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang <[email protected]> + */ + +#ifndef _DT_BINDINGS_CLK_MT8189_H +#define _DT_BINDINGS_CLK_MT8189_H + +/* TOPCKGEN */ +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_AXI_PERI_SEL 1 +#define CLK_TOP_AXI_U_SEL 2 +#define CLK_TOP_BUS_AXIMEM_SEL 3 +#define CLK_TOP_DISP0_SEL 4 +#define CLK_TOP_MMINFRA_SEL 5 +#define CLK_TOP_UART_SEL 6 +#define CLK_TOP_SPI0_SEL 7 +#define CLK_TOP_SPI1_SEL 8 +#define CLK_TOP_SPI2_SEL 9 +#define CLK_TOP_SPI3_SEL 10 +#define CLK_TOP_SPI4_SEL 11 +#define CLK_TOP_SPI5_SEL 12 +#define CLK_TOP_MSDC_MACRO_0P_SEL 13 +#define CLK_TOP_MSDC50_0_HCLK_SEL 14 +#define CLK_TOP_MSDC50_0_SEL 15 +#define CLK_TOP_AES_MSDCFDE_SEL 16 +#define CLK_TOP_MSDC_MACRO_1P_SEL 17 +#define CLK_TOP_MSDC30_1_SEL 18 +#define CLK_TOP_MSDC30_1_HCLK_SEL 19 +#define CLK_TOP_MSDC_MACRO_2P_SEL 20 +#define CLK_TOP_MSDC30_2_SEL 21 +#define CLK_TOP_MSDC30_2_HCLK_SEL 22 +#define CLK_TOP_AUD_INTBUS_SEL 23 +#define CLK_TOP_ATB_SEL 24 +#define CLK_TOP_DISP_PWM_SEL 25 +#define CLK_TOP_USB_TOP_P0_SEL 26 +#define CLK_TOP_USB_XHCI_P0_SEL 27 +#define CLK_TOP_USB_TOP_P1_SEL 28 +#define CLK_TOP_USB_XHCI_P1_SEL 29 +#define CLK_TOP_USB_TOP_P2_SEL 30 +#define CLK_TOP_USB_XHCI_P2_SEL 31 +#define CLK_TOP_USB_TOP_P3_SEL 32 +#define CLK_TOP_USB_XHCI_P3_SEL 33 +#define CLK_TOP_USB_TOP_P4_SEL 34 +#define CLK_TOP_USB_XHCI_P4_SEL 35 +#define CLK_TOP_I2C_SEL 36 +#define CLK_TOP_SENINF_SEL 37 +#define CLK_TOP_SENINF1_SEL 38 +#define CLK_TOP_AUD_ENGEN1_SEL 39 +#define CLK_TOP_AUD_ENGEN2_SEL 40 +#define CLK_TOP_AES_UFSFDE_SEL 41 +#define CLK_TOP_U_SEL 42 +#define CLK_TOP_U_MBIST_SEL 43 +#define CLK_TOP_AUD_1_SEL 44 +#define CLK_TOP_AUD_2_SEL 45 +#define CLK_TOP_VENC_SEL 46 +#define CLK_TOP_VDEC_SEL 47 +#define CLK_TOP_PWM_SEL 48 +#define CLK_TOP_AUDIO_H_SEL 49 +#define CLK_TOP_MCUPM_SEL 50 +#define CLK_TOP_MEM_SUB_SEL 51 +#define CLK_TOP_MEM_SUB_PERI_SEL 52 +#define CLK_TOP_MEM_SUB_U_SEL 53 +#define CLK_TOP_EMI_N_SEL 54 +#define CLK_TOP_DSI_OCC_SEL 55 +#define CLK_TOP_AP2CONN_HOST_SEL 56 +#define CLK_TOP_IMG1_SEL 57 +#define CLK_TOP_IPE_SEL 58 +#define CLK_TOP_CAM_SEL 59 +#define CLK_TOP_CAMTM_SEL 60 +#define CLK_TOP_DSP_SEL 61 +#define CLK_TOP_SR_PKA_SEL 62 +#define CLK_TOP_DXCC_SEL 63 +#define CLK_TOP_MFG_REF_SEL 64 +#define CLK_TOP_MDP0_SEL 65 +#define CLK_TOP_DP_SEL 66 +#define CLK_TOP_EDP_SEL 67 +#define CLK_TOP_EDP_FAVT_SEL 68 +#define CLK_TOP_ETH_250M_SEL 69 +#define CLK_TOP_ETH_62P4M_PTP_SEL 70 +#define CLK_TOP_ETH_50M_RMII_SEL 71 +#define CLK_TOP_SFLASH_SEL 72 +#define CLK_TOP_GCPU_SEL 73 +#define CLK_TOP_MAC_TL_SEL 74 +#define CLK_TOP_VDSTX_DG_CTS_SEL 75 +#define CLK_TOP_PLL_DPIX_SEL 76 +#define CLK_TOP_ECC_SEL 77 +#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78 +#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79 +#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80 +#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81 +#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82 +#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83 +#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84 +#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85 +#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86 +#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87 +#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88 +#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89 +#define CLK_TOP_APLL_FMI2S_MCK_SEL 90 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91 +#define CLK_TOP_MFG_SEL_MFGPLL 92 +#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93 +#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96 +#define CLK_TOP_APLL12_CK_DIV_FMI2S 97 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99 +#define CLK_TOP_MAINPLL_D3 100 +#define CLK_TOP_MAINPLL_D4 101 +#define CLK_TOP_MAINPLL_D4_D2 102 +#define CLK_TOP_MAINPLL_D4_D4 103 +#define CLK_TOP_MAINPLL_D4_D8 104 +#define CLK_TOP_MAINPLL_D5 105 +#define CLK_TOP_MAINPLL_D5_D2 106 +#define CLK_TOP_MAINPLL_D5_D4 107 +#define CLK_TOP_MAINPLL_D5_D8 108 +#define CLK_TOP_MAINPLL_D6 109 +#define CLK_TOP_MAINPLL_D6_D2 110 +#define CLK_TOP_MAINPLL_D6_D4 111 +#define CLK_TOP_MAINPLL_D6_D8 112 +#define CLK_TOP_MAINPLL_D7 113 +#define CLK_TOP_MAINPLL_D7_D2 114 +#define CLK_TOP_MAINPLL_D7_D4 115 +#define CLK_TOP_MAINPLL_D7_D8 116 +#define CLK_TOP_MAINPLL_D9 117 +#define CLK_TOP_UNIVPLL_D2 118 +#define CLK_TOP_UNIVPLL_D3 119 +#define CLK_TOP_UNIVPLL_D4 120 +#define CLK_TOP_UNIVPLL_D4_D2 121 +#define CLK_TOP_UNIVPLL_D4_D4 122 +#define CLK_TOP_UNIVPLL_D4_D8 123 +#define CLK_TOP_UNIVPLL_D5 124 +#define CLK_TOP_UNIVPLL_D5_D2 125 +#define CLK_TOP_UNIVPLL_D5_D4 126 +#define CLK_TOP_UNIVPLL_D6 127 +#define CLK_TOP_UNIVPLL_D6_D2 128 +#define CLK_TOP_UNIVPLL_D6_D4 129 +#define CLK_TOP_UNIVPLL_D6_D8 130 +#define CLK_TOP_UNIVPLL_D6_D16 131 +#define CLK_TOP_UNIVPLL_D7 132 +#define CLK_TOP_UNIVPLL_D7_D2 133 +#define CLK_TOP_UNIVPLL_D7_D3 134 +#define CLK_TOP_LVDSTX_DG_CTS 135 +#define CLK_TOP_UNIVPLL_192M 136 +#define CLK_TOP_UNIVPLL_192M_D2 137 +#define CLK_TOP_UNIVPLL_192M_D4 138 +#define CLK_TOP_UNIVPLL_192M_D8 139 +#define CLK_TOP_UNIVPLL_192M_D10 140 +#define CLK_TOP_UNIVPLL_192M_D16 141 +#define CLK_TOP_UNIVPLL_192M_D32 142 +#define CLK_TOP_APLL1_D2 143 +#define CLK_TOP_APLL1_D4 144 +#define CLK_TOP_APLL1_D8 145 +#define CLK_TOP_APLL1_D3 146 +#define CLK_TOP_APLL2_D2 147 +#define CLK_TOP_APLL2_D4 148 +#define CLK_TOP_APLL2_D8 149 +#define CLK_TOP_APLL2_D3 150 +#define CLK_TOP_MMPLL_D4 151 +#define CLK_TOP_MMPLL_D4_D2 152 +#define CLK_TOP_MMPLL_D4_D4 153 +#define CLK_TOP_VPLL_DPIX 154 +#define CLK_TOP_MMPLL_D5 155 +#define CLK_TOP_MMPLL_D5_D2 156 +#define CLK_TOP_MMPLL_D5_D4 157 +#define CLK_TOP_MMPLL_D6 158 +#define CLK_TOP_MMPLL_D6_D2 159 +#define CLK_TOP_MMPLL_D7 160 +#define CLK_TOP_MMPLL_D9 161 +#define CLK_TOP_TVDPLL1_D2 162 +#define CLK_TOP_TVDPLL1_D4 163 +#define CLK_TOP_TVDPLL1_D8 164 +#define CLK_TOP_TVDPLL1_D16 165 +#define CLK_TOP_TVDPLL2_D2 166 +#define CLK_TOP_TVDPLL2_D4 167 +#define CLK_TOP_TVDPLL2_D8 168 +#define CLK_TOP_TVDPLL2_D16 169 +#define CLK_TOP_ETHPLL_D2 170 +#define CLK_TOP_ETHPLL_D8 171 +#define CLK_TOP_ETHPLL_D10 172 +#define CLK_TOP_MSDCPLL_D2 173 +#define CLK_TOP_VOWPLL 174 +#define CLK_TOP_UFSPLL_D2 175 +#define CLK_TOP_F26M_CK_D2 176 +#define CLK_TOP_OSC_D2 177 +#define CLK_TOP_OSC_D4 178 +#define CLK_TOP_OSC_D8 179 +#define CLK_TOP_OSC_D16 180 +#define CLK_TOP_OSC_D3 181 +#define CLK_TOP_OSC_D7 182 +#define CLK_TOP_OSC_D10 183 +#define CLK_TOP_OSC_D20 184 +#define CLK_TOP_FMCNT_P0_EN 185 +#define CLK_TOP_FMCNT_P1_EN 186 +#define CLK_TOP_FMCNT_P2_EN 187 +#define CLK_TOP_FMCNT_P3_EN 188 +#define CLK_TOP_FMCNT_P4_EN 189 +#define CLK_TOP_USB_F26M_CK_EN 190 +#define CLK_TOP_SSPXTP_F26M_CK_EN 191 +#define CLK_TOP_USB2_PHY_RF_P0_EN 192 +#define CLK_TOP_USB2_PHY_RF_P1_EN 193 +#define CLK_TOP_USB2_PHY_RF_P2_EN 194 +#define CLK_TOP_USB2_PHY_RF_P3_EN 195 +#define CLK_TOP_USB2_PHY_RF_P4_EN 196 +#define CLK_TOP_USB2_26M_CK_P0_EN 197 +#define CLK_TOP_USB2_26M_CK_P1_EN 198 +#define CLK_TOP_USB2_26M_CK_P2_EN 199 +#define CLK_TOP_USB2_26M_CK_P3_EN 200 +#define CLK_TOP_USB2_26M_CK_P4_EN 201 +#define CLK_TOP_F26M_CK_EN 202 +#define CLK_TOP_AP2CON_EN 203 +#define CLK_TOP_EINT_N_EN 204 +#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 205 +#define CLK_TOP_DRAMULP_CK_EN 206 +#define CLK_TOP_EINT_E_EN 207 +#define CLK_TOP_EINT_W_EN 208 +#define CLK_TOP_EINT_S_EN 209 + +/* INFRACFG_AO */ +#define CLK_IFRAO_CQ_DMA_FPC 0 +#define CLK_IFRAO_DEBUGSYS 1 +#define CLK_IFRAO_DBG_TRACE 2 +#define CLK_IFRAO_CQ_DMA 3 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MFGPLL 6 +#define CLK_APMIXED_APLL1 7 +#define CLK_APMIXED_APLL2 8 +#define CLK_APMIXED_EMIPLL 9 +#define CLK_APMIXED_APUPLL2 10 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_TVDPLL1 12 +#define CLK_APMIXED_TVDPLL2 13 +#define CLK_APMIXED_ETHPLL 14 +#define CLK_APMIXED_MSDCPLL 15 +#define CLK_APMIXED_UFSPLL 16 + +/* PERICFG_AO */ +#define CLK_PERAO_UART0 0 +#define CLK_PERAO_UART1 1 +#define CLK_PERAO_UART2 2 +#define CLK_PERAO_UART3 3 +#define CLK_PERAO_PWM_H 4 +#define CLK_PERAO_PWM_B 5 +#define CLK_PERAO_PWM_FB1 6 +#define CLK_PERAO_PWM_FB2 7 +#define CLK_PERAO_PWM_FB3 8 +#define CLK_PERAO_PWM_FB4 9 +#define CLK_PERAO_DISP_PWM0 10 +#define CLK_PERAO_DISP_PWM1 11 +#define CLK_PERAO_SPI0_B 12 +#define CLK_PERAO_SPI1_B 13 +#define CLK_PERAO_SPI2_B 14 +#define CLK_PERAO_SPI3_B 15 +#define CLK_PERAO_SPI4_B 16 +#define CLK_PERAO_SPI5_B 17 +#define CLK_PERAO_SPI0_H 18 +#define CLK_PERAO_SPI1_H 19 +#define CLK_PERAO_SPI2_H 20 +#define CLK_PERAO_SPI3_H 21 +#define CLK_PERAO_SPI4_H 22 +#define CLK_PERAO_SPI5_H 23 +#define CLK_PERAO_AXI 24 +#define CLK_PERAO_AHB_APB 25 +#define CLK_PERAO_TL 26 +#define CLK_PERAO_REF 27 +#define CLK_PERAO_I2C 28 +#define CLK_PERAO_DMA_B 29 +#define CLK_PERAO_SSUSB0_REF 30 +#define CLK_PERAO_SSUSB0_FRMCNT 31 +#define CLK_PERAO_SSUSB0_SYS 32 +#define CLK_PERAO_SSUSB0_XHCI 33 +#define CLK_PERAO_SSUSB0_F 34 +#define CLK_PERAO_SSUSB0_H 35 +#define CLK_PERAO_SSUSB1_REF 36 +#define CLK_PERAO_SSUSB1_FRMCNT 37 +#define CLK_PERAO_SSUSB1_SYS 38 +#define CLK_PERAO_SSUSB1_XHCI 39 +#define CLK_PERAO_SSUSB1_F 40 +#define CLK_PERAO_SSUSB1_H 41 +#define CLK_PERAO_SSUSB2_REF 42 +#define CLK_PERAO_SSUSB2_FRMCNT 43 +#define CLK_PERAO_SSUSB2_SYS 44 +#define CLK_PERAO_SSUSB2_XHCI 45 +#define CLK_PERAO_SSUSB2_F 46 +#define CLK_PERAO_SSUSB2_H 47 +#define CLK_PERAO_SSUSB3_REF 48 +#define CLK_PERAO_SSUSB3_FRMCNT 49 +#define CLK_PERAO_SSUSB3_SYS 50 +#define CLK_PERAO_SSUSB3_XHCI 51 +#define CLK_PERAO_SSUSB3_F 52 +#define CLK_PERAO_SSUSB3_H 53 +#define CLK_PERAO_SSUSB4_REF 54 +#define CLK_PERAO_SSUSB4_FRMCNT 55 +#define CLK_PERAO_SSUSB4_SYS 56 +#define CLK_PERAO_SSUSB4_XHCI 57 +#define CLK_PERAO_SSUSB4_F 58 +#define CLK_PERAO_SSUSB4_H 59 +#define CLK_PERAO_MSDC0 60 +#define CLK_PERAO_MSDC0_H 61 +#define CLK_PERAO_MSDC0_FAES 62 +#define CLK_PERAO_MSDC0_MST_F 63 +#define CLK_PERAO_MSDC0_SLV_H 64 +#define CLK_PERAO_MSDC1 65 +#define CLK_PERAO_MSDC1_H 66 +#define CLK_PERAO_MSDC1_MST_F 67 +#define CLK_PERAO_MSDC1_SLV_H 68 +#define CLK_PERAO_MSDC2 69 +#define CLK_PERAO_MSDC2_H 70 +#define CLK_PERAO_MSDC2_MST_F 71 +#define CLK_PERAO_MSDC2_SLV_H 72 +#define CLK_PERAO_SFLASH 73 +#define CLK_PERAO_SFLASH_F 74 +#define CLK_PERAO_SFLASH_H 75 +#define CLK_PERAO_SFLASH_P 76 +#define CLK_PERAO_AUDIO0 77 +#define CLK_PERAO_AUDIO1 78 +#define CLK_PERAO_AUDIO2 79 +#define CLK_PERAO_AUXADC_26M 80 + +/* UFSCFG_AO_REG */ +#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2 +#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3 +#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4 +#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5 + +/* UFSCFG_PDN_REG */ +#define CLK_UFSCFG_REG_UFSHCI_UFS 0 +#define CLK_UFSCFG_REG_UFSHCI_AES 1 +#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2 +#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3 + +/* IMP_IIC_WRAP_WS */ +#define CLK_IMPWS_I2C2 0 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C0 0 +#define CLK_IMPE_I2C1 1 + +/* IMP_IIC_WRAP_S */ +#define CLK_IMPS_I2C3 0 +#define CLK_IMPS_I2C4 1 +#define CLK_IMPS_I2C5 2 +#define CLK_IMPS_I2C6 3 + +/* IMP_IIC_WRAP_EN */ +#define CLK_IMPEN_I2C7 0 +#define CLK_IMPEN_I2C8 1 + +/* MFG */ +#define CLK_MFG_BG3D 0 + +/* DISPSYS_CONFIG */ +#define CLK_MM_DISP_OVL0_4L 0 +#define CLK_MM_DISP_OVL1_4L 1 +#define CLK_MM_VPP_RSZ0 2 +#define CLK_MM_VPP_RSZ1 3 +#define CLK_MM_DISP_RDMA0 4 +#define CLK_MM_DISP_RDMA1 5 +#define CLK_MM_DISP_COLOR0 6 +#define CLK_MM_DISP_COLOR1 7 +#define CLK_MM_DISP_CCORR0 8 +#define CLK_MM_DISP_CCORR1 9 +#define CLK_MM_DISP_CCORR2 10 +#define CLK_MM_DISP_CCORR3 11 +#define CLK_MM_DISP_AAL0 12 +#define CLK_MM_DISP_AAL1 13 +#define CLK_MM_DISP_GAMMA0 14 +#define CLK_MM_DISP_GAMMA1 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DISP_DITHER1 17 +#define CLK_MM_DISP_DSC_WRAP0 18 +#define CLK_MM_VPP_MERGE0 19 +#define CLK_MMSYS_0_DISP_DVO 20 +#define CLK_MMSYS_0_DISP_DSI0 21 +#define CLK_MM_DP_INTF0 22 +#define CLK_MM_DPI0 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_WDMA1 25 +#define CLK_MM_DISP_FAKE_ENG0 26 +#define CLK_MM_DISP_FAKE_ENG1 27 +#define CLK_MM_SMI_LARB 28 +#define CLK_MM_DISP_MUTEX0 29 +#define CLK_MM_DIPSYS_CONFIG 30 +#define CLK_MM_DUMMY 31 +#define CLK_MMSYS_1_DISP_DSI0 32 +#define CLK_MMSYS_1_LVDS_ENCODER 33 +#define CLK_MMSYS_1_DPI0 34 +#define CLK_MMSYS_1_DISP_DVO 35 +#define CLK_MM_DP_INTF 36 +#define CLK_MMSYS_1_LVDS_ENCODER_CTS 37 +#define CLK_MMSYS_1_DISP_DVO_AVT 38 + +/* IMGSYS1 */ +#define CLK_IMGSYS1_LARB9 0 +#define CLK_IMGSYS1_LARB11 1 +#define CLK_IMGSYS1_DIP 2 +#define CLK_IMGSYS1_GALS 3 + +/* IMGSYS2 */ +#define CLK_IMGSYS2_LARB9 0 +#define CLK_IMGSYS2_LARB11 1 +#define CLK_IMGSYS2_MFB 2 +#define CLK_IMGSYS2_WPE 3 +#define CLK_IMGSYS2_MSS 4 +#define CLK_IMGSYS2_GALS 5 + +/* VDEC_CORE */ +#define CLK_VDEC_CORE_LARB_CKEN 0 +#define CLK_VDEC_CORE_VDEC_CKEN 1 +#define CLK_VDEC_CORE_VDEC_ACTIVE 2 + +/* VENC_GCON */ +#define CLK_VEN1_CKE0_LARB 0 +#define CLK_VEN1_CKE1_VENC 1 +#define CLK_VEN1_CKE2_JPGENC 2 +#define CLK_VEN1_CKE3_JPGDEC 3 +#define CLK_VEN1_CKE4_JPGDEC_C1 4 +#define CLK_VEN1_CKE5_GALS 5 +#define CLK_VEN1_CKE6_GALS_SRAM 6 + +/* VLPCFG_REG */ +#define CLK_VLPCFG_REG_SCP 0 +#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1 +#define CLK_VLPCFG_REG_DPMSRCK_TEST 2 +#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3 +#define CLK_VLPCFG_REG_DPMSRULP_TEST 4 +#define CLK_VLPCFG_REG_SPMI_P_MST 5 +#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10 +#define CLK_VLPCFG_REG_DVFSRC 11 +#define CLK_VLPCFG_REG_PWM_VLP 12 +#define CLK_VLPCFG_REG_SRCK 13 +#define CLK_VLPCFG_REG_SSPM_F26M 14 +#define CLK_VLPCFG_REG_SSPM_F32K 15 +#define CLK_VLPCFG_REG_SSPM_ULPOSC 16 +#define CLK_VLPCFG_REG_VLP_32K_COM 17 +#define CLK_VLPCFG_REG_VLP_26M_COM 18 + +/* VLP_CKSYS */ +#define CLK_VLP_CK_SCP_SEL 0 +#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1 +#define CLK_VLP_CK_SPMI_P_MST_SEL 2 +#define CLK_VLP_CK_DVFSRC_SEL 3 +#define CLK_VLP_CK_PWM_VLP_SEL 4 +#define CLK_VLP_CK_AXI_VLP_SEL 5 +#define CLK_VLP_CK_SYSTIMER_26M_SEL 6 +#define CLK_VLP_CK_SSPM_SEL 7 +#define CLK_VLP_CK_SSPM_F26M_SEL 8 +#define CLK_VLP_CK_SRCK_SEL 9 +#define CLK_VLP_CK_SCP_SPI_SEL 10 +#define CLK_VLP_CK_SCP_IIC_SEL 11 +#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12 +#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13 +#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14 +#define CLK_VLP_CK_APXGPT_26M_SEL 15 +#define CLK_VLP_CK_VADSP_SEL 16 +#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17 +#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18 +#define CLK_VLP_CK_CAMTG0_SEL 19 +#define CLK_VLP_CK_CAMTG1_SEL 20 +#define CLK_VLP_CK_CAMTG2_SEL 21 +#define CLK_VLP_CK_AUD_ADC_SEL 22 +#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23 +#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24 +#define CLK_VLP_CK_SEJ_13M_EN 25 +#define CLK_VLP_CK_SEJ_26M_EN 26 +#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 27 + +/* SCP_IIC */ +#define CLK_SCP_IIC_I2C0_W1S 0 +#define CLK_SCP_IIC_I2C1_W1S 1 + +/* SCP */ +#define CLK_SCP_SET_SPI0 0 +#define CLK_SCP_SET_SPI1 1 + +/* CAMSYS_MAIN */ +#define CLK_CAM_M_LARB13 0 +#define CLK_CAM_M_LARB14 1 +#define CLK_CAM_M_CAMSYS_MAIN_CAM 2 +#define CLK_CAM_M_CAMSYS_MAIN_CAMTG 3 +#define CLK_CAM_M_SENINF 4 +#define CLK_CAM_M_CAMSV1 5 +#define CLK_CAM_M_CAMSV2 6 +#define CLK_CAM_M_CAMSV3 7 +#define CLK_CAM_M_FAKE_ENG 8 +#define CLK_CAM_M_CAM2MM_GALS 9 +#define CLK_CAM_M_CAMSV4 10 +#define CLK_CAM_M_PDA 11 + +/* CAMSYS_RAWA */ +#define CLK_CAM_RA_CAMSYS_RAWA_LARBX 0 +#define CLK_CAM_RA_CAMSYS_RAWA_CAM 1 +#define CLK_CAM_RA_CAMSYS_RAWA_CAMTG 2 + +/* CAMSYS_RAWB */ +#define CLK_CAM_RB_CAMSYS_RAWB_LARBX 0 +#define CLK_CAM_RB_CAMSYS_RAWB_CAM 1 +#define CLK_CAM_RB_CAMSYS_RAWB_CAMTG 2 + +/* IPESYS */ +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPESYS_GALS 6 + +/* VLPCFG_AO_REG */ +#define CLK_VLPCFG_AO_APEINT_RX 0 + +/* DVFSRC_TOP */ +#define CLK_DVFSRC_TOP_DVFSRC_EN 0 + +/* MMINFRA_CONFIG */ +#define CLK_MMINFRA_GCE_D 0 +#define CLK_MMINFRA_GCE_M 1 +#define CLK_MMINFRA_SMI 2 +#define CLK_MMINFRA_GCE_26M 3 + +/* GCE_D */ +#define CLK_GCE_D_TOP 0 + +/* GCE_M */ +#define CLK_GCE_M_TOP 0 + +/* MDPSYS_CONFIG */ +#define CLK_MDP_MUTEX0 0 +#define CLK_MDP_APB_BUS 1 +#define CLK_MDP_SMI0 2 +#define CLK_MDP_RDMA0 3 +#define CLK_MDP_RDMA2 4 +#define CLK_MDP_HDR0 5 +#define CLK_MDP_AAL0 6 +#define CLK_MDP_RSZ0 7 +#define CLK_MDP_TDSHP0 8 +#define CLK_MDP_COLOR0 9 +#define CLK_MDP_WROT0 10 +#define CLK_MDP_FAKE_ENG0 11 +#define CLK_MDPSYS_CONFIG 12 +#define CLK_MDP_RDMA1 13 +#define CLK_MDP_RDMA3 14 +#define CLK_MDP_HDR1 15 +#define CLK_MDP_AAL1 16 +#define CLK_MDP_RSZ1 17 +#define CLK_MDP_TDSHP1 18 +#define CLK_MDP_COLOR1 19 +#define CLK_MDP_WROT1 20 +#define CLK_MDP_RSZ2 21 +#define CLK_MDP_WROT2 22 +#define CLK_MDP_RSZ3 23 +#define CLK_MDP_WROT3 24 +#define CLK_MDP_BIRSZ0 25 +#define CLK_MDP_BIRSZ1 26 + +/* DBGAO */ +#define CLK_DBGAO_ATB_EN 0 + +/* DEM */ +#define CLK_DEM_ATB_EN 0 +#define CLK_DEM_BUSCLK_EN 1 +#define CLK_DEM_SYSCLK_EN 2 + +#endif /* _DT_BINDINGS_CLK_MT8189_H */ diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h deleted file mode 100644 index 6a0b70a37d7..00000000000 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018-2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 3e70ac07055..3a4d502631c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -387,6 +387,10 @@ extern const efi_guid_t efi_guid_capsule_report; extern const efi_guid_t efi_guid_firmware_management_protocol; /* GUID for the ESRT */ extern const efi_guid_t efi_esrt_guid; +/* GUID for the ECPT */ +#if CONFIG_IS_ENABLED(EFI_ECPT) +extern const efi_guid_t efi_ecpt_guid; +#endif /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; extern const efi_guid_t smbios3_guid; @@ -1144,6 +1148,9 @@ struct pkcs7_message *efi_parse_pkcs7_header(const void *buf, /* runtime implementation of memcpy() */ void efi_memcpy_runtime(void *dest, const void *src, size_t n); +/* runtime implementation of memcmp() */ +int efi_memcmp_runtime(const void *s1, const void *s2, size_t n); + /* commonly used helper functions */ u16 *efi_create_indexed_name(u16 *buffer, size_t buffer_size, const char *name, unsigned int index); diff --git a/include/efi_variable.h b/include/efi_variable.h index 4065cf45eca..c3229c717d8 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -137,13 +137,11 @@ struct efi_var_file { }; /** - * efi_var_to_file() - save non-volatile variables as file - * - * File ubootefi.var is created on the EFI system partion. + * efi_var_to_storage() - save non-volatile variables * * Return: status code */ -efi_status_t efi_var_to_file(void); +efi_status_t efi_var_to_storage(void); /** * efi_var_collect() - collect variables in buffer @@ -161,6 +159,11 @@ efi_status_t efi_var_to_file(void); efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, u32 check_attr_mask); +/* GUID used by Shim to store the MOK database */ +#define SHIM_LOCK_GUID \ + EFI_GUID(0x605dab50, 0xe046, 0x4300, \ + 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) + /** * efi_var_restore() - restore EFI variables from buffer * @@ -173,17 +176,14 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe); /** - * efi_var_from_file() - read variables from file - * - * File ubootefi.var is read from the EFI system partitions and the variables - * stored in the file are created. + * efi_var_from_storage() - read variables * * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS * is returned. * * Return: status code */ -efi_status_t efi_var_from_file(void); +efi_status_t efi_var_from_storage(void); /** * efi_var_mem_init() - set-up variable list @@ -216,6 +216,11 @@ void efi_var_mem_del(struct efi_var_entry *var); * The variable is appended without checking if a variable of the same name * already exists. The two data buffers are concatenated. * + * When @changep is non-NULL and @size2 is 0, the function compares the new + * value against an existing variable with the same name and vendor. If + * attributes and data are identical the insertion is skipped and *@changep + * is set to false, avoiding superfluous writes. + * * @variable_name: variable name * @vendor: GUID * @attributes: variable attributes @@ -224,13 +229,14 @@ void efi_var_mem_del(struct efi_var_entry *var); * @size2: size of the second data field * @data2: second data buffer * @time: time of authentication (as seconds since start of epoch) + * @changep: pointer to change flag (may be NULL) * Result: status code */ efi_status_t efi_var_mem_ins(const u16 *variable_name, const efi_guid_t *vendor, u32 attributes, const efi_uintn_t size1, const void *data1, const efi_uintn_t size2, const void *data2, - const u64 time); + const u64 time, bool *changep); /** * efi_var_mem_free() - determine free memory for variables diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index a0ed83f52ac..62b93eb25c4 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -24,12 +24,10 @@ get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run init_${boot}; -#if CONFIG_CMD_REMOTEPROC - if env exists do_main_cpsw0_qsgmii_phyinit; - then run main_cpsw0_qsgmii_phyinit; + if test -n ${board_init}; then + echo Running board_init ...; + run board_init; fi; - run boot_rprocs; -#endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; else; diff --git a/include/env/tq/mmc.env b/include/env/tq/mmc.env new file mode 100644 index 00000000000..abf561f8467 --- /dev/null +++ b/include/env/tq/mmc.env @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared mmc environment for TQ boards + */ + +addmmc= + setenv bootargs "${bootargs}" + root=/dev/mmcblk"${mmcblkdev}"p"${mmcrootpart}" "${rootfsmode}" rootwait; + +get_blockcount= + setexpr blkc "${filesize}" + 0x1ff; + setexpr blkc "${blkc}" / 0x200; + +load_mmc= + mmc dev "${mmcdev}"; mmc rescan; + load mmc "${mmcdev}":"${mmcpart}" "${kernel_addr_r}" /boot/"${image}"; + load mmc "${mmcdev}":"${mmcpart}" "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + load mmc "${mmcdev}":"${mmcpart}" "${fdtoverlay_addr_r}" + /boot/"${overlay}" && fdt apply "${fdtoverlay_addr_r}"; + done; + +mmcargs=run addtty addmmc + +mmcboot= + echo "Booting from mmc ..."; + setenv bootargs && run mmcargs && + if run load_mmc; then + run boot_os; + else + echo "ERROR: loading from mmc"; + fi; + +mmcpart=2 + +mmc_finish_update_uboot= + mmc write "${loadaddr}" "${update_start_blk}" "${blkc}"; + mmc dev "${mmcdev}" 0; + setenv update_part; + setenv update_start_blk; + setenv blkc; + +mmc_prepare_update_uboot= + echo "Write U-Boot to mmc "${mmcdev}" ..."; + mmc dev "${mmcdev}"; mmc rescan; + run get_blockcount; + setenv update_start_blk "${uboot_mmc_start}"; + setenv update_part 0; + +mmc_switch_part= + mmc partconf "${mmcdev}" update_part; + mmc dev "${mmcdev}" "${update_part}"; + +mmcrootpart=2 + +update_uboot_mmc= + run check_ipaddr; + if tftp "${uboot}"; then + run mmc_prepare_update_uboot; + if itest "${blkc}" >= "${uboot_mmc_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + if itest "${mmcdev}" == "${emmc_dev}"; then + run mmc_switch_part; + if itest "${update_part}" > 0 ; then + if env exists emmc_bootp_start; then + setenv update_start_blk "${emmc_bootp_start}"; + else + echo "ERROR: eMMC boot partition block unset"; + exit; + fi; + fi; + fi; + run mmc_finish_update_uboot; + fi; diff --git a/include/env/tq/nfs.env b/include/env/tq/nfs.env new file mode 100644 index 00000000000..53fcbd0d152 --- /dev/null +++ b/include/env/tq/nfs.env @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared nfs environment for TQ boards + */ + +addnfs= + setenv bootargs "${bootargs}" root=/dev/nfs rw + nfsroot="${serverip}":"${rootpath}",v3,tcp + +load_nfs= + nfs "${kernel_addr_r}" "${serverip}":"${rootpath}"/boot/"${image}"; + nfs "${fdt_addr_r}" "${serverip}":"${rootpath}"/boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + nfs "${fdtoverlay_addr_r}" + "${serverip}":"${rootpath}"/boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + +load_tftp= + tftp "${kernel_addr_r}" "${image}"; + tftp "${fdt_addr_r}" "${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + if tftp "${fdtoverlay_addr_r}" "${overlay}"; then + fdt apply "${fdtoverlay_addr_r}"; + else + exit; + fi; + done; + +netargs=run addnfs addip addtty + +netloadcmd=load_tftp + +nfsboot= + echo "Booting from NFS ..."; + setenv bootargs; + run netargs; + run check_ipaddr; + if run ${netloadcmd}; then + run boot_os; + else + echo "ERROR: loading from NFS"; + fi; diff --git a/include/env/tq/spi.env b/include/env/tq/spi.env new file mode 100644 index 00000000000..47dcfea7d3f --- /dev/null +++ b/include/env/tq/spi.env @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared spi environment for TQ boards + */ + +update_uboot_spi= + run check_ipaddr; + if tftp ${uboot}; then + if itest "${filesize}" >= "${uboot_spi_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + echo "Write u-boot image to SPI NOR ..."; + if sf probe; then + run write_uboot_spi; + fi; + fi; + +write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}" diff --git a/include/env/tq/tq-imx-shared.env b/include/env/tq/tq-imx-shared.env new file mode 100644 index 00000000000..d4e42f8b536 --- /dev/null +++ b/include/env/tq/tq-imx-shared.env @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared environment for TQ imx boards + */ + +#ifdef CONFIG_CMD_SF +#include "spi.env" +#ifdef CONFIG_CMD_UBIFS +#include "ubi.env" +#endif /* CONFIG_CMD_UBIFS */ +#endif /* CONFIG_CMD_SF */ + +#ifdef CONFIG_CMD_MMC +#include "mmc.env" +#endif + +#ifdef CONFIG_CMD_NFS +#include "nfs.env" +#endif + +addip= + run check_ipaddr; + setenv bootargs "${bootargs}" + ip="${ipaddr}":"${serverip}":"${gatewayip}":"${netmask}":"${hostname}":"${netdev}":off + +addtty=setenv bootargs "${bootargs}" "${console}" + +check_ipaddr= + if test -z "${ipaddr}" || test -z "${serverip}"; then + echo "ipaddr or serverip unset, falling back to DHCP..."; + dhcp; + fi; + +rootfsmode=ro diff --git a/include/env/tq/ubi.env b/include/env/tq/ubi.env new file mode 100644 index 00000000000..01243d2eb53 --- /dev/null +++ b/include/env/tq/ubi.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared ubi environment for TQ boards + */ + +addubi= + setenv bootargs "${bootargs}" rootfstype=ubifs ubi.mtd="${ubimtdname}" + root=ubi0:"${ubirootfsvol}" "${rootfsmode}" rootwait; + +load_spi= + if sf probe; then + if ubi part "${ubirootfspart}"; then + if ubifsmount ubi0:"${ubirootfsvol}"; then + ubifsload "${kernel_addr_r}" /boot/"${image}"; + ubifsload "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + ubifsload "${fdtoverlay_addr_r}" + /boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + ubifsumount; + fi; + ubi detach; + fi; + fi + +ubiargs=run addubi addtty + +ubiboot= + echo "Booting from UBI ..."; + setenv bootargs; + run ubiargs; + if run load_spi; then + run boot_os; + else + echo "ERROR: loading kernel"; + fi; + +ubimtdname=mtdname +ubirootfspart=ubi +ubirootfsvol=root diff --git a/include/exception.h b/include/exception.h index a7f21e73d75..0d4dff49954 100644 --- a/include/exception.h +++ b/include/exception.h @@ -6,6 +6,7 @@ */ #include <command.h> +#include <string.h> static int do_exception(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/include/fat.h b/include/fat.h index bdf430f7067..40da0370a44 100644 --- a/include/fat.h +++ b/include/fat.h @@ -165,7 +165,9 @@ typedef struct { int fatsize; /* Size of FAT in bits */ __u32 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ +#ifdef CONFIG_FAT_WRITE __u8 fat_dirty; /* Set if fatbuf has been modified */ +#endif __u32 rootdir_sect; /* Start sector of root directory */ __u16 sect_size; /* Size of sectors in bytes */ __u16 clust_size; /* Size of clusters in sectors */ @@ -190,6 +192,30 @@ static inline u32 sect_to_clust(fsdata *fsdata, int sect) return (sect - fsdata->data_begin) / fsdata->clust_size; } +static inline void fat_mark_clean(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 0; +#endif +} + +static inline void fat_mark_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 1; +#endif +} + +static inline bool fat_is_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + if (fsdata->fat_dirty) + return true; +#endif + + return false; +} + int file_fat_detectfs(void); int fat_exists(const char *filename); int fat_size(const char *filename, loff_t *size); diff --git a/include/fdtdec.h b/include/fdtdec.h index d9fcd037ed2..4e09f9d718c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -16,6 +16,7 @@ #include <linux/libfdt.h> #include <pci.h> +#include <dm/ofnode_decl.h> /* * Support for 64bit fdt addresses. @@ -199,6 +200,29 @@ struct fdtdec_phandle_args { }; /** + * fdtdec_get_next_memory_node() - Get the next enabled memory node from device tree + * + * @mem: Current memory node to start search from, or ofnode_null() to get first node + * + * This function iterates through device tree nodes with device_type = "memory" + * property, automatically skipping disabled nodes (status != "okay"). + * + * It is used to enumerate multiple memory regions when the system has + * non-contiguous or multiple memory banks defined in the device tree. + * The function continues searching from the given node onwards, looking + * for the next node with the "memory" device_type property and checking + * its status property. + * + * Can be called multiple times to iterate through all memory nodes. + * Pass ofnode_null() on first call, then pass the returned node + * on subsequent calls until an invalid node is returned. + * + * Return: Next valid, enabled memory ofnode, or invalid ofnode if no more + * memory nodes exist + */ +ofnode fdtdec_get_next_memory_node(ofnode mem); + +/** * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list * * This function is useful to parse lists of phandles and their arguments. diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 876d52cac35..7f4ca735663 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -86,6 +86,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val); void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); diff --git a/include/fwu.h b/include/fwu.h index e7bd1d492af..9cee8fb085c 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -80,9 +80,11 @@ struct fwu_mdata_ops { #define FWU_IMAGE_ACCEPTED 0x1 -#define FWU_BANK_INVALID (uint8_t)0xFF -#define FWU_BANK_VALID (uint8_t)0xFE -#define FWU_BANK_ACCEPTED (uint8_t)0xFC +enum fwu_bank_states { + FWU_BANK_INVALID = 0xFF, + FWU_BANK_VALID = 0xFE, + FWU_BANK_ACCEPTED = 0xFC, +}; enum { PRIMARY_PART = 1, @@ -396,24 +398,24 @@ int fwu_get_mdata_size(uint32_t *mdata_size); /** * fwu_state_machine_updates() - Update FWU state of the platform - * @trial_state: Is platform transitioning into Trial State + * @state: FWU bank state * @update_index: Bank number to which images have been updated * - * On successful completion of updates, transition the platform to - * either Trial State or Regular State. + * FWU_BANK_VALID transition the platform to Trial state + * FWU_BANK_ACCEPTED accept the FWU bank state + * FWU_BANK_INVALID invalid the FWU bank state * * To transition the platform to Trial State, start the * TrialStateCtr counter, followed by setting the value of bank_state * field of the metadata to Valid state(applicable only in version 2 * of metadata). * - * In case, the platform is to transition directly to Regular State, - * update the bank_state field of the metadata to Accepted - * state(applicable only in version 2 of metadata). + * Saving the bank_state field of the metadata is only applicable in + * version 2 of metadata. * * Return: 0 if OK, -ve on error */ -int fwu_state_machine_updates(bool trial_state, uint32_t update_index); +int fwu_state_machine_updates(enum fwu_bank_states state, uint32_t update_index); /** * fwu_init() - FWU specific initialisations diff --git a/include/linker_lists.h b/include/linker_lists.h index 0f4a2d686e2..78ba937c8c3 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -288,56 +288,6 @@ #define ll_entry_ref(_type, _name, _list) \ ((_type *)&_u_boot_list_2_##_list##_2_##_name) -/** - * ll_start() - Point to first entry of first linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer to the very first entry of - * the very first linker-generated array. - * - * Since this macro defines the start of the linker-generated arrays, - * its leftmost index must be 1. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd); - */ -#define ll_start(_type) \ -({ \ - static char start[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_1"); \ - _type * tmp = (_type *)&start; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - -/** - * ll_end() - Point after last entry of last linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer after the very last entry of - * the very last linker-generated array. - * - * Since this macro defines the end of the linker-generated arrays, - * its leftmost index must be 3. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd); - */ -#define ll_end(_type) \ -({ \ - static char end[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_3"); \ - _type * tmp = (_type *)&end; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - #endif /* __ASSEMBLY__ */ #endif /* __LINKER_LISTS_H__ */ diff --git a/include/mmc.h b/include/mmc.h index 51d3f2f8dd5..9509c9e9543 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -54,6 +54,7 @@ struct bd_info; #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) +#define MMC_VERSION_5_1B MAKE_MMC_VERSION(5, 1, 0xB) #define MMC_CAP(mode) (1 << mode) #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) diff --git a/include/part.h b/include/part.h index daebbbc2e68..15daacd7faa 100644 --- a/include/part.h +++ b/include/part.h @@ -461,6 +461,7 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); #ifdef CONFIG_XPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ + defined(CONFIG_SPL_FS_SQUASHFS) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) # define part_get_info_ptr(x) x @@ -704,6 +705,20 @@ int write_mbr_partitions(struct blk_desc *dev, int layout_mbr_partitions(struct disk_partition *p, int count, lbaint_t total_sectors); +/** + * part_get_mbr() - get the MBR partition record of a partition + * + * This function reads the MBR partition record for a given block + * device and partition number. + * + * @desc: block device descriptor + * @part: partition number for which to return the partition record + * @mbr: MBR partition record + * + * Return: 0 on success, otherwise error + */ +int part_get_mbr(struct blk_desc *desc, int part, dos_partition_t *mbr); + #endif #if CONFIG_IS_ENABLED(PARTITIONS) diff --git a/include/part_dos.h b/include/part_dos.h new file mode 100644 index 00000000000..92956d53063 --- /dev/null +++ b/include/part_dos.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, [email protected]. + */ + +#ifndef _DISK_PART_DOS_H +#define _DISK_PART_DOS_H + +#define DOS_PART_DISKSIG_OFFSET 0x1b8 +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR32_FSTYPE_OFFSET 0x52 +#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 +#define DOS_MBR 0 +#define DOS_PBR 1 +#define DOS_PART_TYPE_EXTENDED 0x05 +#define DOS_PART_TYPE_EXTENDED_LBA 0x0F +#define DOS_PART_TYPE_EXTENDED_LINUX 0x85 + +#define DOS_PART_DEFAULT_GAP 2048 + +typedef struct dos_partition { + unsigned char boot_ind; /* 0x80 - active */ + unsigned char head; /* starting head */ + unsigned char sector; /* starting sector */ + unsigned char cyl; /* starting cylinder */ + unsigned char sys_ind; /* What partition type */ + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ + __le32 start_sect; /* starting sector counting from 0 */ + __le32 nr_sects; /* nr of sectors in partition */ +} __packed dos_partition_t; + +#endif /* _DISK_PART_DOS_H */ diff --git a/include/part_efi.h b/include/part_efi.h index fb402df6f13..2cea5088046 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -18,6 +18,7 @@ #define _DISK_PART_EFI_H #include <efi.h> +#include <part_dos.h> #define MSDOS_MBR_SIGNATURE 0xAA55 #define MSDOS_MBR_BOOT_CODE_SIZE 440 @@ -77,20 +78,6 @@ /* linux/include/efi.h */ typedef u16 efi_char16_t; -/* based on linux/include/genhd.h */ -struct partition { - u8 boot_ind; /* 0x80 - active */ - u8 head; /* starting head */ - u8 sector; /* starting sector */ - u8 cyl; /* starting cylinder */ - u8 sys_ind; /* What partition type */ - u8 end_head; /* end head */ - u8 end_sector; /* end sector */ - u8 end_cyl; /* end cylinder */ - __le32 start_sect; /* starting sector counting from 0 */ - __le32 nr_sects; /* nr of sectors in partition */ -} __packed; - /* based on linux/fs/partitions/efi.h */ typedef struct _gpt_header { __le64 signature; @@ -134,7 +121,7 @@ typedef struct _legacy_mbr { u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; __le32 unique_mbr_signature; __le16 unknown; - struct partition partition_record[4]; + dos_partition_t partition_record[4]; __le16 signature; } __packed legacy_mbr; @@ -153,7 +140,7 @@ struct efi_partition_info { u8 system; u8 reserved[7]; union { - struct partition mbr; + dos_partition_t mbr; gpt_entry gpt; } info; } __packed; diff --git a/include/power/cpcap.h b/include/power/cpcap.h index bb0e28cec55..b035b84840f 100644 --- a/include/power/cpcap.h +++ b/include/power/cpcap.h @@ -297,32 +297,21 @@ static const char * const cpcap_regulator_to_name[] = { }; static const u32 unknown_val_tbl[] = { 0, }; -static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, - 812500, 825000, 837500, 850000, 862500, - 875000, 887500, 900000, 912500, 925000, - 937500, 950000, 962500, 975000, 987500, - 1000000, 1012500, 1025000, 1037500, - 1050000, 1062500, 1075000, 1087500, - 1100000, 1112500, 1125000, 1137500, - 1150000, 1162500, 1175000, 1187500, - 1200000, 1212500, 1225000, 1237500, - 1250000, 1262500, 1275000, 1287500, - 1300000, 1312500, 1325000, 1337500, - 1350000, 1362500, 1375000, 1387500, - 1400000, 1412500, 1425000, 1437500, - 1450000, 1462500, 1475000 }; -static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, - 962500, 975000, 987500, 1000000, 1012500, - 1025000, 1037500, 1050000, 1062500, - 1075000, 1087500, 1100000, 1112500, - 1125000, 1137500, 1150000, 1162500, - 1175000, 1187500, 1200000, 1212500, - 1225000, 1237500, 1250000, 1262500, - 1275000, 1287500, 1300000, 1312500, - 1325000, 1337500, 1350000, 1362500, - 1375000, 1387500, 1400000, 1412500, - 1425000, 1437500, 1450000, 1462500, - 1475000 }; +static const u32 sw_val_tbl[] = { 600000, 612500, 625000, 637500, 650000, + 662500, 675000, 687500, 700000, 712500, + 725000, 737500, 750000, 762500, 775000, + 787500, 800000, 812500, 825000, 837500, + 850000, 862500, 875000, 887500, 900000, + 912500, 925000, 937500, 950000, 962500, + 975000, 987500, 1000000, 1012500, 1025000, + 1037500, 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, 1150000, + 1162500, 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, 1275000, + 1287500, 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, 1400000, + 1412500, 1425000, 1437500, 1450000, 1462500, + 1475000, }; static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; static const u32 sw5_val_tbl[] = { 0, 5050000 }; static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; @@ -361,13 +350,6 @@ struct cpcap_regulator_data { u32 mode_cntr; u32 volt_trans_time; /* in micro seconds */ u32 turn_on_time; /* in micro seconds */ - - /* - * Bit difference between lowest value in val_tbl and start of voltage - * table setting in cpcap. Use this for switchers that have many too - * many voltages to list in val_tbl. - */ - u32 bit_offset_from_cpcap_lowest_voltage; }; #endif /* _CPCAP_H_ */ diff --git a/include/power/mt6357.h b/include/power/mt6357.h new file mode 100644 index 00000000000..b7ee9d64386 --- /dev/null +++ b/include/power/mt6357.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson <[email protected]> + */ + +#ifndef _REGULATOR_MT6357_H_ +#define _REGULATOR_MT6357_H_ + +#define MT6357_REGULATOR_DRIVER "mt6357_regulator" + +enum { + /* Bucks */ + MT6357_ID_VCORE, + MT6357_ID_VMODEM, + MT6357_ID_VPA, + MT6357_ID_VPROC, + MT6357_ID_VS1, + + /* LDOs */ + MT6357_ID_VAUX18, + MT6357_ID_VAUD28, + MT6357_ID_VCAMA, + MT6357_ID_VCAMD, + MT6357_ID_VCAMIO, + MT6357_ID_VCN18, + MT6357_ID_VCN28, + MT6357_ID_VCN33_BT, + MT6357_ID_VCN33_WIFI, + MT6357_ID_VDRAM, + MT6357_ID_VEFUSE, + MT6357_ID_VEMC, + MT6357_ID_VFE28, + MT6357_ID_VIBR, + MT6357_ID_VIO18, + MT6357_ID_VIO28, + MT6357_ID_VLDO28, + MT6357_ID_VMC, + MT6357_ID_VMCH, + MT6357_ID_VRF12, + MT6357_ID_VRF18, + MT6357_ID_VSIM1, + MT6357_ID_VSIM2, + MT6357_ID_VSRAM_OTHERS, + MT6357_ID_VSRAM_PROC, + MT6357_ID_VUSB33, + MT6357_ID_VXO22, +}; + +/* PMIC Registers */ +#define MT6357_BUCK_TOP_CLK_CON0 0x140c +#define MT6357_BUCK_TOP_CLK_HWEN_CON0 0x1412 +#define MT6357_BUCK_TOP_CLK_MISC_CON0 0x1418 +#define MT6357_BUCK_TOP_INT_CON0 0x141a +#define MT6357_BUCK_TOP_INT_MASK_CON0 0x1420 +#define MT6357_BUCK_TOP_SLP_CON0 0x142c +#define MT6357_BUCK_TOP_OC_CON0 0x1434 +#define MT6357_BUCK_TOP_K_CON0 0x1436 +#define MT6357_BUCK_VPROC_CON0 0x1488 +#define MT6357_BUCK_VPROC_DBG0 0x14a2 +#define MT6357_BUCK_VPROC_ELR0 0x14aa +#define MT6357_BUCK_VCORE_CON0 0x1508 +#define MT6357_BUCK_VCORE_DBG0 0x1522 +#define MT6357_BUCK_VCORE_ELR0 0x152a +#define MT6357_BUCK_VMODEM_CON0 0x1588 +#define MT6357_BUCK_VMODEM_DBG0 0x15a2 +#define MT6357_BUCK_VMODEM_ELR0 0x15aa +#define MT6357_BUCK_VS1_CON0 0x1608 +#define MT6357_BUCK_VS1_DBG0 0x1622 +#define MT6357_BUCK_VS1_ELR0 0x1632 +#define MT6357_BUCK_VPA_CON0 0x1688 +#define MT6357_BUCK_VPA_CON1 0x168a +#define MT6357_BUCK_VPA_DBG0 0x1692 +#define MT6357_BUCK_VPA_DLC_CON0 0x1698 +#define MT6357_BUCK_VPA_MSFG_CON0 0x169e +#define MT6357_LDO_TOP_CLK_DCM_CON0 0x188c +#define MT6357_LDO_TOP_CLK_VIO28_CON0 0x188e +#define MT6357_LDO_TOP_CLK_VIO18_CON0 0x1890 +#define MT6357_LDO_TOP_CLK_VAUD28_CON0 0x1892 +#define MT6357_LDO_TOP_CLK_VDRAM_CON0 0x1894 +#define MT6357_LDO_TOP_CLK_VSRAM_PROC_CON0 0x1896 +#define MT6357_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1898 +#define MT6357_LDO_TOP_CLK_VAUX18_CON0 0x189a +#define MT6357_LDO_TOP_CLK_VUSB33_CON0 0x189c +#define MT6357_LDO_TOP_CLK_VEMC_CON0 0x189e +#define MT6357_LDO_TOP_CLK_VXO22_CON0 0x18a0 +#define MT6357_LDO_TOP_CLK_VSIM1_CON0 0x18a2 +#define MT6357_LDO_TOP_CLK_VSIM2_CON0 0x18a4 +#define MT6357_LDO_TOP_CLK_VCAMD_CON0 0x18a6 +#define MT6357_LDO_TOP_CLK_VCAMIO_CON0 0x18a8 +#define MT6357_LDO_TOP_CLK_VEFUSE_CON0 0x18aa +#define MT6357_LDO_TOP_CLK_VCN33_CON0 0x18ac +#define MT6357_LDO_TOP_CLK_VCN18_CON0 0x18ae +#define MT6357_LDO_TOP_CLK_VCN28_CON0 0x18b0 +#define MT6357_LDO_TOP_CLK_VIBR_CON0 0x18b2 +#define MT6357_LDO_TOP_CLK_VFE28_CON0 0x18b4 +#define MT6357_LDO_TOP_CLK_VMCH_CON0 0x18b6 +#define MT6357_LDO_TOP_CLK_VMC_CON0 0x18b8 +#define MT6357_LDO_TOP_CLK_VRF18_CON0 0x18ba +#define MT6357_LDO_TOP_CLK_VLDO28_CON0 0x18bc +#define MT6357_LDO_TOP_CLK_VRF12_CON0 0x18be +#define MT6357_LDO_TOP_CLK_VCAMA_CON0 0x18c0 +#define MT6357_LDO_TOP_CLK_TREF_CON0 0x18c2 +#define MT6357_LDO_TOP_INT_CON0 0x18c4 +#define MT6357_LDO_TOP_INT_MASK_CON0 0x18d0 +#define MT6357_LDO_TEST_CON0 0x18e4 +#define MT6357_LDO_TOP_WDT_CON0 0x18e6 +#define MT6357_LDO_TOP_RSV_CON0 0x18e8 +#define MT6357_LDO_VXO22_CON0 0x1908 +#define MT6357_LDO_VAUX18_CON0 0x191c +#define MT6357_LDO_VAUD28_CON0 0x1930 +#define MT6357_LDO_VIO28_CON0 0x1944 +#define MT6357_LDO_VIO18_CON0 0x1958 +#define MT6357_LDO_VDRAM_CON0 0x196c +#define MT6357_LDO_VEMC_CON0 0x1988 +#define MT6357_LDO_VUSB33_CON0_0 0x199c +#define MT6357_LDO_VSRAM_PROC_CON0 0x19b2 +#define MT6357_LDO_VSRAM_PROC_DBG0 0x19cc +#define MT6357_LDO_VSRAM_OTHERS_CON0 0x19d0 +#define MT6357_LDO_VSRAM_OTHERS_DBG0 0x19ea +#define MT6357_LDO_VSRAM_WDT_DBG0 0x19f6 +#define MT6357_LDO_VSRAM_CON0 0x19fa +#define MT6357_LDO_VSRAM_CON1 0x19fc +#define MT6357_LDO_VFE28_CON0 0x1a08 +#define MT6357_LDO_VRF18_CON0 0x1a1c +#define MT6357_LDO_VRF12_CON0 0x1a30 +#define MT6357_LDO_VEFUSE_CON0 0x1a44 +#define MT6357_LDO_VCN18_CON0 0x1a58 +#define MT6357_LDO_VCAMA_CON0 0x1a6c +#define MT6357_LDO_VCAMD_CON0 0x1a88 +#define MT6357_LDO_VCAMIO_CON0 0x1a9c +#define MT6357_LDO_VMC_CON0 0x1ab0 +#define MT6357_LDO_VMCH_CON0 0x1ac4 +#define MT6357_LDO_VSIM1_CON0 0x1ad8 +#define MT6357_LDO_VSIM2_CON0 0x1aec +#define MT6357_LDO_VIBR_CON0 0x1b08 +#define MT6357_LDO_VCN33_CON0_0 0x1b1c +#define MT6357_LDO_VCN33_CON0_1 0x1b2a +#define MT6357_LDO_VLDO28_CON0_0 0x1b32 +#define MT6357_LDO_GOFF2_RSV_CON0 0x1b48 +#define MT6357_LDO_VCN28_CON0 0x1b88 +#define MT6357_LDO_TREF_CON0 0x1b9e +#define MT6357_LDO_GOFF3_RSV_CON0 0x1bae +#define MT6357_VXO22_ANA_CON0 0x1c18 +#define MT6357_VCN33_ANA_CON0 0x1c1c +#define MT6357_VEMC_ANA_CON0 0x1c20 +#define MT6357_VLDO28_ANA_CON0 0x1c24 +#define MT6357_VIBR_ANA_CON0 0x1c2c +#define MT6357_VSIM1_ANA_CON0 0x1c30 +#define MT6357_VSIM2_ANA_CON0 0x1c34 +#define MT6357_VMCH_ANA_CON0 0x1c38 +#define MT6357_VMC_ANA_CON0 0x1c3c +#define MT6357_VUSB33_ANA_CON0 0x1c88 +#define MT6357_VCAMA_ANA_CON0 0x1c8c +#define MT6357_VEFUSE_ANA_CON0 0x1c90 +#define MT6357_VCAMD_ANA_CON0 0x1c94 +#define MT6357_VDRAM_ELR_2 0x1cac + +#endif diff --git a/include/power/mt6359.h b/include/power/mt6359.h new file mode 100644 index 00000000000..1e0380e87b0 --- /dev/null +++ b/include/power/mt6359.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen <[email protected]> + */ + +#ifndef __MT6359_H_ +#define __MT6359_H_ + +#define MT6359_REGULATOR_DRIVER "mt6359_regulator" + +enum { + MT6359_ID_VS1 = 0, + MT6359_ID_VGPU11, + MT6359_ID_VMODEM, + MT6359_ID_VPU, + MT6359_ID_VCORE, + MT6359_ID_VS2, + MT6359_ID_VPA, + MT6359_ID_VPROC2, + MT6359_ID_VPROC1, + MT6359_ID_VCORE_SSHUB, + MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB, + MT6359_ID_VAUD18 = 10, + MT6359_ID_VSIM1, + MT6359_ID_VIBR, + MT6359_ID_VRF12, + MT6359_ID_VUSB, + MT6359_ID_VSRAM_PROC2, + MT6359_ID_VIO18, + MT6359_ID_VCAMIO, + MT6359_ID_VCN18, + MT6359_ID_VFE28, + MT6359_ID_VCN13, + MT6359_ID_VCN33_1_BT, + MT6359_ID_VCN33_1_WIFI, + MT6359_ID_VAUX18, + MT6359_ID_VSRAM_OTHERS, + MT6359_ID_VEFUSE, + MT6359_ID_VXO22, + MT6359_ID_VRFCK, + MT6359_ID_VBIF28, + MT6359_ID_VIO28, + MT6359_ID_VEMC, + MT6359_ID_VCN33_2_BT, + MT6359_ID_VCN33_2_WIFI, + MT6359_ID_VA12, + MT6359_ID_VA09, + MT6359_ID_VRF18, + MT6359_ID_VSRAM_MD, + MT6359_ID_VUFS, + MT6359_ID_VM18, + MT6359_ID_VBBCK, + MT6359_ID_VSRAM_PROC1, + MT6359_ID_VSIM2, + MT6359_ID_VSRAM_OTHERS_SSHUB, + MT6359_ID_RG_MAX, +}; + + +/* PMIC Registers */ +#define MT6359_BUCK_VPU_CON0 0x1488 +#define MT6359_BUCK_VPU_DBG1 0x14a8 +#define MT6359_BUCK_VPU_ELR0 0x14ac +#define MT6359_BUCK_VCORE_CON0 0x1508 +#define MT6359_BUCK_VCORE_DBG1 0x1528 +#define MT6359_BUCK_VGPU11_CON0 0x1588 +#define MT6359_BUCK_VGPU11_DBG1 0x15a8 +#define MT6359_BUCK_VMODEM_CON0 0x1688 +#define MT6359_BUCK_VMODEM_DBG1 0x16a8 +#define MT6359_BUCK_VMODEM_ELR0 0x16ae +#define MT6359_BUCK_VPROC1_CON0 0x1708 +#define MT6359_BUCK_VPROC1_DBG1 0x1728 +#define MT6359_BUCK_VPROC1_ELR0 0x172e +#define MT6359_BUCK_VPROC2_CON0 0x1788 +#define MT6359_BUCK_VPROC2_DBG1 0x17a8 +#define MT6359_BUCK_VPROC2_ELR0 0x17b2 +#define MT6359_BUCK_VS1_CON0 0x1808 +#define MT6359_BUCK_VS1_DBG1 0x1828 +#define MT6359_BUCK_VS1_ELR0 0x1834 +#define MT6359_BUCK_VS2_CON0 0x1888 +#define MT6359_BUCK_VS2_DBG1 0x18a8 +#define MT6359_BUCK_VS2_ELR0 0x18b4 +#define MT6359_BUCK_VPA_CON0 0x1908 +#define MT6359_BUCK_VPA_CON1 0x190e +#define MT6359_BUCK_VPA_DBG1 0x1916 +#define MT6359_VGPUVCORE_ANA_CON2 0x198e +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4 +#define MT6359_VPROC1_ANA_CON3 0x19b2 +#define MT6359_VPROC2_ANA_CON3 0x1a0e +#define MT6359_VMODEM_ANA_CON3 0x1a1a +#define MT6359_VPU_ANA_CON3 0x1a26 +#define MT6359_VS1_ANA_CON0 0x1a2c +#define MT6359_VS2_ANA_CON0 0x1a34 +#define MT6359_VPA_ANA_CON0 0x1a3c + +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1 +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1 +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1 +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1 +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 +#define MT6359_RG_VGPU11_FCCM_SHIFT 9 +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 +#define MT6359_RG_VCORE_FCCM_SHIFT 5 +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 +#define MT6359_RG_VPROC1_FCCM_SHIFT 1 +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 +#define MT6359_RG_VPROC2_FCCM_SHIFT 1 +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 +#define MT6359_RG_VMODEM_FCCM_SHIFT 1 +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 +#define MT6359_RG_VPU_FCCM_SHIFT 1 +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 +#define MT6359_RG_VS1_FPWM_SHIFT 3 +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 +#define MT6359_RG_VS2_FPWM_SHIFT 3 +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 +#define MT6359_RG_VPA_MODESET_SHIFT 1 +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8 +#define MT6359_RG_VIO28_VOSEL_MASK 0xF +#define MT6359_RG_VIO28_VOSEL_SHIFT 8 +#define MT6359_RG_VIBR_VOSEL_MASK 0xF +#define MT6359_RG_VIBR_VOSEL_SHIFT 8 +#define MT6359_RG_VRF18_VOSEL_MASK 0xF +#define MT6359_RG_VRF18_VOSEL_SHIFT 8 +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 +#define MT6359_RG_VIO18_VOSEL_MASK 0xF +#define MT6359_RG_VIO18_VOSEL_SHIFT 8 +#define MT6359_RG_VM18_VOSEL_MASK 0xF +#define MT6359_RG_VM18_VOSEL_SHIFT 8 +#define MT6359_RG_VUFS_VOSEL_MASK 0xF +#define MT6359_RG_VUFS_VOSEL_SHIFT 8 +#define MT6359_RG_VRF12_VOSEL_MASK 0xF +#define MT6359_RG_VRF12_VOSEL_SHIFT 8 +#define MT6359_RG_VCN13_VOSEL_MASK 0xF +#define MT6359_RG_VCN13_VOSEL_SHIFT 8 +#define MT6359_RG_VA09_VOSEL_MASK 0xF +#define MT6359_RG_VA09_VOSEL_SHIFT 8 +#define MT6359_RG_VA12_VOSEL_MASK 0xF +#define MT6359_RG_VA12_VOSEL_SHIFT 8 +#define MT6359_RG_VXO22_VOSEL_MASK 0xF +#define MT6359_RG_VXO22_VOSEL_SHIFT 8 +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8 + +#endif diff --git a/include/power/mt6359p.h b/include/power/mt6359p.h new file mode 100644 index 00000000000..506b5d38c68 --- /dev/null +++ b/include/power/mt6359p.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen <[email protected]> + */ + +#ifndef __MT6359P_H_ +#define __MT6359P_H_ + +#define MT6359P_CHIP_VER 0x5930 + +/* PMIC Registers */ +#define MT6359P_HWCID 0x8 +#define MT6359P_TOP_TRAP 0x50 +#define MT6359P_TOP_TMA_KEY 0x3a8 +#define MT6359P_BUCK_VCORE_ELR0 0x152c +#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa +#define MT6359P_BUCK_VGPU11_ELR0 0x15b4 +#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 +#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 +#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 +#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a +#define MT6359P_LDO_VEMC_ELR_0 0x1b4c +#define MT6359P_LDO_VFE28_CON0 0x1b88 +#define MT6359P_LDO_VFE28_MON 0x1b8c +#define MT6359P_LDO_VXO22_CON0 0x1b9a +#define MT6359P_LDO_VXO22_MON 0x1b9e +#define MT6359P_LDO_VRF18_CON0 0x1bac +#define MT6359P_LDO_VRF18_MON 0x1bb0 +#define MT6359P_LDO_VRF12_CON0 0x1bbe +#define MT6359P_LDO_VRF12_MON 0x1bc2 +#define MT6359P_LDO_VEFUSE_CON0 0x1bd0 +#define MT6359P_LDO_VEFUSE_MON 0x1bd4 +#define MT6359P_LDO_VCN33_1_CON0 0x1be2 +#define MT6359P_LDO_VCN33_1_MON 0x1be6 +#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 +#define MT6359P_LDO_VCN33_2_CON0 0x1c08 +#define MT6359P_LDO_VCN33_2_MON 0x1c0c +#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a +#define MT6359P_LDO_VCN13_CON0 0x1c1c +#define MT6359P_LDO_VCN13_MON 0x1c20 +#define MT6359P_LDO_VCN18_CON0 0x1c2e +#define MT6359P_LDO_VCN18_MON 0x1c32 +#define MT6359P_LDO_VA09_CON0 0x1c40 +#define MT6359P_LDO_VA09_MON 0x1c44 +#define MT6359P_LDO_VCAMIO_CON0 0x1c52 +#define MT6359P_LDO_VCAMIO_MON 0x1c56 +#define MT6359P_LDO_VA12_CON0 0x1c64 +#define MT6359P_LDO_VA12_MON 0x1c68 +#define MT6359P_LDO_VAUX18_CON0 0x1c88 +#define MT6359P_LDO_VAUX18_MON 0x1c8c +#define MT6359P_LDO_VAUD18_CON0 0x1c9a +#define MT6359P_LDO_VAUD18_MON 0x1c9e +#define MT6359P_LDO_VIO18_CON0 0x1cac +#define MT6359P_LDO_VIO18_MON 0x1cb0 +#define MT6359P_LDO_VEMC_CON0 0x1cbe +#define MT6359P_LDO_VEMC_MON 0x1cc2 +#define MT6359P_LDO_VSIM1_CON0 0x1cd0 +#define MT6359P_LDO_VSIM1_MON 0x1cd4 +#define MT6359P_LDO_VSIM2_CON0 0x1ce2 +#define MT6359P_LDO_VSIM2_MON 0x1ce6 +#define MT6359P_LDO_VUSB_CON0 0x1d08 +#define MT6359P_LDO_VUSB_MON 0x1d0c +#define MT6359P_LDO_VRFCK_CON0 0x1d1c +#define MT6359P_LDO_VRFCK_MON 0x1d20 +#define MT6359P_LDO_VBBCK_CON0 0x1d2e +#define MT6359P_LDO_VBBCK_MON 0x1d32 +#define MT6359P_LDO_VBIF28_CON0 0x1d40 +#define MT6359P_LDO_VBIF28_MON 0x1d44 +#define MT6359P_LDO_VIBR_CON0 0x1d52 +#define MT6359P_LDO_VIBR_MON 0x1d56 +#define MT6359P_LDO_VIO28_CON0 0x1d64 +#define MT6359P_LDO_VIO28_MON 0x1d68 +#define MT6359P_LDO_VM18_CON0 0x1d88 +#define MT6359P_LDO_VM18_MON 0x1d8c +#define MT6359P_LDO_VUFS_CON0 0x1d9a +#define MT6359P_LDO_VUFS_MON 0x1d9e +#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 +#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c +#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 +#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac +#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 +#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c +#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 +#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e +#define MT6359P_LDO_VSRAM_MD_MON 0x1f32 +#define MT6359P_VCN33_1_ANA_CON0 0x1f98 +#define MT6359P_VCN33_2_ANA_CON0 0x1f9c +#define MT6359P_VSIM1_ANA_CON0 0x1fa2 +#define MT6359P_VSIM2_ANA_CON0 0x1fa6 +#define MT6359P_VIO28_ANA_CON0 0x1faa +#define MT6359P_VIBR_ANA_CON0 0x1fae +#define MT6359P_VFE28_ELR_4 0x1fc0 +#define MT6359P_VRF18_ANA_CON0 0x2008 +#define MT6359P_VEFUSE_ANA_CON0 0x200c +#define MT6359P_VCAMIO_ANA_CON0 0x2014 +#define MT6359P_VIO18_ANA_CON0 0x201c +#define MT6359P_VM18_ANA_CON0 0x2020 +#define MT6359P_VUFS_ANA_CON0 0x2024 +#define MT6359P_VRF12_ANA_CON0 0x202a +#define MT6359P_VCN13_ANA_CON0 0x202e +#define MT6359P_VRF18_ELR_3 0x204e +#define MT6359P_VXO22_ANA_CON0 0x2088 +#define MT6359P_VRFCK_ANA_CON0 0x208c +#define MT6359P_VBBCK_ANA_CON0 0x2096 + +#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR +#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 +#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF +#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 +#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 +#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON +#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 +#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 +#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON +#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 +#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 +#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON +#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 +#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 +#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON +#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 +#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 +#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON +#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 +#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON +#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW +#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 +#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 +#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 +#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON +#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW +#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 +#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 +#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON +#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 +#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON +#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 +#define MT6359P_RG_LDO_VA09_EN_SHIFT 0 +#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON +#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 +#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 +#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON +#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 +#define MT6359P_RG_LDO_VA12_EN_SHIFT 0 +#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON +#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 +#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON +#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 +#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON +#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 +#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 +#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON +#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 +#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 +#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON +#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 +#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 +#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON +#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 +#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 +#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON +#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 +#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON +#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 +#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 +#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON +#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 +#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 +#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON +#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 +#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON +#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 +#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 +#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON +#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 +#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 +#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON +#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 +#define MT6359P_RG_LDO_VM18_EN_SHIFT 0 +#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON +#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 +#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 +#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON +#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 +#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON +#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 +#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 +#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 +#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON +#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 +#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 +#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 +#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 +#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 +#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 +#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 +#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 +#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 +#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 +#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 +#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 +#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 +#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 +#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3 +#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 +#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 +#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF +#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4 +#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP +#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY + +#define MT6359P_TMA_KEY 0x9CA6 + +#endif diff --git a/include/relocate.h b/include/relocate.h index 8ca25e1105e..331be138728 100644 --- a/include/relocate.h +++ b/include/relocate.h @@ -8,9 +8,7 @@ #define _RELOCATE_H_ #ifndef USE_HOSTCC -#include <asm/global_data.h> -DECLARE_GLOBAL_DATA_PTR; #endif /** diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 9b36d3ae67b..c40b448bcba 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -52,7 +52,7 @@ struct scmi_agent_priv { #if IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) struct udevice *voltagedom_dev; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) struct udevice *pinctrl_dev; #endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80) diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index ecab021b472..a8fd0a5a729 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -54,7 +54,8 @@ enum scmi_discovery_id { }; enum scmi_imx_misc_message_id { - SCMI_MISC_ROM_PASSOVER_GET = 0x7 + SCMI_MISC_ROM_PASSOVER_GET = 0x7, + SCMI_MISC_DDR_INFO_GET = 0x22, }; /* @@ -1088,7 +1089,14 @@ struct scmi_voltd_level_get_out { /* SCMI Pinctrl Protocol */ enum scmi_pinctrl_message_id { - SCMI_MSG_PINCTRL_CONFIG_SET = 0x6 + SCMI_PINCTRL_ATTRIBUTES = 0x3, + SCMI_PINCTRL_LIST_ASSOCIATIONS = 0x4, + SCMI_PINCTRL_SETTINGS_GET = 0x5, + SCMI_PINCTRL_SETTINGS_CONFIGURE = 0x6, + SCMI_PINCTRL_REQUEST = 0x7, + SCMI_PINCTRL_RELEASE = 0x8, + SCMI_PINCTRL_NAME_GET = 0x9, + SCMI_PINCTRL_SET_PERMISSIONS = 0xA, }; struct scmi_pin_config { @@ -1100,14 +1108,14 @@ struct scmi_pin_config { * struct scmi_pinctrl_config_set_in - Message payload for PAD_CONFIG_SET command * @identifier: Identifier for the pin or group. * @function_id: Identifier for the function selected to be enabled - * for the selected pin or group. This field is set to - * 0xFFFFFFFF if no function should be enabled by the - * pin or group. + * for the selected pin or group. This field is set to + * 0xFFFFFFFF if no function should be enabled by the + * pin or group. * @attributes: Bits[31:11] Reserved, must be zero. - * Bit[10] Function valid. - * Bits[9:2] Number of configurations to set. - * Bits[1:0] Selector: Whether the identifier field - * refers to a pin or a group. + * Bit[10] Function valid. + * Bits[9:2] Number of configurations to set. + * Bits[1:0] Selector: Whether the identifier field + * refers to a pin or a group. * @configs: Array of configurations. */ struct scmi_pinctrl_config_set_in { @@ -1139,4 +1147,360 @@ struct scmi_perf_in { struct scmi_perf_out { s32 status; }; + +#define SCMI_PIN_NAME_LEN 16 + +struct pin_info { + char name[SCMI_PIN_NAME_LEN]; +}; + +struct group_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *pins; + u32 num_pins; +}; + +struct function_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *groups; + u32 num_groups; +}; + +/* This is used by both the SCMI pinctrl and gpio drivers */ +struct pinctrl_scmi_priv { + int num_pins; + struct pin_info *pin_info; + int num_groups; + struct group_info *group_info; + int num_functions; + struct function_info *function_info; +}; + +/* SCMI Pinctrl selector type */ +enum select_type { + SCMI_PIN, + SCMI_GROUP, + SCMI_FUNCTION, +}; + +/** + * struct scmi_pinctrl_protocol_attrs_out - Response to SCMI_PROTOCOL_ATTRIBUTES + * command. + * @status: SCMI command status + * @attr_low: Number of pins and groups + * @attr_high: Number of functions + */ +struct scmi_pinctrl_protocol_attrs_out { + s32 status; + u32 attr_low; + u32 attr_high; +}; + +/** + * struct scmi_pinctrl_attrs_in - Parameters for SCMI_PINCTRL_ATTRIBUTES command + * @id: Identifier for pin, group or function + * @select_type: Pin, group or function + */ +struct scmi_pinctrl_attrs_in { + u32 id; + u32 select_type; +}; + +/** + * struct scmi_pinctrl_attrs_out - Response to SCMI_PINCTRL_ATTRIBUTES command + * @status: SCMI command status + * @attr: GPIO, number of pins or groups + * @name: Name of pin, group or function + */ +struct scmi_pinctrl_attrs_out { + s32 status; + u32 attr; + u8 name[SCMI_PIN_NAME_LEN]; +}; + +/** + * struct scmi_pinctrl_list_associations_in - Parameters for + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @id: Identifier for group or function + * @select_type: Group or function + * @index: Index within the group or function + */ +struct scmi_pinctrl_list_associations_in { + u32 id; + u32 select_type; + u32 index; +}; + +/** + * struct scmi_pinctrl_list_associations_out - Response to + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @status: SCMI command status + * @flags: Number of items returned and number still remaining + * @array: List of groups or pins + */ +struct scmi_pinctrl_list_associations_out { + s32 status; + u32 flags; + u16 array[]; +}; + +/** + * struct scmi_pinctrl_settings_get_in - Parameters for + * SCMI_PINCTRL_SETTINGS_GET command + * @id: Identifier for pin or group + * @attr: Config flag: one setting, function or all settings + * Selector: Pin or Group + * Skip: Number of config types to skip + * Config type: Type of config to read + */ +struct scmi_pinctrl_settings_get_in { + u32 id; + u32 attr; +}; + +#define SCMI_PINCTRL_CONFIG_SETTINGS_ALL -2u /* This is an internal magic number */ +#define SCMI_PINCTRL_FUNCTION_NONE 0xFFFFFFFF + +/** + * struct scmi_pinctrl_settings_get_out - Response to SCMI_PINCTRL_SETTINGS_GET + * command + * @status: SCMI command status + * @function_selected: The function enabled by the pin or group + * @num_configs: The number of settings returned and number still remaining + * @configs: The list of config data + */ +struct scmi_pinctrl_settings_get_out { + s32 status; + u32 function_selected; + u32 num_configs; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_in - Parameters for + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @id: Identifier for pin or group + * @function_id: The function to enable for this pin or group (optional) + * @attr: Function id: Set the function or not + * Number of configs to set + * Selector: pin or group + * @configs: List of config type value pairs + */ +struct scmi_pinctrl_settings_configure_in { + u32 id; + u32 function_id; + u32 attr; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_out - Response to + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @status: SCMI command status + */ +struct scmi_pinctrl_settings_configure_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_request_in - Parameters for SCMI_PINCTRL_REQUEST command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_request_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_request_out - Response to SCMI_PINCTRL_REQUEST command + * @status: SCMI command status + */ +struct scmi_pinctrl_request_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_release_in - Parameters for SCMI_PINCTRL_RELEASE command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_release_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_release_out - Response to SCMI_PINCTRL_RELEASE command + * @status: SCMI command status + */ +struct scmi_pinctrl_release_out { + s32 status; +}; + +/* SCMI Pinctrl Config Types */ +enum scmi_config_type { + SCMI_PIN_DEFUALT = 0, + SCMI_PIN_BIAS_BUS_HOLD = 1, + SCMI_PIN_BIAS_DISABLE = 2, + SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, + SCMI_PIN_BIAS_PULL_UP = 4, + SCMI_PIN_BIAS_PULL_DEFAULT = 5, + SCMI_PIN_BIAS_PULL_DOWN = 6, + SCMI_PIN_DRIVE_OPEN_DRAIN = 7, + SCMI_PIN_DRIVE_OPEN_SOURCE = 8, + SCMI_PIN_DRIVE_PUSH_PULL = 9, + SCMI_PIN_DRIVE_STRENGTH = 10, + SCMI_PIN_INPUT_DEBOUNCE = 11, + SCMI_PIN_INPUT_MODE = 12, + SCMI_PIN_PULL_MODE = 13, + SCMI_PIN_INPUT_VALUE = 14, + SCMI_PIN_INPUT_SCHMITT = 15, + SCMI_PIN_LOW_POWER_MODE = 16, + SCMI_PIN_OUTPUT_MODE = 17, + SCMI_PIN_OUTPUT_VALUE = 18, + SCMI_PIN_POWER_SOURCE = 19, + SCMI_PIN_SLEW_RATE = 20, +}; + +/** + * scmi_pinctrl_protocol_attrs - get pinctrl information + * @dev: SCMI protocol device + * @num_pins: Number of pins + * @num_groups: Number of groups + * @num_functions: Number of functions + * + * Obtain the number of pins, groups and functions. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions); + +/** + * scmi_pinctrl_attrs - get information for a specific pin, group or function + * @dev: SCMI protocol device + * @select_type: pin, group or function + * @selector: id of pin, group or function + * @gpio: set to true if the pin or group supports gpio + * @count: number of groups in function or pins in group + * @name: name of pin, group or function + * + * Obtain information about a specific pin, group or function. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name); + +/** + * scmi_pinctrl_request - claim a pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Claim ownership of a pin or group. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector); +/** + * scmi_pinctrl_release - release a claimed pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Release a pin or group that you previously claimed. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector); + +/** + * scmi_pinctrl_list_associations - get list of pins in group or groups in function + * @dev: SCMI protocol device + * @select_type: group or function + * @selector: id of group or function + * @output: list of groups in function or pins in group + * @num_out: How many groups are in the function or pins in the group + * + * Obtain the list of groups or pins in the function or group respectively. + * We know how many items will be in the list from calling scmi_pinctrl_attrs(). + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out); + +/** + * scmi_pinctrl_settings_get_one - get a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @config_type: Which configuration type to read + * @value: returned configuration value + * + * This reads a single config setting. Most importantly the + * SCMI_PIN_INPUT_VALUE setting is used to read from a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value); + +/** + * scmi_pinctrl_settings_configure - set multiple configuration settings + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @num_configs: number of settings to set + * @configs: Config type and value pairs + * + * Configure multiple settings at once to reduce overhead. The + * SCMI_PIN_OUTPUT_VALUE setting is used to write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs); + +/** + * scmi_pinctrl_settings_configure_one - set a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @param: The setting type to configure + * @argument: The value of the configuration + * + * Configure a single setting. The SCMI_PIN_OUTPUT_VALUE setting is used to + * write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument); + +/** + * scmi_pinctrl_set_function - set the function for a group or pin + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @function_id: id of the function + * + * Set the function for a group or pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id); + #endif /* _SCMI_PROTOCOLS_H */ diff --git a/include/smbios.h b/include/smbios.h index f2f7483bce5..39090d3ba18 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -110,10 +110,42 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE0_LENGTH_V24 0x18 +#define SMBIOS_TYPE0_LENGTH_V31 0x1a + #define SMBIOS_TYPE1_LENGTH_V20 0x08 #define SMBIOS_TYPE1_LENGTH_V21 0x19 #define SMBIOS_TYPE1_LENGTH_V24 0x1b +#define SMBIOS_TYPE4_LENGTH_V20 0x1a +#define SMBIOS_TYPE4_LENGTH_V23 0x23 +#define SMBIOS_TYPE4_LENGTH_V25 0x28 +#define SMBIOS_TYPE4_LENGTH_V26 0x2a +#define SMBIOS_TYPE4_LENGTH_V30 0x30 +#define SMBIOS_TYPE4_LENGTH_V36 0x32 + +#define SMBIOS_TYPE7_LENGTH_V20 0x0f +#define SMBIOS_TYPE7_LENGTH_V21 0x13 +#define SMBIOS_TYPE7_LENGTH_V31 0x1b + +#define SMBIOS_TYPE9_LENGTH_V20 0x0c +#define SMBIOS_TYPE9_LENGTH_V21 0x0d +#define SMBIOS_TYPE9_LENGTH_V26 0x11 + +#define SMBIOS_TYPE16_LENGTH_V21 0x0f +#define SMBIOS_TYPE16_LENGTH_V27 0x17 + +#define SMBIOS_TYPE17_LENGTH_V21 0x15 +#define SMBIOS_TYPE17_LENGTH_V23 0x1b +#define SMBIOS_TYPE17_LENGTH_V26 0x1c +#define SMBIOS_TYPE17_LENGTH_V27 0x22 +#define SMBIOS_TYPE17_LENGTH_V28 0x28 +#define SMBIOS_TYPE17_LENGTH_V32 0x54 +#define SMBIOS_TYPE17_LENGTH_V33 0x5c + +#define SMBIOS_TYPE19_LENGTH_V21 0x0f +#define SMBIOS_TYPE19_LENGTH_V27 0x1f + struct __packed smbios_type1 { struct smbios_header hdr; u8 manufacturer; @@ -264,6 +296,125 @@ struct __packed smbios_type7 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE9_PGROUP_SIZE 5 + +struct pci_attr_lookup_table { + const char *str; + u8 slot_type; + u8 data_bus_width; + u8 slot_length; + u8 chara1; + u8 chara2; +}; + +union dev_func_num { + struct { + u8 dev_num:5; + u8 func_num:3; + } fields; + u8 data; +}; + +struct __packed smbios_type9 { + struct smbios_header hdr; + u8 socket_design; + u8 slot_type; + u8 slot_data_bus_width; + u8 current_usage; + u8 slot_length; + u16 slot_id; + u8 slot_characteristics_1; + u8 slot_characteristics_2; + u16 segment_group_number; + u8 bus_number; + union dev_func_num device_function_number; + u8 electrical_bus_width; + u8 peer_grouping_count; + /* + * Dynamic bytes will be inserted here to store peer_groups. + * length is equal to 'peer_grouping_count' * 5 + */ + u8 slot_information; + u8 slot_physical_width; + u16 slot_pitch; + u8 slot_height; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +enum { + SMBIOS_MEM_NONE = 0, + SMBIOS_MEM_CUSTOM = 1, + SMBIOS_MEM_FDT_MEM_NODE = 2, + SMBIOS_MEM_FDT_MEMCON_NODE = 3 +}; + +struct __packed smbios_type16 { + struct smbios_header hdr; + u8 location; + u8 use; + u8 mem_err_corr; + u32 max_cap; + u16 mem_err_info_hdl; + u16 num_of_mem_dev; + u64 ext_max_cap; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type17 { + struct smbios_header hdr; + u16 phy_mem_array_hdl; + u16 mem_err_info_hdl; + u16 total_width; + u16 data_width; + u16 size; + u8 form_factor; + u8 dev_set; + u8 dev_locator; + u8 bank_locator; + u8 mem_type; + u16 type_detail; + u16 speed; + u8 manufacturer; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 attributes; + u32 ext_size; + u16 config_mem_speed; + u16 min_voltage; + u16 max_voltage; + u16 config_voltage; + u8 mem_tech; + u16 mem_op_mode_cap; + u8 fw_ver; + u16 module_man_id; + u16 module_prod_id; + u16 mem_subsys_con_man_id; + u16 mem_subsys_con_prod_id; + u64 nonvolatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; + u32 ext_speed; + u32 ext_config_mem_speed; + u16 pmic0_man_id; + u16 pmic0_rev_num; + u16 rcd_man_id; + u16 rcd_rev_num; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type19 { + struct smbios_header hdr; + u32 start_addr; + u32 end_addr; + u16 mem_array_hdl; + u8 partition_wid; + u64 ext_start_addr; + u64 ext_end_addr; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index 81c5781217f..ae50e1a808e 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -191,4 +191,254 @@ #define SMBIOS_CACHE_ASSOC_64WAY 13 #define SMBIOS_CACHE_ASSOC_20WAY 14 +/* + * System Slot + */ + +/* Slot Type */ +#define SMBIOS_SYSSLOT_TYPE_OTHER 1 +#define SMBIOS_SYSSLOT_TYPE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_TYPE_ISA 3 /* ISA */ +#define SMBIOS_SYSSLOT_TYPE_PCI 6 /* PCI */ +#define SMBIOS_SYSSLOT_TYPE_PCMCIA 7 /* PCMCIA */ +#define SMBIOS_SYSSLOT_TYPE_PCIE 0xa5 /* PCI Express */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX1 0xa6 /* PCI Express x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX2 0xa7 /* PCI Express x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX4 0xa8 /* PCI Express x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX8 0xa9 /* PCI Express x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX16 0xaa /* PCI Express x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2 0xab /* PCI Express Gen 2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X1 0xac /* PCI Express Gen 2 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X2 0xad /* PCI Express Gen 2 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X4 0xae /* PCI Express Gen 2 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X8 0xaf /* PCI Express Gen 2 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X16 0xb0 /* PCI Express Gen 2 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3 0xb1 /* PCI Express Gen 3 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X1 0xb2 /* PCI Express Gen 3 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X2 0xb3 /* PCI Express Gen 3 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X4 0xb4 /* PCI Express Gen 3 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X8 0xb5 /* PCI Express Gen 3 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16 0xb6 /* PCI Express Gen 3 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4 0xb8 /* PCI Express Gen 4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X1 0xb9 /* PCI Express Gen 4 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X2 0xba /* PCI Express Gen 4 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X4 0xbb /* PCI Express Gen 4 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8 0xbc /* PCI Express Gen 4 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16 0xbd /* PCI Express Gen 4 x16 */ + +/* Slot Data Bus Width */ +#define SMBIOS_SYSSLOT_WIDTH_OTHER 1 +#define SMBIOS_SYSSLOT_WIDTH_UNKNOWN 2 +#define SMBIOS_SYSSLOT_WIDTH_8BIT 3 +#define SMBIOS_SYSSLOT_WIDTH_16BIT 4 +#define SMBIOS_SYSSLOT_WIDTH_32BIT 5 +#define SMBIOS_SYSSLOT_WIDTH_64BIT 6 +#define SMBIOS_SYSSLOT_WIDTH_128BIT 7 +#define SMBIOS_SYSSLOT_WIDTH_1X 8 +#define SMBIOS_SYSSLOT_WIDTH_2X 9 +#define SMBIOS_SYSSLOT_WIDTH_4X 10 +#define SMBIOS_SYSSLOT_WIDTH_8X 11 +#define SMBIOS_SYSSLOT_WIDTH_12X 12 +#define SMBIOS_SYSSLOT_WIDTH_16X 13 +#define SMBIOS_SYSSLOT_WIDTH_32X 14 + +/* Current Usage */ +#define SMBIOS_SYSSLOT_USAGE_OTHER 1 +#define SMBIOS_SYSSLOT_USAGE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_USAGE_AVAILABLE 3 +#define SMBIOS_SYSSLOT_USAGE_INUSE 4 +#define SMBIOS_SYSSLOT_USAGE_NA 5 + +/* Slot Length */ +#define SMBIOS_SYSSLOT_LENG_OTHER 1 +#define SMBIOS_SYSSLOT_LENG_UNKNOWN 2 +#define SMBIOS_SYSSLOT_LENG_SHORT 3 +#define SMBIOS_SYSSLOT_LENG_LONG 4 +#define SMBIOS_SYSSLOT_LENG_2_5INDRV 5 +#define SMBIOS_SYSSLOT_LENG_3_5INDRV 6 + +/* Slot Characteristics 1 */ +#define SMBIOS_SYSSLOT_CHAR_UND 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_5V 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_3_3V 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_SHARED 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARD16 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDBUS 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDZV 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDMRR 0x80 /* BIT(7) */ + +/* Slot Characteristics 2 */ +#define SMBIOS_SYSSLOT_CHAR_PCIPME 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_HOTPLUG 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_PCISMB 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_PCIBIF 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_ASYNCRM 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL1 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL2 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL3 0x80 /* BIT(7) */ + +/* Slot segment group number */ +#define SMBIOS_SYSSLOT_SGGNUM_UND 0 + +/* Physical Memory Array */ + +/* Location */ +#define SMBIOS_MA_LOCATION_OTHER 1 +#define SMBIOS_MA_LOCATION_UNKNOWN 2 +#define SMBIOS_MA_LOCATION_MOTHERBOARD 3 + +/* Use */ +#define SMBIOS_MA_USE_OTHER 1 +#define SMBIOS_MA_USE_UNKNOWN 2 +#define SMBIOS_MA_USE_SYSTEM 3 +#define SMBIOS_MA_USE_VIDEO 4 +#define SMBIOS_MA_USE_FLASH 5 +#define SMBIOS_MA_USE_NVRAM 6 +#define SMBIOS_MA_USE_CACHE 7 + +/* Error Correction Type */ +#define SMBIOS_MA_ERRCORR_OTHER 1 +#define SMBIOS_MA_ERRCORR_UNKNOWN 2 +#define SMBIOS_MA_ERRCORR_NONE 3 +#define SMBIOS_MA_ERRCORR_PARITY 4 +#define SMBIOS_MA_ERRCORR_SBITECC 5 +#define SMBIOS_MA_ERRCORR_MBITECC 6 +#define SMBIOS_MA_ERRCORR_CRC 7 + +/* Error Information Handle */ +#define SMBIOS_MA_ERRINFO_NONE 0xFFFE +#define SMBIOS_MA_ERRINFO_NOERR 0xFFFF + +/* Memory Device */ + +/* Size */ + +#define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF +#define SMBIOS_MD_SIZE_EXT 0x7FFF + +/* Form Factor */ +#define SMBIOS_MD_FF_OTHER 1 +#define SMBIOS_MD_FF_UNKNOWN 2 +#define SMBIOS_MD_FF_SIMM 3 +#define SMBIOS_MD_FF_SIP 4 +#define SMBIOS_MD_FF_CHIP 5 +#define SMBIOS_MD_FF_DIP 6 +#define SMBIOS_MD_FF_ZIP 7 +#define SMBIOS_MD_FF_PROPCARD 8 +#define SMBIOS_MD_FF_DIMM 9 +#define SMBIOS_MD_FF_TSOP 10 +#define SMBIOS_MD_FF_ROC 11 +#define SMBIOS_MD_FF_RIMM 12 +#define SMBIOS_MD_FF_SODIMM 13 +#define SMBIOS_MD_FF_SRIMM 14 +#define SMBIOS_MD_FF_FBDIMM 15 +#define SMBIOS_MD_FF_DIE 16 + +/* Device set */ +#define SMBIOS_MD_DEVSET_NONE 0 +#define SMBIOS_MD_DEVSET_UNKNOWN 0xFF + +/* Speed */ +#define SMBIOS_MD_SPEED_UNKNOWN 0 +#define SMBIOS_MD_SPEED_EXT 0xFFFF + +/* Attributes */ +#define SMBIOS_MD_ATTR_RANK_UNKNOWN 0 + +/* Configured Memory Speed */ +#define SMBIOS_MD_CONFSPEED_UNKNOWN 0 +#define SMBIOS_MD_CONFSPEED_EXT 0xFFFF + +/* Voltage */ +#define SMBIOS_MD_VOLTAGE_UNKNOWN 0 + +/* Type */ +#define SMBIOS_MD_TYPE_OTHER 1 +#define SMBIOS_MD_TYPE_UNKNOWN 2 +#define SMBIOS_MD_TYPE_DRAM 3 +#define SMBIOS_MD_TYPE_EDRAM 4 +#define SMBIOS_MD_TYPE_VRAM 5 +#define SMBIOS_MD_TYPE_SRAM 6 +#define SMBIOS_MD_TYPE_RAM 7 +#define SMBIOS_MD_TYPE_ROM 8 +#define SMBIOS_MD_TYPE_FLASH 9 +#define SMBIOS_MD_TYPE_EEPROM 10 +#define SMBIOS_MD_TYPE_FEPROM 11 +#define SMBIOS_MD_TYPE_EPROM 12 +#define SMBIOS_MD_TYPE_CDRAM 13 +#define SMBIOS_MD_TYPE_3DRAM 14 +#define SMBIOS_MD_TYPE_SDRAM 15 +#define SMBIOS_MD_TYPE_SGRAM 16 +#define SMBIOS_MD_TYPE_RDRAM 17 +#define SMBIOS_MD_TYPE_DDR 18 +#define SMBIOS_MD_TYPE_DDR2 19 +#define SMBIOS_MD_TYPE_DDR2FBD 20 +#define SMBIOS_MD_TYPE_RSVD1 21 +#define SMBIOS_MD_TYPE_RSVD2 22 +#define SMBIOS_MD_TYPE_DSVD3 23 +#define SMBIOS_MD_TYPE_DDR3 24 +#define SMBIOS_MD_TYPE_FBD2 25 +#define SMBIOS_MD_TYPE_DDR4 26 +#define SMBIOS_MD_TYPE_LPDDR 27 +#define SMBIOS_MD_TYPE_LPDDR2 28 +#define SMBIOS_MD_TYPE_LPDDR3 29 +#define SMBIOS_MD_TYPE_LPDDR4 30 +#define SMBIOS_MD_TYPE_LNVD 31 +#define SMBIOS_MD_TYPE_HBM 32 +#define SMBIOS_MD_TYPE_HBM2 33 +#define SMBIOS_MD_TYPE_DDR5 34 +#define SMBIOS_MD_TYPE_LPDDR5 35 +#define SMBIOS_MD_TYPE_HBM3 36 + +/* Type Detail */ +#define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_TD_FP 8 /* BIT(3) */ +#define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */ +#define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */ +#define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */ +#define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */ +#define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */ +#define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */ +#define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */ +#define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */ +#define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */ +#define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */ +#define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */ +#define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */ + +/* Technology */ +#define SMBIOS_MD_TECH_OTHER 1 +#define SMBIOS_MD_TECH_UNKNOWN 2 +#define SMBIOS_MD_TECH_DRAM 3 +#define SMBIOS_MD_TECH_NVDIMMN 4 +#define SMBIOS_MD_TECH_NVDIMMF 5 +#define SMBIOS_MD_TECH_NVDIMMP 6 +#define SMBIOS_MD_TECH_OPTANE 7 + +/* Operating Mode Capability */ +#define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */ +#define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */ +#define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */ +/* Bit 6:15 Reserved, set to 0 */ + +/* Non-volatile / Volatile / Cache / Logical portion Size */ +#define SMBIOS_MD_PORT_SIZE_NONE 0 +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF +#define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF + +/* Error Information Handle */ +#define SMBIOS_MD_ERRINFO_NONE 0xFFFE +#define SMBIOS_MD_ERRINFO_NOERR 0xFFFF + +/* Memory Array Mapped Address */ + +/* Partition Width */ +#define SMBIOS_MAMA_PW_DEF 1 /* not partitioned */ + #endif /* _SMBIOS_DEF_H_ */ diff --git a/include/spi.h b/include/spi.h index 2783200d663..95e7d5b1556 100644 --- a/include/spi.h +++ b/include/spi.h @@ -658,17 +658,6 @@ int spi_chip_select(struct udevice *slave); int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); /** - * spi_slave_of_to_plat() - decode standard SPI platform data - * - * This decodes the speed and mode for a slave from a device tree node - * - * @blob: Device tree blob - * @node: Node offset to read from - * @plat: Place to put the decoded information - */ -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat); - -/** * spi_cs_info() - Check information on a chip select * * This checks a particular chip select on a bus to see if it has a device diff --git a/include/spl.h b/include/spl.h index 06dc28362d3..5078d7525ab 100644 --- a/include/spl.h +++ b/include/spl.h @@ -882,6 +882,12 @@ int spl_blk_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, enum uclass_id uclass_id, int devnum, int partnum); +/* SPL SQUASHFS image functions */ +int spl_load_image_sqfs(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + struct blk_desc *block_dev, int partition, + const char *filename); + /** * spl_early_init() - Set up device tree and driver model in SPL if enabled * diff --git a/include/squashfs.h b/include/squashfs.h index 7489eefa1f2..83ed8a49442 100644 --- a/include/squashfs.h +++ b/include/squashfs.h @@ -10,7 +10,10 @@ #ifndef _SQFS_H_ #define _SQFS_H_ -struct disk_partition; +#include <fs.h> +#include <blk.h> +#include <part.h> +#include <linux/types.h> int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp); int sqfs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); diff --git a/include/status_led.h b/include/status_led.h deleted file mode 100644 index c3ff399b1ae..00000000000 --- a/include/status_led.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, [email protected]. - */ - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -#ifndef _STATUS_LED_H_ -#define _STATUS_LED_H_ - -#ifdef CONFIG_LED_STATUS - -#define LED_STATUS_PERIOD (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ) -#ifdef CONFIG_LED_STATUS1 -#define LED_STATUS_PERIOD1 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ1) -#endif /* CONFIG_LED_STATUS1 */ -#ifdef CONFIG_LED_STATUS2 -#define LED_STATUS_PERIOD2 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ2) -#endif /* CONFIG_LED_STATUS2 */ -#ifdef CONFIG_LED_STATUS3 -#define LED_STATUS_PERIOD3 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ3) -#endif /* CONFIG_LED_STATUS3 */ -#ifdef CONFIG_LED_STATUS4 -#define LED_STATUS_PERIOD4 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ4) -#endif /* CONFIG_LED_STATUS4 */ -#ifdef CONFIG_LED_STATUS5 -#define LED_STATUS_PERIOD5 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ5) -#endif /* CONFIG_LED_STATUS5 */ - -void status_led_init(void); -void status_led_tick(unsigned long timestamp); -void status_led_set(int led, int state); - -static inline void status_led_boot_blink(void) -{ -#ifdef CONFIG_LED_STATUS_BOOT_ENABLE - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING); -#endif -} - -#if defined(CONFIG_LED_STATUS_BOARD_SPECIFIC) -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -extern void __led_toggle (led_id_t mask); -extern void __led_init (led_id_t mask, int state); -extern void __led_set (led_id_t mask, int state); -void __led_blink(led_id_t mask, int freq); -#else -# error Status LED configuration missing -#endif - -#else - -static inline void status_led_init(void) { } -static inline void status_led_set(int led, int state) { } -static inline void status_led_boot_blink(void) { } - -#endif /* CONFIG_LED_STATUS */ -#endif /* _STATUS_LED_H_ */ diff --git a/include/sysinfo.h b/include/sysinfo.h index e87cf969fcd..54eb64a204a 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -12,6 +12,7 @@ struct udevice; #define SYSINFO_CACHE_LVL_MAX 3 +#define SYSINFO_MEM_HANDLE_MAX 8 /* * This uclass encapsulates hardware methods to gather information about a @@ -149,6 +150,9 @@ enum sysinfo_id { SYSID_SM_CACHE_INFO_END = SYSID_SM_CACHE_INST_SIZE2 + SYSINFO_CACHE_LVL_MAX - 1, + /* Memory Array (Type 16) */ + SYSID_SM_MEMARRAY_HANDLE, + /* For show_board_info() */ SYSID_BOARD_MODEL, SYSID_BOARD_MANUFACTURER, diff --git a/include/usb.h b/include/usb.h index be37ed272e1..dab23753f0c 100644 --- a/include/usb.h +++ b/include/usb.h @@ -209,15 +209,6 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); #define USB_UHCI_DEV_ID 0x7112 /* - * PXA25x can only act as USB device. There are drivers - * which works with USB CDC gadgets implementations. - * Some of them have common routines which can be used - * in boards init functions e.g. udc_disconnect() used for - * forced device disconnection from host. - */ -extern void udc_disconnect(void); - -/* * board-specific hardware initialization, called by * usb drivers and u-boot commands * diff --git a/include/usb/udc.h b/include/usb/udc.h index 749b3a3f015..c5e431813be 100644 --- a/include/usb/udc.h +++ b/include/usb/udc.h @@ -39,7 +39,6 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint); void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); void udc_connect(void); -void udc_disconnect(void); void udc_enable(struct usb_device_instance *device); void udc_disable(void); void udc_startup_events(struct usb_device_instance *device); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 05df49f292a..f5e72625e53 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -185,6 +185,11 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +#define NUM_GROUPS_PER_RESP 6 +#define NA_GROUP -1 +#define RESERVED_GROUP -2 +#define MAX_FUNC_NAME_LEN 16 + enum pm_pinctrl_config_param { PM_PINCTRL_CONFIG_SLEW_RATE = 0, PM_PINCTRL_CONFIG_BIAS_STATUS = 1, |