Merge tag 'u-boot-rockchip-20220418' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

- Add rk3066 SoC support;
- Add rk3066 MK808 board support;
- dts sync from kernel for rk322x, rk3288;
- some other board level config update;

19 files changed, 202 insertions, 24 deletions

diff --git a/include/configs/mk808.h b/include/configs/mk808.h
new file mode 100644
index 00000000000..e2ab2b512c8
--- /dev/null
+++ b/include/configs/mk808.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3066_common.h>
+
+#endif
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 09923871571..dc609013f32 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -12,7 +12,6 @@
 
 #define CONFIG_SYS_NS16550_MEM32
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xff220020
 #define COUNTER_FREQUENCY		24000000
 
 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 00c453d739d..5905518edf1 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -10,7 +10,6 @@
 
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0x200440a0
 #define COUNTER_FREQUENCY		24000000
 #define CONFIG_SYS_HZ_CLOCK		24000000
 
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
new file mode 100644
index 00000000000..be7d644e1e5
--- /dev/null
+++ b/include/configs/rk3066_common.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_RK3066_COMMON_H
+#define __CONFIG_RK3066_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE		256
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x78000000
+
+#define CONFIG_IRAM_BASE		0x10080000
+
+#define CONFIG_SPL_MAX_SIZE		0x32000
+
+#define CONFIG_SPL_STACK		0x1008FFFF
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define SDRAM_BANK_SIZE			(1024UL << 20UL)
+#define SDRAM_MAX_SIZE			CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x6fffffff\0" \
+	"initrd_high=0x6fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 97caceacfe6..d77a7d7b098 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0x200440a0
 #define COUNTER_FREQUENCY		24000000
 #define CONFIG_SYS_HZ_CLOCK		24000000
 
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index ef55ef0a83b..3258820fcdc 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0x110d0020
 #define COUNTER_FREQUENCY		24000000
 #define CONFIG_SYS_HZ_CLOCK		24000000
 
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 490da7cb23b..e2e0f70a70c 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -13,7 +13,6 @@
 
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xff810020
 #define COUNTER_FREQUENCY		24000000
 #define CONFIG_SYS_HZ_CLOCK		24000000
 
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 1664707ca65..9cda8d9c48b 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -15,7 +15,6 @@
 
 #define CONFIG_SYS_NS16550_MEM32
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xff1b00a0
 #define CONFIG_IRAM_BASE		0xfff80000
 #define CONFIG_SYS_INIT_SP_ADDR		0x00800000
 #define CONFIG_SPL_STACK		0x00400000
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index c1e26a019b5..8a5f0c8999f 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -10,7 +10,6 @@
 
 #define CONFIG_IRAM_BASE		0xff090000
 
-#define CONFIG_ROCKCHIP_STIMER_BASE    0xff1d0020
 #define COUNTER_FREQUENCY		24000000
 
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 8b239ca07da..239296c1d22 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -15,7 +15,6 @@
 #define SDRAM_MAX_SIZE			0xff000000
 #define CONFIG_SYS_CBSIZE		1024
 
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xff830020
 #define COUNTER_FREQUENCY		24000000
 
 #define CONFIG_IRAM_BASE		0xff8c0000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index ed72c8bb6b1..4037dba58cc 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 
 #define COUNTER_FREQUENCY               24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xff8680a0
 
 #define CONFIG_IRAM_BASE		0xff8c0000
 
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index 25d7c5cc8ff..5649cd64e0e 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 
 #define COUNTER_FREQUENCY               24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE	0xfdd1c020
 
 #define CONFIG_IRAM_BASE		0xfdcc0000
 
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index ba7061a287c..0c08776ae26 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -29,6 +29,12 @@
 	#define BOOT_TARGET_NVME(func)
 #endif
 
+#if CONFIG_IS_ENABLED(CMD_SCSI)
+	#define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
+#else
+	#define BOOT_TARGET_SCSI(func)
+#endif
+
 #if CONFIG_IS_ENABLED(CMD_USB)
 	#define BOOT_TARGET_USB(func) func(USB, usb, 0)
 #else
@@ -57,6 +63,7 @@
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_MMC(func) \
 	BOOT_TARGET_NVME(func) \
+	BOOT_TARGET_SCSI(func) \
 	BOOT_TARGET_USB(func) \
 	BOOT_TARGET_PXE(func) \
 	BOOT_TARGET_DHCP(func) \
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 1217d5239f5..de550ea56ee 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Jeffy Chen <[email protected]>
  */
 
 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
@@ -39,6 +40,7 @@
 #define SCLK_EMMC_DRV		117
 #define SCLK_SDMMC_SAMPLE	118
 #define SCLK_SDIO_SAMPLE	119
+#define SCLK_SDIO_SRC		120
 #define SCLK_EMMC_SAMPLE	121
 #define SCLK_VOP		122
 #define SCLK_HDMI_HDCP		123
@@ -51,6 +53,18 @@
 #define SCLK_MAC_TX		130
 #define SCLK_MAC_PHY		131
 #define SCLK_MAC_OUT		132
+#define SCLK_VDEC_CABAC		133
+#define SCLK_VDEC_CORE		134
+#define SCLK_RGA		135
+#define SCLK_HDCP		136
+#define SCLK_HDMI_CEC		137
+#define SCLK_CRYPTO		138
+#define SCLK_TSP		139
+#define SCLK_HSADC		140
+#define SCLK_WIFI		141
+#define SCLK_OTGPHY0		142
+#define SCLK_OTGPHY1		143
+#define SCLK_HDMI_PHY		144
 
 /* dclk gates */
 #define DCLK_VOP		190
@@ -58,15 +72,32 @@
 
 /* aclk gates */
 #define ACLK_DMAC		194
+#define ACLK_CPU		195
+#define ACLK_VPU_PRE		196
+#define ACLK_RKVDEC_PRE		197
+#define ACLK_RGA_PRE		198
+#define ACLK_IEP_PRE		199
+#define ACLK_HDCP_PRE		200
+#define ACLK_VOP_PRE		201
+#define ACLK_VPU		202
+#define ACLK_RKVDEC		203
+#define ACLK_IEP		204
+#define ACLK_RGA		205
+#define ACLK_HDCP		206
 #define ACLK_PERI		210
 #define ACLK_VOP		211
 #define ACLK_GMAC		212
+#define ACLK_GPU		213
 
 /* pclk gates */
 #define PCLK_GPIO0		320
 #define PCLK_GPIO1		321
 #define PCLK_GPIO2		322
 #define PCLK_GPIO3		323
+#define PCLK_VIO_H2P		324
+#define PCLK_HDCP		325
+#define PCLK_EFUSE_1024		326
+#define PCLK_EFUSE_256		327
 #define PCLK_GRF		329
 #define PCLK_I2C0		332
 #define PCLK_I2C1		333
@@ -79,6 +110,7 @@
 #define PCLK_TSADC		344
 #define PCLK_PWM		350
 #define PCLK_TIMER		353
+#define PCLK_CPU		354
 #define PCLK_PERI		363
 #define PCLK_HDMI_CTRL		364
 #define PCLK_HDMI_PHY		365
@@ -94,6 +126,24 @@
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
 #define HCLK_EMMC		459
+#define HCLK_CPU		460
+#define HCLK_VPU_PRE		461
+#define HCLK_RKVDEC_PRE		462
+#define HCLK_VIO_PRE		463
+#define HCLK_VPU		464
+#define HCLK_RKVDEC		465
+#define HCLK_VIO		466
+#define HCLK_RGA		467
+#define HCLK_IEP		468
+#define HCLK_VIO_H2P		469
+#define HCLK_HDCP_MMU		470
+#define HCLK_HOST0		471
+#define HCLK_HOST1		472
+#define HCLK_HOST2		473
+#define HCLK_OTG		474
+#define HCLK_TSP		475
+#define HCLK_M_CRYPTO		476
+#define HCLK_S_CRYPTO		477
 #define HCLK_PERI		478
 
 #define CLK_NR_CLKS		(HCLK_PERI + 1)
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index e368d767506..453f66718c6 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -1,9 +1,12 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright (c) 2014 MundoReader S.L.
  * Author: Heiko Stuebner <[email protected]>
  */
 
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+
 /* core clocks */
 #define PLL_APLL		1
 #define PLL_DPLL		2
@@ -74,6 +77,9 @@
 #define SCLK_USBPHY480M_SRC	122
 #define SCLK_PVTM_CORE		123
 #define SCLK_PVTM_GPU		124
+#define SCLK_CRYPTO		125
+#define SCLK_MIPIDSI_24M	126
+#define SCLK_VIP_OUT		127
 
 #define SCLK_MAC_PLL		150
 #define SCLK_MAC		151
@@ -153,6 +159,9 @@
 #define PCLK_DDRUPCTL1		366
 #define PCLK_PUBL1		367
 #define PCLK_WDT		368
+#define PCLK_EFUSE256		369
+#define PCLK_EFUSE1024		370
+#define PCLK_ISP_IN		371
 
 /* hclk gates */
 #define HCLK_GPS		448
@@ -368,3 +377,5 @@
 #define SRST_TSP_CLKIN0		189
 #define SRST_TSP_CLKIN1		190
 #define SRST_TSP_27M		191
+
+#endif
diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
deleted file mode 100644
index ca68c11475c..00000000000
--- a/include/dt-bindings/power-domain/rk3288.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
-
-/* RK3288 power domain index */
-#define RK3288_PD_GPU          0
-#define RK3288_PD_VIO          1
-#define RK3288_PD_VIDEO        2
-#define RK3288_PD_HEVC         3
-#define RK3288_PD_PERI         4
-
-#endif
diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h
new file mode 100644
index 00000000000..acf9f310ac5
--- /dev/null
+++ b/include/dt-bindings/power/rk3066-power.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__
+#define __DT_BINDINGS_POWER_RK3066_POWER_H__
+
+/* VD_CORE */
+#define RK3066_PD_A9_0		0
+#define RK3066_PD_A9_1		1
+#define RK3066_PD_DBG		4
+#define RK3066_PD_SCU		5
+
+/* VD_LOGIC */
+#define RK3066_PD_VIDEO		6
+#define RK3066_PD_VIO		7
+#define RK3066_PD_GPU		8
+#define RK3066_PD_PERI		9
+#define RK3066_PD_CPU		10
+#define RK3066_PD_ALIVE		11
+
+/* VD_PMU */
+#define RK3066_PD_RTC		12
+
+#endif
diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h
new file mode 100644
index 00000000000..6a8dc1bf76c
--- /dev/null
+++ b/include/dt-bindings/power/rk3228-power.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__
+#define __DT_BINDINGS_POWER_RK3228_POWER_H__
+
+/**
+ * RK3228 idle id Summary.
+ */
+
+#define RK3228_PD_CORE		0
+#define RK3228_PD_MSCH		1
+#define RK3228_PD_BUS		2
+#define RK3228_PD_SYS		3
+#define RK3228_PD_VIO		4
+#define RK3228_PD_VOP		5
+#define RK3228_PD_VPU		6
+#define RK3228_PD_RKVDEC	7
+#define RK3228_PD_GPU		8
+#define RK3228_PD_PERI		9
+#define RK3228_PD_GMAC		10
+
+#endif
diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h
new file mode 100644
index 00000000000..f710b56ccd8
--- /dev/null
+++ b/include/dt-bindings/power/rk3288-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__
+#define __DT_BINDINGS_POWER_RK3288_POWER_H__
+
+/**
+ * RK3288 Power Domain and Voltage Domain Summary.
+ */
+
+/* VD_CORE */
+#define RK3288_PD_A17_0		0
+#define RK3288_PD_A17_1		1
+#define RK3288_PD_A17_2		2
+#define RK3288_PD_A17_3		3
+#define RK3288_PD_SCU		4
+#define RK3288_PD_DEBUG		5
+#define RK3288_PD_MEM		6
+
+/* VD_LOGIC */
+#define RK3288_PD_BUS		7
+#define RK3288_PD_PERI		8
+#define RK3288_PD_VIO		9
+#define RK3288_PD_ALIVE		10
+#define RK3288_PD_HEVC		11
+#define RK3288_PD_VIDEO		12
+
+/* VD_GPU */
+#define RK3288_PD_GPU		13
+
+/* VD_PMU */
+#define RK3288_PD_PMU		14
+
+#endif