diff options
| author | Chia-Wei Wang <[email protected]> | 2024-09-10 17:39:16 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2024-09-11 20:35:03 +0800 |
| commit | 9efcb10a09d69d9cf14111dd452bbf54dc0502b4 (patch) | |
| tree | e1554ebe4da7d87915116f64d3264d9dd4e12714 /include | |
| parent | 717002f8ff277bb687ce1f2739d0ef715d319ad9 (diff) | |
riscv: Add AST2700 SoC initial platform support
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.
This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ibex_ast2700.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/configs/ibex_ast2700.h b/include/configs/ibex_ast2700.h new file mode 100644 index 00000000000..0f6850f7240 --- /dev/null +++ b/include/configs/ibex_ast2700.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __CONFIG_H */ |