diff options
| author | Paul Barker <[email protected]> | 2024-11-20 09:48:29 +0000 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2024-12-08 23:06:52 +0100 |
| commit | bba516a772853595901a7359209bc588d2bffda0 (patch) | |
| tree | 019c031f1ebdfcff46896d02f0ce143ab1c75e3e /include | |
| parent | 215663f5e47db92c6c13107e877a943c3e70aa2a (diff) | |
pinctrl: rzg2l: Support Ethernet TXC output enable
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.
As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/renesas/rzg2l-pfc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index d1015b1d2ac..0c94487754d 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -22,6 +22,7 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_OEN BIT(13) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -79,6 +80,7 @@ #define SD_CH(n) (0x3000 + (n) * 4) #define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 +#define ETH_MODE 0x3018 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ |