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authorPrasad Kummari <[email protected]>2025-03-27 16:21:58 +0530
committerMichal Simek <[email protected]>2025-04-16 13:44:44 +0200
commitc2db55499a5d460f33d649728853ca3b69d0c754 (patch)
treed08e93c788e6e7f1de27143abc87e04ce1b8b4f8 /include
parentb5a88e9d95369537876bef1e84e591f583bf7d85 (diff)
arm64: versal-net: Add PL bit stream load support
Add support for loading the secure & non-secure pdi images and PL bitstream on the Versal NET platform. The FPGA driver is enabled to load the bitstream in PDI format on the AMD Versal NET device. PDI is the new programmable device image format for Versal NET, and the bitstream for the Versal NET platform is generated exclusively in this format. The source code for the versalnet loadpdi command and the CONFIG_CMD_VERSAL_NET configuration has been removed. It now utilizes the fpga load <dev> <address> <length> command to load secure & non-secure pdi images. Signed-off-by: Prasad Kummari <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'include')
-rw-r--r--include/xilinx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/xilinx.h b/include/xilinx.h
index e4e29797988..2b4d6c9bb06 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -34,6 +34,7 @@ typedef enum { /* typedef xilinx_family */
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
xilinx_versal, /* Versal Family */
+ xilinx_versal_net, /* Versal NET Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */