diff options
| author | Tom Rini <[email protected]> | 2021-10-03 19:31:04 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2021-10-03 19:31:04 -0400 |
| commit | e17cbdd050f7127737988997f4a01583b34f7c96 (patch) | |
| tree | 6c7cd744ac55da0f0a782a40b6c165b405bcd7e8 /include | |
| parent | 67e6c540a098ee5ecb3fdf0b332d9a63b00fdbd7 (diff) | |
| parent | 26fa063c6e6c12ff111c9ccadd41b84e3f66ad1d (diff) | |
Merge branch '2021-10-03-platform-updates' into next
- TI K3 updates, add IOT2050 platform
- rtc rx8025 updates, PCI fixes
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/iot2050.h | 62 | ||||
| -rw-r--r-- | include/dt-bindings/net/ti-dp83867.h | 39 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/k3.h | 51 | ||||
| -rw-r--r-- | include/pci.h | 2 |
4 files changed, 108 insertions, 46 deletions
diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h new file mode 100644 index 00000000000..ddb4cfcc8e2 --- /dev/null +++ b/include/configs/iot2050.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for IOT2050 + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Le Jin <[email protected]> + * Jan Kiszka <[email protected]> + */ + +#ifndef __CONFIG_IOT2050_H +#define __CONFIG_IOT2050_H + +#include <linux/sizes.h> + +/* SPL Loader Configuration */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* U-Boot general configuration */ +#define EXTRA_ENV_IOT2050_BOARD_SETTINGS \ + "usb_pgood_delay=900\0" + +#ifndef CONFIG_SPL_BUILD + +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ + func(USB, usb, 2) +#else +# define BOOT_TARGET_USB(func) +#endif + +/* + * This defines all MMC devices, even if the basic variant has no mmc1. + * The non-supported device will be removed from the boot targets during + * runtime, when that board was detected. + */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_USB(func) + +#include <config_distro_bootcmd.h> + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + BOOTENV \ + EXTRA_ENV_IOT2050_BOARD_SETTINGS + +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_IOT2050_H */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index cde5aa7e27d..6fc4b445d3a 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -1,7 +1,10 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* - * TI DP83867 PHY drivers + * Device Tree constants for the Texas Instruments DP83867 PHY * + * Author: Dan Murphy <[email protected]> + * + * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H @@ -14,22 +17,22 @@ #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e6cb1d0540e..e085f102b28 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -1,36 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This header provides constants for TI K3-AM65 pinctrl bindings. + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. * - * Copyright (C) 2018-2021 Texas Instruments + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_200MHZ 0 -#define SLEWCTRL_150MHZ (1 << 19) -#define SLEWCTRL_100MHZ (2 << 19) -#define SLEWCTRL_50MHZ (3 << 19) -#define TX_DIS (1 << 21) -#define ISO_OVR (1 << 22) -#define ISO_BYPASS (1 << 23) -#define DS_EN (1 << 24) -#define DS_INPUT (1 << 25) -#define DS_FORCE_OUT_HIGH (1 << 26) -#define DS_PULL_UP_DOWN_EN 0 -#define DS_PULL_UP_DOWN_DIS (1 << 27) -#define DS_PULL_UP_SEL (1 << 28) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +#define _DT_BINDINGS_PINCTRL_TI_K3_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) #define PIN_INPUT (INPUT_EN | PULL_DISABLE) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/include/pci.h b/include/pci.h index 0fc22adffd0..11009a2f787 100644 --- a/include/pci.h +++ b/include/pci.h @@ -724,6 +724,7 @@ void pciauto_config_init(struct pci_controller *hose); */ int pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit); +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); #if defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, @@ -741,7 +742,6 @@ extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern struct pci_controller *pci_get_hose_head(void); -extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); |
