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authorTom Rini <[email protected]>2026-03-25 11:09:34 -0600
committerTom Rini <[email protected]>2026-03-25 11:09:34 -0600
commitfce0358351017ab88987e40ad887670463373e7e (patch)
tree1c132acb016978ed453a9596a4a110ec8e47988f /include
parent5a36f434254f6977884eedffc2b8f3a8d70a5a34 (diff)
parent20531fa6183e6b9426c955abf72b1e3db7687c8c (diff)
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
Diffstat (limited to 'include')
-rw-r--r--include/power/cpcap.h48
1 files changed, 15 insertions, 33 deletions
diff --git a/include/power/cpcap.h b/include/power/cpcap.h
index bb0e28cec55..b035b84840f 100644
--- a/include/power/cpcap.h
+++ b/include/power/cpcap.h
@@ -297,32 +297,21 @@ static const char * const cpcap_regulator_to_name[] = {
};
static const u32 unknown_val_tbl[] = { 0, };
-static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000,
- 812500, 825000, 837500, 850000, 862500,
- 875000, 887500, 900000, 912500, 925000,
- 937500, 950000, 962500, 975000, 987500,
- 1000000, 1012500, 1025000, 1037500,
- 1050000, 1062500, 1075000, 1087500,
- 1100000, 1112500, 1125000, 1137500,
- 1150000, 1162500, 1175000, 1187500,
- 1200000, 1212500, 1225000, 1237500,
- 1250000, 1262500, 1275000, 1287500,
- 1300000, 1312500, 1325000, 1337500,
- 1350000, 1362500, 1375000, 1387500,
- 1400000, 1412500, 1425000, 1437500,
- 1450000, 1462500, 1475000 };
-static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000,
- 962500, 975000, 987500, 1000000, 1012500,
- 1025000, 1037500, 1050000, 1062500,
- 1075000, 1087500, 1100000, 1112500,
- 1125000, 1137500, 1150000, 1162500,
- 1175000, 1187500, 1200000, 1212500,
- 1225000, 1237500, 1250000, 1262500,
- 1275000, 1287500, 1300000, 1312500,
- 1325000, 1337500, 1350000, 1362500,
- 1375000, 1387500, 1400000, 1412500,
- 1425000, 1437500, 1450000, 1462500,
- 1475000 };
+static const u32 sw_val_tbl[] = { 600000, 612500, 625000, 637500, 650000,
+ 662500, 675000, 687500, 700000, 712500,
+ 725000, 737500, 750000, 762500, 775000,
+ 787500, 800000, 812500, 825000, 837500,
+ 850000, 862500, 875000, 887500, 900000,
+ 912500, 925000, 937500, 950000, 962500,
+ 975000, 987500, 1000000, 1012500, 1025000,
+ 1037500, 1050000, 1062500, 1075000, 1087500,
+ 1100000, 1112500, 1125000, 1137500, 1150000,
+ 1162500, 1175000, 1187500, 1200000, 1212500,
+ 1225000, 1237500, 1250000, 1262500, 1275000,
+ 1287500, 1300000, 1312500, 1325000, 1337500,
+ 1350000, 1362500, 1375000, 1387500, 1400000,
+ 1412500, 1425000, 1437500, 1450000, 1462500,
+ 1475000, };
static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 };
static const u32 sw5_val_tbl[] = { 0, 5050000 };
static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 };
@@ -361,13 +350,6 @@ struct cpcap_regulator_data {
u32 mode_cntr;
u32 volt_trans_time; /* in micro seconds */
u32 turn_on_time; /* in micro seconds */
-
- /*
- * Bit difference between lowest value in val_tbl and start of voltage
- * table setting in cpcap. Use this for switchers that have many too
- * many voltages to list in val_tbl.
- */
- u32 bit_offset_from_cpcap_lowest_voltage;
};
#endif /* _CPCAP_H_ */