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| author | Nikhil M Jain <[email protected]> | 2023-07-18 14:27:35 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-07-21 15:32:12 -0400 |
| commit | a72532fa194ed31b559bdd8b287854df0a4903f8 (patch) | |
| tree | b6981028f79b40cc7a85b8bb615704edcb23d66f /scripts | |
| parent | 1f7682383f4334afc21ea62b072392955d201d62 (diff) | |
doc: board: ti: am62x_sk: Add A53 SPL DDR layout
To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.
Signed-off-by: Nikhil M Jain <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions