diff options
36 files changed, 2592 insertions, 325 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d90e02ca4e5..4085d4c2de1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1124,6 +1124,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7988-rfb.dtb \ mt7988-sd-rfb.dtb \ mt8183-pumpkin.dtb \ + mt8371-genio-520-evk.dtb \ + mt8391-genio-720-evk.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/mt8189-pinfunc.h b/arch/arm/dts/mt8189-pinfunc.h new file mode 100644 index 00000000000..df69f50c267 --- /dev/null +++ b/arch/arm/dts/mt8189-pinfunc.h @@ -0,0 +1,1125 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Lei Xue <[email protected]> + * Cathy Xu <[email protected]> + */ + +#ifndef __MT8189_PINFUNC_H +#define __MT8189_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SPIM3_A_CSB (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_I2SOUT0_MCK (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_SCP_SPI0_CS (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SPIM3_A_CLK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I2SOUT0_BCK (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_SCP_SPI0_CK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_SPIM3_A_MO (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPIM3_A_MI (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_I2SOUT0_DO (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_SPIM4_A_CSB (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_I2SIN0_DI (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_SCP_SPI1_CS (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_SPIM4_A_CLK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_I2SIN0_BCK (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_SCP_SPI1_CK (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPIM4_A_MO (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_I2SIN0_LRCK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_SCP_SPI1_MO (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SPIM4_A_MI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_I2SIN0_MCK (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_SCP_SPI1_MI (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SPIM5_A_CSB (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_I2SOUT1_MCK (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_VADSP_UTXD0 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_TP_URXD1_VLP (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SPIM5_A_CLK (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_I2SOUT1_BCK (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_VADSP_URXD0 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPIM5_A_MO (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SRCLKENAI0 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_TP_URTS1_VLP (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPIM5_A_MI (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2SOUT1_DO (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_PWM_vlp (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_UTXD3 (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_CLKM0 (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_CMFLASH0 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_ANT_SEL0 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_DBG_MON_B20 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_URXD3 (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_CLKM1 (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_CMFLASH1 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_ANT_SEL1 (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_DBG_MON_B21 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_UCTS3 (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_CLKM2 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_CMFLASH2 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_ANT_SEL2 (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_DBG_MON_B22 (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_URTS3 (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_CLKM3 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_CMVREF0 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_ANT_SEL3 (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_DBG_MON_B23 (MTK_PIN_NO(15) | 7) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_PWM_0 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_UCTS2 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_DP_TX_HPD (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_CMVREF1 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_ANT_SEL4 (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_B24 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_PWM_1 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_URTS2 (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_EDP_TX_HPD (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_CMVREF2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_PMSR_SMAP (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_B25 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_CMFLASH0 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_CMVREF3 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_UTXD2 (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_DISP_PWM1 (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_I2SIN1_MCK (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A12 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_CMFLASH1 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_CMVREF2 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_URXD2 (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_I2SIN1_BCK (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A13 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_CMFLASH2 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_CMVREF1 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_UCTS2 (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_PERSTN (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_I2SIN1_LRCK (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_DMIC0_DAT1 (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A14 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_CMFLASH3 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CMVREF0 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_URTS2 (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CLKREQN (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_I2SIN1_DI (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_DMIC1_DAT1 (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A15 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_CMMCLK0 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_TP_GPIO4_AO (MTK_PIN_NO(22) | 2) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_CMMCLK1 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_TP_GPIO5_AO (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_PWM_vlp (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_SRCLKENAI0 (MTK_PIN_NO(23) | 6) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_CMMCLK2 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_TP_GPIO6_AO (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_WAKEN (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 6) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_LCM_RST (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_DP_TX_HPD (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_CMFLASH3 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(25) | 5) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_DSI_TE (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_EDP_TX_HPD (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_CMVREF3 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(26) | 5) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_DP_TX_HPD (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_CMVREF4 (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_EXTIF0_ACT (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_ANT_SEL0 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_EDP_TX_HPD (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_EXTIF0_PRI (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_ANT_SEL1 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_DISP_PWM0 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(29) | 5) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_DISP_PWM1 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_PMSR_SMAP (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_ANT_SEL2 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_UTXD0 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 2) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 2) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_UTXD1 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_VADSP_UTXD0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_MD32_1_TXD (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_VADSP_URXD0 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_TP_URXD1_VLP (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_MD32_1_RXD (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_UCTS1 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_VADSP_UTXD0 (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_BT_TXD (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_URXD2 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_URTS1 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_TP_URTS1_VLP (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_VADSP_URXD0 (MTK_PIN_NO(36) | 5) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_UTXD3 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_UCTS0 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_MD32_0_TXD (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_URXD3 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_URTS0 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_MD32_0_RXD (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_JTMS_SEL1 (MTK_PIN_NO(39) | 1) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_JTCK_SEL1 (MTK_PIN_NO(40) | 1) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_JTDI_SEL1 (MTK_PIN_NO(41) | 1) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_JTDO_SEL1 (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_JTRSTn_SEL1 (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_KPCOL0 (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_KPCOL1 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_TP_GPIO0_AO (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SRCLKENAI1 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_DBG_MON_A31 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_KPROW0 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_TP_GPIO1_AO (MTK_PIN_NO(46) | 2) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_KPROW1 (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_TP_GPIO2_AO (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_SRCLKENAI0 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_DBG_MON_A32 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_WAKEN (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_TP_GPIO3_AO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(48) | 3) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_PERSTN (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_CLKREQN (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SCP_SCL0 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SCP_SDA0 (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SCP_SCL1 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_SCL1 (MTK_PIN_NO(53) | 2) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_SCP_SDA1 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_SDA1 (MTK_PIN_NO(54) | 2) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SCL2 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(55) | 3) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SDA2 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(56) | 3) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_SCL3 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(57) | 3) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_SDA3 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(58) | 3) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_SCL4 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(59) | 2) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_SDA4 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(60) | 2) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SCL5 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(61) | 2) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SDA5 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(62) | 2) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SCL6 (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SDA6 (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SCL7 (MTK_PIN_NO(65) | 1) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SDA7 (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SCL8 (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SDA8 (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_SPIM0_CSB (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_SCP_SPI0_CS (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_SPIM0_CLK (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_SCP_SPI0_CK (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_SPIM0_MO (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_SCP_SPI0_MO (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_SPIM0_MI (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_SCP_SPI0_MI (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(72) | 4) +#define PINMUX_GPIO72__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(72) | 6) +#define PINMUX_GPIO72__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(72) | 7) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_SPIM1_CSB (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_SCP_SPI1_CS (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(73) | 3) +#define PINMUX_GPIO73__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(73) | 6) +#define PINMUX_GPIO73__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_SPIM1_CLK (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_SCP_SPI1_CK (MTK_PIN_NO(74) | 2) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_SPIM1_MO (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_SCP_SPI1_MO (MTK_PIN_NO(75) | 2) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_SPIM1_MI (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_SCP_SPI1_MI (MTK_PIN_NO(76) | 2) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_SPIM2_CSB (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_PCM0_SYNC (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_SSUSB_U2SIF_SCL (MTK_PIN_NO(77) | 3) +#define PINMUX_GPIO77__FUNC_DBG_MON_A27 (MTK_PIN_NO(77) | 7) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_SPIM2_CLK (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_PCM0_CLK (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_SSUSB_U2SIF_SDA (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_DBG_MON_A28 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_SPIM2_MO (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_PCM0_DO (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_SSUSB_U2SIF_SCL_1P (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_DBG_MON_A29 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_SPIM2_MI (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_PCM0_DI (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_SSUSB_U2SIF_SDA_1P (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_DBG_MON_A30 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_IDDIG (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B32 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_USB_DRVVBUS (MTK_PIN_NO(82) | 1) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_VBUSVALID (MTK_PIN_NO(83) | 1) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_DBG_MON_A16 (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_DBG_MON_A17 (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_DBG_MON_A18 (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CMVREF4 (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_DBG_MON_A19 (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(88) | 1) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(89) | 1) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(90) | 1) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_SRCLKENA0 (MTK_PIN_NO(92) | 1) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_SRCLKENA1 (MTK_PIN_NO(93) | 1) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(94) | 1) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_RTC32K_CK (MTK_PIN_NO(95) | 1) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_WATCHDOG (MTK_PIN_NO(96) | 1) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(99) | 1) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(100) | 1) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(101) | 1) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(102) | 1) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_I2SIN0_MCK (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SPIM3_B_CSB (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_APU_JTAG_TMS (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_I2SIN0_BCK (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_SPIM3_B_CLK (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_APU_JTAG_TCK (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_I2SIN0_LRCK (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_SPIM3_B_MO (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_APU_JTAG_TDI (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_I2SIN0_DI (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_SPIM3_B_MI (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_APU_JTAG_TDO (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_I2SOUT0_MCK (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_SPIM4_B_CSB (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_APU_JTAG_TRST (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_I2SOUT0_BCK (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_SPIM4_B_CLK (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_EXTIF0_ACT (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_CLKM2 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_DBG_MON_A20 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_I2SOUT0_LRCK (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_SPIM4_B_MO (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_EXTIF0_PRI (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_CLKM3 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DBG_MON_A21 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_I2SOUT0_DO (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_SPIM4_B_MI (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_DBG_MON_A22 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_DMIC0_CLK (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_I2SIN1_MCK (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_I2SOUT1_MCK (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_DBG_MON_A23 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_DMIC0_DAT0 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_I2SIN1_BCK (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_I2SOUT1_BCK (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_DBG_MON_A24 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_DMIC1_CLK (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_I2SIN1_LRCK (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_PMSR_SMAP (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_DBG_MON_A25 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_DMIC1_DAT0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_I2SIN1_DI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_I2SOUT1_DO (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_DBG_MON_A26 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_PCM0_CLK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_PCIE_PHY_I2C_SCL (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_SSUSB_U3PHY_I2C_SCL (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_CMFLASH0 (MTK_PIN_NO(115) | 6) +#define PINMUX_GPIO115__FUNC_EXTIF0_ACT (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_PCM0_SYNC (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_PCIE_PHY_I2C_SDA (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_SSUSB_U3PHY_I2C_SDA (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_CMFLASH1 (MTK_PIN_NO(116) | 6) +#define PINMUX_GPIO116__FUNC_EXTIF0_PRI (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_PCM0_DI (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_DP_TX_HPD (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_SSPXTP_U3PHY_I2C_SCL (MTK_PIN_NO(117) | 4) +#define PINMUX_GPIO117__FUNC_CMVREF0 (MTK_PIN_NO(117) | 6) +#define PINMUX_GPIO117__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_PCM0_DO (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_EDP_TX_HPD (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_SSPXTP_U3PHY_I2C_SDA (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_CMVREF1 (MTK_PIN_NO(118) | 6) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_GBE_TXD3 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_DMIC0_CLK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_LVTS_FOUT (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_ANT_SEL5 (MTK_PIN_NO(119) | 6) +#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_GBE_TXD2 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_DMIC0_DAT0 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_LVTS_SDO (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_ANT_SEL6 (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_DBG_MON_B1 (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_GBE_TXD1 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_DMIC0_DAT1 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_LVTS_26M (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_ANT_SEL7 (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_DBG_MON_B2 (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_GBE_TXD0 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_DMIC1_CLK (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_LVTS_SCF (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ANT_SEL8 (MTK_PIN_NO(122) | 6) +#define PINMUX_GPIO122__FUNC_DBG_MON_B3 (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_GBE_RXD3 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_DMIC1_DAT0 (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_LVTS_SCK (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_ANT_SEL9 (MTK_PIN_NO(123) | 6) +#define PINMUX_GPIO123__FUNC_DBG_MON_B4 (MTK_PIN_NO(123) | 7) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_GBE_RXD2 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_DMIC1_DAT1 (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_LVTS_SDI (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_DBG_MON_B5 (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_GBE_RXD1 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_CLKM2 (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_ANT_SEL11 (MTK_PIN_NO(125) | 6) +#define PINMUX_GPIO125__FUNC_DBG_MON_B6 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_GBE_RXD0 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CLKM3 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(126) | 4) +#define PINMUX_GPIO126__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_ANT_SEL12 (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_DBG_MON_B7 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_GBE_TXC (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_I2SIN1_MCK (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_ANT_SEL13 (MTK_PIN_NO(127) | 6) +#define PINMUX_GPIO127__FUNC_DBG_MON_B8 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_GBE_RXC (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_I2SIN1_BCK (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_ANT_SEL14 (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_DBG_MON_B9 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_GBE_RXDV (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_I2SIN1_LRCK (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_ANT_SEL15 (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_DBG_MON_B10 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_GBE_TXEN (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_I2SIN1_DI (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_ANT_SEL16 (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_B11 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_GBE_MDC (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_CLKM0 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_ANT_SEL17 (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_B12 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_GBE_MDIO (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_CLKM1 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_ANT_SEL18 (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_DBG_MON_B13 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_GBE_TXER (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_GBE_AUX_PPS2 (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_CONN_BT_TXD (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_ANT_SEL19 (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_B14 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_GBE_RXER (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_GBE_AUX_PPS3 (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_APU_JTAG_TMS (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_ANT_SEL20 (MTK_PIN_NO(134) | 6) +#define PINMUX_GPIO134__FUNC_DBG_MON_B15 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_GBE_COL (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_I2SOUT1_MCK (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_APU_JTAG_TCK (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_ANT_SEL21 (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_DBG_MON_B16 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_GBE_INTR (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_I2SOUT1_BCK (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_APU_JTAG_TDI (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_PWM_0 (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_DBG_MON_B17 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_GBE_AUX_PPS0 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_I2SOUT1_LRCK (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_DP_TX_HPD (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_APU_JTAG_TDO (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_PWM_1 (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_DBG_MON_B18 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_GBE_AUX_PPS1 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_I2SOUT1_DO (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_EDP_TX_HPD (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_APU_JTAG_TRST (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_PWM_2 (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_DBG_MON_B19 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_CONN_TOP_CLK (MTK_PIN_NO(139) | 1) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_CONN_TOP_DATA (MTK_PIN_NO(140) | 1) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_CONN_BT_CLK (MTK_PIN_NO(141) | 1) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_CONN_BT_DATA (MTK_PIN_NO(142) | 1) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_CONN_HRST_B (MTK_PIN_NO(143) | 1) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_CONN_WB_PTA (MTK_PIN_NO(144) | 1) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(145) | 1) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(146) | 1) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(147) | 1) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(148) | 1) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(149) | 1) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_SPINOR_CK (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_DMIC0_CLK (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_DP_TX_HPD (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_PWM_0 (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_LVTS_FOUT (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_DBG_MON_B26 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_SPINOR_CS (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_DMIC0_DAT0 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_EDP_TX_HPD (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_PWM_1 (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_LVTS_SDO (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_DBG_MON_B27 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_SPINOR_IO0 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_DMIC0_DAT1 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_UTXD2 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(152) | 4) +#define PINMUX_GPIO152__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_LVTS_26M (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_DBG_MON_B28 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_SPINOR_IO1 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DMIC1_CLK (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_UCTS2 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(153) | 5) +#define PINMUX_GPIO153__FUNC_LVTS_SCF (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_DBG_MON_B29 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_SPINOR_IO2 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DMIC1_DAT0 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_URTS2 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(154) | 4) +#define PINMUX_GPIO154__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_LVTS_SCK (MTK_PIN_NO(154) | 6) +#define PINMUX_GPIO154__FUNC_DBG_MON_B30 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_SPINOR_IO3 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_DMIC1_DAT1 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_URXD2 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_USB_DRVVBUS_4P (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_DISP_PWM1 (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_LVTS_SDI (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B31 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_MSDC0_DAT7 (MTK_PIN_NO(156) | 1) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_MSDC0_DAT6 (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_MSDC0_DAT5 (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_MSDC0_DAT4 (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_MSDC0_RSTB (MTK_PIN_NO(160) | 1) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_MSDC0_CMD (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_MSDC0_CLK (MTK_PIN_NO(162) | 1) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_MSDC0_DAT3 (MTK_PIN_NO(163) | 1) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_MSDC0_DAT2 (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_MSDC0_DAT1 (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_MSDC0_DAT0 (MTK_PIN_NO(166) | 1) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MSDC0_DSL (MTK_PIN_NO(167) | 1) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MSDC1_CMD (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_UCTS1 (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_UDI_TMS (MTK_PIN_NO(168) | 4) +#define PINMUX_GPIO168__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(168) | 5) +#define PINMUX_GPIO168__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(168) | 6) +#define PINMUX_GPIO168__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(168) | 7) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MSDC1_CLK (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_URTS1 (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_UDI_TCK (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC1_DAT0 (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_SPIM5_B_CSB (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_UCTS2 (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_UDI_TDI (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(170) | 6) +#define PINMUX_GPIO170__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC1_DAT1 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_SPIM5_B_CLK (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_URTS2 (MTK_PIN_NO(171) | 3) +#define PINMUX_GPIO171__FUNC_UDI_TDO (MTK_PIN_NO(171) | 4) +#define PINMUX_GPIO171__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(171) | 5) +#define PINMUX_GPIO171__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(171) | 6) +#define PINMUX_GPIO171__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC1_DAT2 (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_SPIM5_B_MO (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_UCTS3 (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_UDI_NTRST (MTK_PIN_NO(172) | 4) +#define PINMUX_GPIO172__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(172) | 5) +#define PINMUX_GPIO172__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(172) | 6) +#define PINMUX_GPIO172__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC1_DAT3 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_SPIM5_B_MI (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_URTS3 (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_CLKM0 (MTK_PIN_NO(173) | 4) +#define PINMUX_GPIO173__FUNC_PWM_2 (MTK_PIN_NO(173) | 5) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC2_CMD (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_UTXD1 (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_VADSP_JTAG0_TMS (MTK_PIN_NO(174) | 4) +#define PINMUX_GPIO174__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(174) | 5) +#define PINMUX_GPIO174__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(174) | 6) +#define PINMUX_GPIO174__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC2_CLK (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(175) | 2) +#define PINMUX_GPIO175__FUNC_URXD1 (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_VADSP_JTAG0_TCK (MTK_PIN_NO(175) | 4) +#define PINMUX_GPIO175__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(175) | 5) +#define PINMUX_GPIO175__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(175) | 6) +#define PINMUX_GPIO175__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_MSDC2_DAT0 (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_SRCLKENAI0 (MTK_PIN_NO(176) | 2) +#define PINMUX_GPIO176__FUNC_UTXD2 (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_VADSP_JTAG0_TDI (MTK_PIN_NO(176) | 4) +#define PINMUX_GPIO176__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(176) | 5) +#define PINMUX_GPIO176__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(176) | 6) +#define PINMUX_GPIO176__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_MSDC2_DAT1 (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_SRCLKENAI1 (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_URXD2 (MTK_PIN_NO(177) | 3) +#define PINMUX_GPIO177__FUNC_VADSP_JTAG0_TDO (MTK_PIN_NO(177) | 4) +#define PINMUX_GPIO177__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(177) | 5) +#define PINMUX_GPIO177__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(177) | 6) +#define PINMUX_GPIO177__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(177) | 7) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_MSDC2_DAT2 (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_UTXD3 (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_VADSP_JTAG0_TRSTN (MTK_PIN_NO(178) | 4) +#define PINMUX_GPIO178__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(178) | 5) +#define PINMUX_GPIO178__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(178) | 6) +#define PINMUX_GPIO178__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(178) | 7) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_MSDC2_DAT3 (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_URXD3 (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_CLKM1 (MTK_PIN_NO(179) | 4) +#define PINMUX_GPIO179__FUNC_PWM_vlp (MTK_PIN_NO(179) | 5) +#define PINMUX_GPIO179__FUNC_TP_GPIO7_AO (MTK_PIN_NO(179) | 7) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_SPMI_P_SCL (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SPMI_P_SDA (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_DDR_PAD_RRESETB (MTK_PIN_NO(182) | 1) + +#endif /* __MT8189_PINFUNC_H */ diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi new file mode 100644 index 00000000000..d246be63293 --- /dev/null +++ b/arch/arm/dts/mt8189.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Macpaul Lin <[email protected]> + */ + +#include <dt-bindings/clock/mediatek,mt8189-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt8189"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + }; + + memory: memory@40000000 { + device_type = "memory"; + /* This memory size is filled in by the bootloader */ + reg = <0 0x40000000 0 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + watchdog: watchdog@1c00a000 { + compatible = "mediatek,mt8391-wdt", + "mediatek,wdt"; + reg = <0 0x1c00a000 0 0x100>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-controller; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + uart0: serial@11001000 { + compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001000 0 0x1000>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8189-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11e70000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC0_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC0>; + clock-names = "source", "hclk", "source_cg"; + interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8189-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11d80000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC1_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC1>; + clock-names = "source", "hclk", "source_cg"; + interrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + clock-controller@1000c000 { + compatible = "mediatek,mt8189-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@14000000 { + compatible = "mediatek,mt8189-dispsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1e980000 { + compatible = "mediatek,mt8189-gce-d", "syscon"; + reg = <0 0x1e980000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1e990000 { + compatible = "mediatek,mt8189-gce-m", "syscon"; + reg = <0 0x1e990000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1e800000 { + compatible = "mediatek,mt8189-mm-infra", "syscon"; + reg = <0 0x1e800000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg_ao_clk: clock-controller@11036000 { + compatible = "mediatek,mt8189-peri-ao", "syscon"; + reg = <0 0x11036000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + topckgen_clk: clock-controller@10000000 { + compatible = "mediatek,mt8189-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8189-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11b50000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11c60000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11ce0000 0 0x1000>, + <0 0x11de0000 0 0x1000>, + <0 0x11e60000 0 0x1000>, + <0 0x1c01e000 0 0x1000>, + <0 0x11f00000 0 0x1000>; + reg-names = "base", + "lm", + "rb0", + "rb1", + "bm0", + "bm1", + "bm2", + "lt0", + "lt1", + "rt", + "eint0", + "eint1", + "eint2", + "eint3", + "eint4"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 182>; + interrupt-controller; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + }; + + pwrap: pwrap@1cc04000 { + compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x1cc04000 0 0x1000>; + reg-names = "pwrap"; + assigned-clocks = <&vlpckgen_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_OSC_D10>; + clocks = <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>, + <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>; + clock-names = "spi", "wrap"; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + vlpcfg_ao_clk: clock-controller@1c00c000 { + compatible = "mediatek,mt8189-vlpcfg-ao", "syscon"; + reg = <0 0x1c00c000 0 0x1000>; + #clock-cells = <1>; + }; + + vlpckgen_clk: clock-controller@1c012000 { + compatible = "mediatek,mt8189-vlpckgen", "syscon"; + reg = <0 0x1c012000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; diff --git a/arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi b/arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi new file mode 100644 index 00000000000..a69e2db5a04 --- /dev/null +++ b/arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "mt8371-genio-common-u-boot.dtsi" diff --git a/arch/arm/dts/mt8371-genio-520-evk.dts b/arch/arm/dts/mt8371-genio-520-evk.dts new file mode 100644 index 00000000000..1ed325eb587 --- /dev/null +++ b/arch/arm/dts/mt8371-genio-520-evk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt8189.dtsi" +#include "mt8371-genio-common.dtsi" + +/ { + model = "MediaTek Genio-520 EVK"; + compatible = "mediatek,mt8371-evk", "mediatek,mt8371", "mediatek,mt8189"; +}; diff --git a/arch/arm/dts/mt8371-genio-common-u-boot.dtsi b/arch/arm/dts/mt8371-genio-common-u-boot.dtsi new file mode 100644 index 00000000000..b7a0c0a82a7 --- /dev/null +++ b/arch/arm/dts/mt8371-genio-common-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + */ + +&mmc1 { + /* U-Boot driver doesn't support UHS yet. */ + /delete-property/ sd-uhs-sdr50; + /delete-property/ sd-uhs-sdr104; + mmc-no-1-8-v; +}; + +/* + * Needed to trigger U-Boot auto-set-voltage. Default voltages for these + * supplies at boot are incorrect and U-Boot MMC drivers don't set them. + */ + +&mt6359_vpa_buck_reg { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi new file mode 100644 index 00000000000..58322193aef --- /dev/null +++ b/arch/arm/dts/mt8371-genio-common.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Macpaul Lin <[email protected]> + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "mt8189.dtsi" +#include "mt8189-pinfunc.h" +#include "mt6359.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + memory@40000000 { + /* 8GB */ + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + dsi_reserved: dsi@60000000 { + reg = <0 0x60000000 0 0x02000000>; + no-map; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc0 { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x1481b>; + cap-mmc-hw-reset; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + max-frequency = <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; + status = "okay"; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&pio { + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO165__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO164__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO163__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO161__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO165__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO164__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO163__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO161__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO167__FUNC_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO171__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO168__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_GPIO2>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO171__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO168__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_GPIO2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_UTXD0>, + <PINMUX_GPIO32__FUNC_URXD0>; + bias-pull-up; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi b/arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi new file mode 100644 index 00000000000..a69e2db5a04 --- /dev/null +++ b/arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "mt8371-genio-common-u-boot.dtsi" diff --git a/arch/arm/dts/mt8391-genio-720-evk.dts b/arch/arm/dts/mt8391-genio-720-evk.dts new file mode 100644 index 00000000000..c8e57433ce6 --- /dev/null +++ b/arch/arm/dts/mt8391-genio-720-evk.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt8189.dtsi" +#include "mt8371-genio-common.dtsi" + +/ { + model = "MediaTek Genio-720 EVK"; + compatible = "mediatek,mt8391-evk", "mediatek,mt8391", "mediatek,mt8189"; +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 671a6cb1cad..b5b06f4e5b2 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -93,6 +93,15 @@ config TARGET_MT8188 USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. +config TARGET_MT8189 + bool "MediaTek MT8189 SoC" + select ARM64 + help + The MediaTek MT8189 is a ARM64-based SoC with a dual-core Cortex-A78 and + a six-core Cortex-A55. It is including UART, SPI, USB3.0 dual role, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR4x + and LPDDR5x options. + config TARGET_MT8195 bool "MediaTek MT8195 SoC" select ARM64 @@ -201,7 +210,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8195 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8189 || TARGET_MT8195 default "lk=1" if TARGET_MT7623 config MTK_TZ_MOVABLE diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index d1f64d61ab9..35f748a70d6 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8188) += mt8188/ +obj-$(CONFIG_TARGET_MT8189) += mt8189/ obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ obj-$(CONFIG_TARGET_MT8512) += mt8512/ diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c index 8e8bc4f9cea..56a41e42df6 100644 --- a/arch/arm/mach-mediatek/cpu.c +++ b/arch/arm/mach-mediatek/cpu.c @@ -8,6 +8,11 @@ #include <init.h> #include <wdt.h> #include <dm/uclass-internal.h> +#include <linux/arm-smccc.h> +#include <linux/types.h> + +#define MTK_SIP_PLAT_BINFO ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, 0x529) int arch_cpu_init(void) { @@ -21,3 +26,53 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +/** + * mediatek_sip_part_name - get the part name + * + * Retrieve the part name of platform description. + * + * This only applicable to SoCs that support SIP plat binfo SMC call. + * + * Returns: the part name or 0 if error or no part name + */ +u32 mediatek_sip_part_name(void) +{ + if (CONFIG_IS_ENABLED(TARGET_MT8188) || CONFIG_IS_ENABLED(TARGET_MT8189) || + CONFIG_IS_ENABLED(TARGET_MT8195) || CONFIG_IS_ENABLED(TARGET_MT8365)) { + struct arm_smccc_res res __maybe_unused; + + arm_smccc_smc(MTK_SIP_PLAT_BINFO, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) + return 0; + + return res.a1; + } + + return 0; +} + +/** + * mediatek_sip_segment_name - get the segment name + * + * Retrieve the segment name of platform description. + * + * This only applicable to SoCs that support SIP plat binfo SMC call. + * + * Returns: the segment name or 0 if error or no segment name + */ +u32 mediatek_sip_segment_name(void) +{ + if (CONFIG_IS_ENABLED(TARGET_MT8188) || CONFIG_IS_ENABLED(TARGET_MT8189) || + CONFIG_IS_ENABLED(TARGET_MT8195) || CONFIG_IS_ENABLED(TARGET_MT8365)) { + struct arm_smccc_res res __maybe_unused; + + arm_smccc_smc(MTK_SIP_PLAT_BINFO, 1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) + return 0; + + return res.a1; + } + + return 0; +} diff --git a/arch/arm/mach-mediatek/cpu.h b/arch/arm/mach-mediatek/cpu.h new file mode 100644 index 00000000000..768284e487f --- /dev/null +++ b/arch/arm/mach-mediatek/cpu.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. + */ + +#ifndef _MACH_MEDIATEK_CPU_H_ +#define _MACH_MEDIATEK_CPU_H_ + +#include <linux/types.h> + +u32 mediatek_sip_segment_name(void); +u32 mediatek_sip_part_name(void); + +#endif /* _MACH_MEDIATEK_CPU_H_ */ diff --git a/arch/arm/mach-mediatek/mt7987/init.c b/arch/arm/mach-mediatek/mt7987/init.c index 6364ab497f7..f16a25843a9 100644 --- a/arch/arm/mach-mediatek/mt7987/init.c +++ b/arch/arm/mach-mediatek/mt7987/init.c @@ -27,14 +27,6 @@ int dram_init(void) return 0; } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - void reset_cpu(ulong addr) { psci_system_reset(); diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 7ff843585ec..7f4d934bfe9 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -26,14 +26,6 @@ int dram_init(void) return 0; } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - void reset_cpu(ulong addr) { psci_system_reset(); diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 8dbf9c3df7e..8797261368e 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -20,23 +20,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - void reset_cpu(void) { psci_system_reset(); diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index 9743e39d582..a48a41f3b97 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -9,6 +9,7 @@ #include <asm/global_data.h> #include <asm/system.h> #include <dm/uclass.h> +#include <linux/kernel.h> #include <linux/sizes.h> #include <wdt.h> @@ -16,33 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - - fdtdec_setup_mem_size_base(); - - /* - * Limit gd->ram_top not exceeding SZ_4G. Some periphals like mmc - * requires DMA buffer allocated below SZ_4G. - * - * Note: SZ_1M is for adjusting gd->relocaddr, the reserved memory for - * u-boot itself. - */ - if (gd->ram_base + gd->ram_size >= SZ_4G) - gd->mon_len = (gd->ram_base + gd->ram_size + SZ_1M) - SZ_4G; - - return 0; + return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) +phys_size_t get_effective_memsize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; + /* + * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like + * MMC requires DMA buffer allocated below SZ_4G. + */ + return min(SZ_4G - gd->ram_base, gd->ram_size); } void reset_cpu(void) diff --git a/arch/arm/mach-mediatek/mt8189/Makefile b/arch/arm/mach-mediatek/mt8189/Makefile new file mode 100644 index 00000000000..886ab7e4eb9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8189/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8189/init.c b/arch/arm/mach-mediatek/mt8189/init.c new file mode 100644 index 00000000000..ec7587c3586 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8189/init.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Chris-QJ Chen <[email protected]> + */ + +#include <fdtdec.h> +#include <stdio.h> +#include <asm/global_data.h> +#include <asm/system.h> +#include <linux/kernel.h> +#include <linux/sizes.h> + +#include "../cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +phys_size_t get_effective_memsize(void) +{ + /* + * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like + * MMC requires DMA buffer allocated below SZ_4G. + */ + return min(SZ_4G - gd->ram_base, gd->ram_size); +} + +void reset_cpu(ulong addr) +{ + if (!CONFIG_IS_ENABLED(SYSRESET)) + psci_system_reset(); +} + +static const char *mediatek_get_segment_name_string(void) +{ + u32 seg = mediatek_sip_segment_name(); + + switch (seg) { + case 0x80: + return "MT8391AV/AZA"; + case 0x81: + return "MT8371AV/AZA"; + case 0x82: + return "MT8371LV/AZA"; + case 0x88: + return "MT8391IV/AZA"; + case 0x89: + return "MT8371IV/AZA"; + default: + return NULL; + } +} + +int print_cpuinfo(void) +{ + const char *seg_name = mediatek_get_segment_name_string(); + u32 part = mediatek_sip_part_name(); + + if (seg_name) + printf("CPU: MediaTek %s\n", seg_name); + else if (part) + printf("CPU: MediaTek part MT%.4x\n", part); + else + printf("CPU: MediaTek MT8189\n"); + + return 0; +} diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c index 0f68c589e9a..e31d4eec0fb 100644 --- a/arch/arm/mach-mediatek/mt8195/init.c +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -9,6 +9,7 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <dm/uclass.h> +#include <linux/kernel.h> #include <linux/sizes.h> #include <wdt.h> @@ -16,33 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - - fdtdec_setup_mem_size_base(); - - /* - * Limit gd->ram_top not exceeding SZ_4G. Some periphals like mmc - * requires DMA buffer allocated below SZ_4G. - * - * Note: SZ_1M is for adjusting gd->relocaddr, the reserved memory for - * u-boot itself. - */ - if (gd->ram_base + gd->ram_size >= SZ_4G) - gd->mon_len = (gd->ram_base + gd->ram_size + SZ_1M) - SZ_4G; - - return 0; + return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) +phys_size_t get_effective_memsize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; + /* + * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like + * MMC requires DMA buffer allocated below SZ_4G. + */ + return min(SZ_4G - gd->ram_base, gd->ram_size); } int mtk_soc_early_init(void) diff --git a/arch/arm/mach-mediatek/mt8365/init.c b/arch/arm/mach-mediatek/mt8365/init.c index fb14a5a1902..1063dbf72a9 100644 --- a/arch/arm/mach-mediatek/mt8365/init.c +++ b/arch/arm/mach-mediatek/mt8365/init.c @@ -18,14 +18,6 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - void reset_cpu(void) { struct udevice *wdt; diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 361c589cbc2..bc1d515fcca 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -35,14 +35,6 @@ phys_size_t get_effective_memsize(void) return gd->ram_size - 6 * SZ_1M; } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - - return 0; -} - void reset_cpu(void) { struct udevice *watchdog_dev = NULL; diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 1d925dd478a..b470910da7f 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -32,14 +32,6 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - static int mtk_pll_early_init(void) { unsigned long pll_rates[] = { diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index 8fa1346021a..9cedf337743 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -24,23 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - return fdtdec_setup_mem_size_base(); } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - void reset_cpu(void) { psci_system_reset(); diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS index 446a9e8e53c..c342ff24330 100644 --- a/board/mediatek/MAINTAINERS +++ b/board/mediatek/MAINTAINERS @@ -1,20 +1,28 @@ +MT8189/MT8371/MT8391 EVK +M: Macpaul Lin <[email protected]> +S: Maintained +F: arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi +F: arch/arm/dts/mt8371-genio-common-u-boot.dtsi +F: arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi +F: configs/mt8189.config +F: configs/mt8371_genio_520_evk_defconfig +F: configs/mt8391_genio_720_evk_defconfig + MT8365 EVK M: Julien Masson <[email protected]> S: Maintained F: configs/mt8365_evk_defconfig -MT8370 EVK -M: Macpaul Lin <[email protected]> -S: Maintained -F: configs/mt8370_evk_defconfig - -MT8390 EVK -M: Julien Masson <[email protected]> +MT8188/MT8370/MT8390 M: Macpaul Lin <[email protected]> +M: Julien Stephan <[email protected]> S: Maintained -F: configs/mt8390_evk_defconfig +F: configs/mt8188.config +F: configs/mt8370_genio_510_evk_defconfig +F: configs/mt8390_genio_700_evk_defconfig -MT8395 EVK +MT8395 M: Macpaul Lin <[email protected]> +M: Julien Stephan <[email protected]> S: Maintained -F: configs/mt8395_evk_defconfig +F: configs/mt8395_genio_1200_evk_defconfig diff --git a/configs/mt8390_evk_defconfig b/configs/mt8188.config index 06437be625e..9dfba6bf99f 100644 --- a/configs/mt8390_evk_defconfig +++ b/configs/mt8188.config @@ -1,14 +1,11 @@ CONFIG_ARM=y -CONFIG_SYS_BOARD="mt8390_evk" CONFIG_COUNTER_FREQUENCY=13000000 CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_TEXT_BASE=0x4c000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8390-genio-700-evk" CONFIG_TARGET_MT8188=y CONFIG_SYS_LOAD_ADDR=0x4c000000 -CONFIG_IDENT_STRING="mt8390-evk" # CONFIG_BOARD_INIT is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y diff --git a/configs/mt8370_evk_defconfig b/configs/mt8189.config index 48d3f64a42e..55c2ccfc01f 100644 --- a/configs/mt8370_evk_defconfig +++ b/configs/mt8189.config @@ -4,25 +4,33 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_TEXT_BASE=0x4c000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8370-genio-510-evk" -CONFIG_TARGET_MT8188=y -CONFIG_MTK_MEM_MAP_DDR_SIZE=0x100000000 +CONFIG_DM_GPIO=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT8189=y +CONFIG_MTK_MEM_MAP_DDR_SIZE=0x200000000 CONFIG_SYS_LOAD_ADDR=0x4c000000 -CONFIG_IDENT_STRING="mt8370-evk" +CONFIG_FIT=y +CONFIG_BOOTSTD_FULL=y # CONFIG_BOARD_INIT is not set CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_OF_UPSTREAM=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CLK=y +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_PINCTRL_MT8188=y +CONFIG_PINCTRL_MT8189=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MTK_PWRAP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MT6359=y CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_WDT=y CONFIG_WDT_MTK=y -# CONFIG_RANDOM_UUID is not set diff --git a/configs/mt8370_genio_510_evk_defconfig b/configs/mt8370_genio_510_evk_defconfig new file mode 100644 index 00000000000..e3530571cc4 --- /dev/null +++ b/configs/mt8370_genio_510_evk_defconfig @@ -0,0 +1,5 @@ +#include <configs/mt8188.config> + +CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8370-genio-510-evk" +CONFIG_MTK_MEM_MAP_DDR_SIZE=0x100000000 +CONFIG_IDENT_STRING="mt8370-genio-510-evk" diff --git a/configs/mt8371_genio_520_evk_defconfig b/configs/mt8371_genio_520_evk_defconfig new file mode 100644 index 00000000000..9a5e68e48ee --- /dev/null +++ b/configs/mt8371_genio_520_evk_defconfig @@ -0,0 +1,4 @@ +#include <configs/mt8189.config> + +CONFIG_DEFAULT_DEVICE_TREE="mt8371-genio-520-evk" +CONFIG_DEFAULT_FDT_FILE="mt8371-genio-520-evk" diff --git a/configs/mt8390_genio_700_evk_defconfig b/configs/mt8390_genio_700_evk_defconfig new file mode 100644 index 00000000000..0b07e3be2c4 --- /dev/null +++ b/configs/mt8390_genio_700_evk_defconfig @@ -0,0 +1,4 @@ +#include <configs/mt8188.config> + +CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8390-genio-700-evk" +CONFIG_IDENT_STRING="mt8390-genio-700-evk" diff --git a/configs/mt8391_genio_720_evk_defconfig b/configs/mt8391_genio_720_evk_defconfig new file mode 100644 index 00000000000..3fcd08be50a --- /dev/null +++ b/configs/mt8391_genio_720_evk_defconfig @@ -0,0 +1,4 @@ +#include <configs/mt8189.config> + +CONFIG_DEFAULT_DEVICE_TREE="mt8391-genio-720-evk" +CONFIG_DEFAULT_FDT_FILE="mt8391-genio-720-evk" diff --git a/configs/mt8395_evk_defconfig b/configs/mt8395_genio_1200_evk_defconfig index 2edf3cb3e35..2d73af353f7 100644 --- a/configs/mt8395_evk_defconfig +++ b/configs/mt8395_genio_1200_evk_defconfig @@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8395-genio-1200-evk" CONFIG_TARGET_MT8195=y CONFIG_SYS_LOAD_ADDR=0x60000000 -CONFIG_IDENT_STRING=" mt8395-evk" +CONFIG_IDENT_STRING="mt8395-genio-1200-evk" # CONFIG_BOARD_INIT is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index fec908728c0..9e640059f11 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -287,12 +287,16 @@ enum { CLK_PAD_CLK32K, CLK_PAD_CLK26M, CLK_PAD_ULPOSC, + CLK_PAD_CLK13M, + CLK_PAD_AUD_ADC_EXT, }; static ulong ext_clock_rates[] = { [CLK_PAD_CLK32K] = 32000, [CLK_PAD_CLK26M] = 26 * MHZ, [CLK_PAD_ULPOSC] = 260 * MHZ, + [CLK_PAD_CLK13M] = 13 * MHZ, + [CLK_PAD_AUD_ADC_EXT] = 260 * MHZ, }; #define MT8189_PLL_FMAX (3800UL * MHZ) @@ -1637,6 +1641,258 @@ static const struct mtk_gate mminfra_config_clks[] = { GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17), }; +static const struct mtk_parent vlp_26m_oscd10_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_vadsp_vowpll_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VOWPLL), +}; + +static const struct mtk_parent vlp_sspm_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_aud_adc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VOWPLL), + EXT_PARENT(CLK_PAD_AUD_ADC_EXT), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_scp_iic_spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_vadsp_uarthub_b_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), +}; + +static const struct mtk_parent vlp_axi_kp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), +}; + +static const struct mtk_parent vlp_sspm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vlp_pwm_vlp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D4), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), +}; + +static const struct mtk_parent vlp_pwrap_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D7), + TOP_PARENT(CLK_TOP_OSC_D8), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), +}; + +static const struct mtk_parent vlp_vadsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D20), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D2), + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent vlp_scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + APMIXED_PARENT(CLK_APMIXED_APLL1), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_spmi_p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_OSC_D8), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent vlp_camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D20), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_composite vlp_ck_muxes[] = { + /* VLP_CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, vlp_scp_parents, + 0x008, 0x00c, 0x010, 0, 4, 7, 0x04, 0), + MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_pwrap_ulposc_parents, + 0x008, 0x00c, 0x010, 8, 3, 0x04, 1), + MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_spmi_p_parents, + 0x008, 0x00c, 0x010, 16, 4, 0x04, 2), + MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_26m_oscd10_parents, + 0x008, 0x00c, 0x010, 24, 1, 0x04, 3), + /* VLP_CLK_CFG_1 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_pwm_vlp_parents, + 0x014, 0x018, 0x01c, 0, 3, 0x04, 4), + MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_axi_kp_parents, + 0x014, 0x018, 0x01c, 8, 3, 0x04, 5), + MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_26m_oscd10_parents, + 0x014, 0x018, 0x01c, 16, 1, 0x04, 6), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, vlp_sspm_parents, + 0x014, 0x018, 0x01c, 24, 3, 0x04, 7), + /* VLP_CLK_CFG_2 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_26m_oscd10_parents, + 0x020, 0x024, 0x028, 0, 1, 0x04, 8), + MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, vlp_26m_oscd10_parents, + 0x020, 0x024, 0x028, 8, 1, 0x04, 9), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_scp_iic_spi_parents, + 0x020, 0x024, 0x028, 16, 2, 0x04, 10), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_scp_iic_spi_parents, + 0x020, 0x024, 0x028, 24, 2, 0x04, 11), + /* VLP_CLK_CFG_3 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, + vlp_scp_iic_spi_parents, + 0x02c, 0x030, 0x034, 0, 2, 0x04, 12), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + vlp_scp_iic_spi_parents, + 0x02c, 0x030, 0x034, 8, 2, 0x04, 13), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_sspm_ulposc_parents, + 0x02c, 0x030, 0x034, 16, 2, 0x04, 14), + MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_26m_oscd10_parents, + 0x02c, 0x030, 0x034, 24, 1, 0x04, 15), + /* VLP_CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, vlp_vadsp_parents, + 0x038, 0x03c, 0x040, 0, 3, 7, 0x04, 16), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL, + vlp_vadsp_vowpll_parents, + 0x038, 0x03c, 0x040, 8, 1, 15, 0x04, 17), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL, + vlp_vadsp_uarthub_b_parents, + 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_camtg_parents, + 0x038, 0x03c, 0x040, 24, 4, 31, 0x04, 19), + /* VLP_CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_camtg_parents, + 0x044, 0x048, 0x04c, 0, 4, 7, 0x04, 20), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_camtg_parents, + 0x044, 0x048, 0x04c, 8, 4, 15, 0x04, 21), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_aud_adc_parents, + 0x044, 0x048, 0x04c, 16, 2, 23, 0x04, 22), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_axi_kp_parents, + 0x044, 0x048, 0x04c, 24, 3, 31, 0x04, 23), +}; + +static const struct mtk_gate_regs vlp_ck_gate_regs = { + .set_ofs = 0x1f4, + .clr_ofs = 0x1f8, + .sta_ofs = 0x1f0, +}; + +#define GATE_VLP_CK(id, parent, shift, flags) \ + GATE_FLAGS(id, parent, &vlp_ck_gate_regs, shift, flags | CLK_GATE_NO_SETCLR_INV) + +#define GATE_VLP_CK_EXT(id, parent, shift) \ + GATE_VLP_CK(id, parent, shift, CLK_PARENT_EXT) + +#define GATE_VLP_CK_TOP(id, parent, shift) \ + GATE_VLP_CK(id, parent, shift, CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate vlp_ck_gates[] = { + GATE_VLP_CK_EXT(CLK_VLP_CK_VADSYS_VLP_26M_EN, CLK_PAD_CLK26M, 1), + GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_13M_EN, CLK_PAD_CLK13M, 4), + GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_26M_EN, CLK_PAD_CLK26M, 5), + GATE_VLP_CK_TOP(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, CLK_TOP_OSC_D10, 11), +}; + +static const struct mtk_gate_regs vlpcfg_ao_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x4, + .sta_ofs = 0x4, +}; + +/* + * REVISIT: this is currently the only clock tree using the infrasys ops so we + * are using it instead of introducing a new parent in the core code. Instead, + * we should eventually rework the core code to do a better job of supporting + * arbitrary parent trees. + */ +#define CLK_PARENT_VLP_CK CLK_PARENT_INFRASYS + +#define GATE_VLPCFG_AO(id, parent, shift, flags) \ + GATE_FLAGS(id, parent, &vlpcfg_ao_regs, shift, flags | CLK_GATE_NO_SETCLR_INV) + +#define GATE_VLPCFG_AO_EXT(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_EXT) + +#define GATE_VLPCFG_AO_TOP(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_TOPCKGEN) + +#define GATE_VLPCFG_AO_VLP(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_VLP_CK) + +static const struct mtk_gate vlpcfg_ao_clks[] = { + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 12), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 11), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 10), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DVFSRC, CLK_VLP_CK_DVFSRC_SEL, 9), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PWM_VLP, CLK_VLP_CK_PWM_VLP_SEL, 8), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SRCK, CLK_VLP_CK_SRCK_SEL, 7), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_F26M, CLK_VLP_CK_SSPM_F26M_SEL, 4), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SSPM_F32K, CLK_PAD_CLK32K, 3), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_ULPOSC, CLK_VLP_CK_SSPM_ULPOSC_SEL, 2), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_32K_COM, CLK_PAD_CLK32K, 1), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_26M_COM, CLK_PAD_CLK26M, 0), +}; + static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, @@ -1659,6 +1915,17 @@ static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { .num_gates = ARRAY_SIZE(top_gates), }; +static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .muxes_offs = CLK_VLP_CK_SCP_SEL, + .gates_offs = CLK_VLP_CK_VADSYS_VLP_26M_EN, + .muxes = vlp_ck_muxes, + .gates = vlp_ck_gates, + .num_muxes = ARRAY_SIZE(vlp_ck_muxes), + .num_gates = ARRAY_SIZE(vlp_ck_gates), +}; + static const struct udevice_id mt8189_apmixed[] = { { .compatible = "mediatek,mt8189-apmixedsys", }, { } @@ -1669,6 +1936,11 @@ static const struct udevice_id mt8189_topckgen_compat[] = { { } }; +static const struct udevice_id mt8189_vlpckgen[] = { + { .compatible = "mediatek,mt8189-vlpckgen", }, + { } +}; + struct mt8189_gate_clk_data { const struct mtk_gate *gates; int num_gates; @@ -1683,12 +1955,14 @@ GATE_CLK_DATA(perao_clks); GATE_CLK_DATA(imp_clks); GATE_CLK_DATA(mm_clks); GATE_CLK_DATA(mminfra_config_clks); +GATE_CLK_DATA(vlpcfg_ao_clks); static const struct udevice_id of_match_mt8189_clk_gate[] = { { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, + { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data }, { } }; @@ -1702,6 +1976,11 @@ static int mt8189_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree); } +static int mt8189_infrasys_probe(struct udevice *dev) +{ + return mtk_common_clk_infrasys_init(dev, &mt8189_vlpckgen_clk_tree); +} + static int mt8189_clk_gate_probe(struct udevice *dev) { struct mt8189_gate_clk_data *data; @@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; +U_BOOT_DRIVER(mtk_clk_vlpckgen) = { + .name = "mt8189-vlpckgen", + .id = UCLASS_CLK, + .of_match = mt8189_vlpckgen, + .probe = mt8189_infrasys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + U_BOOT_DRIVER(mtk_clk_gate) = { .name = "mt8189-gate-clk", .id = UCLASS_CLK, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index a64440d8bb3..b01533ed80b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1015,6 +1015,29 @@ static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = { PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3), }; +static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = { + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00B0, 0, 3), /* SCP_SCL0 */ + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00B0, 6, 3), /* SCP_SDA0 */ + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00B0, 3, 3), /* SCP_SCL1 */ + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00B0, 9, 3), /* SCP_SDA1 */ + PIN_FIELD_BASE(55, IO_BASE_LM, 0x00B0, 0, 3), /* SCL2 */ + PIN_FIELD_BASE(56, IO_BASE_LM, 0x00B0, 3, 3), /* SDA2 */ + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00B0, 0, 3), /* SCL3 */ + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00B0, 12, 3), /* SDA3 */ + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00B0, 3, 3), /* SCL4 */ + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00B0, 15, 3), /* SDA4 */ + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00B0, 6, 3), /* SCL5 */ + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00B0, 18, 3), /* SDA5 */ + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00B0, 9, 3), /* SCL6 */ + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00B0, 21, 3), /* SDA6 */ + PIN_FIELD_BASE(65, IO_BASE_RT, 0x00E0, 0, 3), /* SCL7 */ + PIN_FIELD_BASE(66, IO_BASE_RT, 0x00E0, 6, 3), /* SDA7 */ + PIN_FIELD_BASE(67, IO_BASE_RT, 0x00E0, 3, 3), /* SCL8 */ + PIN_FIELD_BASE(68, IO_BASE_RT, 0x00E0, 9, 3), /* SDA8 */ + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0110, 0, 3), /* SPMI_P_SCL */ + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0110, 3, 3), /* SPMI_P_SDA */ +}; + static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range), @@ -1028,6 +1051,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range), [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range), [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range), }; static const char * const mt8189_pinctrl_register_base_names[] = { @@ -1048,198 +1072,222 @@ static const char * const mt8189_pinctrl_register_base_names[] = { [IO_BASE_EINT4] = "eint4", }; +#define MT8189_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8189_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define MT8189_TYPE2_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2) + static const struct mtk_pin_desc mt8189_pins[] = { - MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0), + MT8189_TYPE0_PIN(0, "GPIO00"), + MT8189_TYPE0_PIN(1, "GPIO01"), + MT8189_TYPE0_PIN(2, "GPIO02"), + MT8189_TYPE0_PIN(3, "GPIO03"), + MT8189_TYPE0_PIN(4, "GPIO04"), + MT8189_TYPE0_PIN(5, "GPIO05"), + MT8189_TYPE0_PIN(6, "GPIO06"), + MT8189_TYPE0_PIN(7, "GPIO07"), + MT8189_TYPE0_PIN(8, "GPIO08"), + MT8189_TYPE0_PIN(9, "GPIO09"), + MT8189_TYPE0_PIN(10, "GPIO10"), + MT8189_TYPE0_PIN(11, "GPIO11"), + MT8189_TYPE0_PIN(12, "GPIO12"), + MT8189_TYPE0_PIN(13, "GPIO13"), + MT8189_TYPE0_PIN(14, "GPIO14"), + MT8189_TYPE0_PIN(15, "GPIO15"), + MT8189_TYPE0_PIN(16, "GPIO16"), + MT8189_TYPE0_PIN(17, "GPIO17"), + MT8189_TYPE0_PIN(18, "GPIO18"), + MT8189_TYPE0_PIN(19, "GPIO19"), + MT8189_TYPE0_PIN(20, "GPIO20"), + MT8189_TYPE0_PIN(21, "GPIO21"), + MT8189_TYPE0_PIN(22, "GPIO22"), + MT8189_TYPE0_PIN(23, "GPIO23"), + MT8189_TYPE0_PIN(24, "GPIO24"), + MT8189_TYPE0_PIN(25, "GPIO25"), + MT8189_TYPE0_PIN(26, "GPIO26"), + MT8189_TYPE0_PIN(27, "GPIO27"), + MT8189_TYPE0_PIN(28, "GPIO28"), + MT8189_TYPE0_PIN(29, "GPIO29"), + MT8189_TYPE0_PIN(30, "GPIO30"), + MT8189_TYPE0_PIN(31, "GPIO31"), + MT8189_TYPE0_PIN(32, "GPIO32"), + MT8189_TYPE0_PIN(33, "GPIO33"), + MT8189_TYPE0_PIN(34, "GPIO34"), + MT8189_TYPE0_PIN(35, "GPIO35"), + MT8189_TYPE0_PIN(36, "GPIO36"), + MT8189_TYPE0_PIN(37, "GPIO37"), + MT8189_TYPE0_PIN(38, "GPIO38"), + MT8189_TYPE0_PIN(39, "GPIO39"), + MT8189_TYPE0_PIN(40, "GPIO40"), + MT8189_TYPE0_PIN(41, "GPIO41"), + MT8189_TYPE0_PIN(42, "GPIO42"), + MT8189_TYPE0_PIN(43, "GPIO43"), + MT8189_TYPE1_PIN(44, "GPIO44"), + MT8189_TYPE1_PIN(45, "GPIO45"), + MT8189_TYPE1_PIN(46, "GPIO46"), + MT8189_TYPE1_PIN(47, "GPIO47"), + MT8189_TYPE0_PIN(48, "GPIO48"), + MT8189_TYPE0_PIN(49, "GPIO49"), + MT8189_TYPE0_PIN(50, "GPIO50"), + MT8189_TYPE2_PIN(51, "GPIO51"), + MT8189_TYPE2_PIN(52, "GPIO52"), + MT8189_TYPE2_PIN(53, "GPIO53"), + MT8189_TYPE2_PIN(54, "GPIO54"), + MT8189_TYPE2_PIN(55, "GPIO55"), + MT8189_TYPE2_PIN(56, "GPIO56"), + MT8189_TYPE2_PIN(57, "GPIO57"), + MT8189_TYPE2_PIN(58, "GPIO58"), + MT8189_TYPE2_PIN(59, "GPIO59"), + MT8189_TYPE2_PIN(60, "GPIO60"), + MT8189_TYPE2_PIN(61, "GPIO61"), + MT8189_TYPE2_PIN(62, "GPIO62"), + MT8189_TYPE2_PIN(63, "GPIO63"), + MT8189_TYPE2_PIN(64, "GPIO64"), + MT8189_TYPE2_PIN(65, "GPIO65"), + MT8189_TYPE2_PIN(66, "GPIO66"), + MT8189_TYPE2_PIN(67, "GPIO67"), + MT8189_TYPE2_PIN(68, "GPIO68"), + MT8189_TYPE0_PIN(69, "GPIO69"), + MT8189_TYPE0_PIN(70, "GPIO70"), + MT8189_TYPE0_PIN(71, "GPIO71"), + MT8189_TYPE0_PIN(72, "GPIO72"), + MT8189_TYPE0_PIN(73, "GPIO73"), + MT8189_TYPE0_PIN(74, "GPIO74"), + MT8189_TYPE0_PIN(75, "GPIO75"), + MT8189_TYPE0_PIN(76, "GPIO76"), + MT8189_TYPE0_PIN(77, "GPIO77"), + MT8189_TYPE0_PIN(78, "GPIO78"), + MT8189_TYPE0_PIN(79, "GPIO79"), + MT8189_TYPE0_PIN(80, "GPIO80"), + MT8189_TYPE0_PIN(81, "GPIO81"), + MT8189_TYPE0_PIN(82, "GPIO82"), + MT8189_TYPE0_PIN(83, "GPIO83"), + MT8189_TYPE0_PIN(84, "GPIO84"), + MT8189_TYPE0_PIN(85, "GPIO85"), + MT8189_TYPE0_PIN(86, "GPIO86"), + MT8189_TYPE0_PIN(87, "GPIO87"), + MT8189_TYPE0_PIN(88, "GPIO88"), + MT8189_TYPE0_PIN(89, "GPIO89"), + MT8189_TYPE0_PIN(90, "GPIO90"), + MT8189_TYPE0_PIN(91, "GPIO91"), + MT8189_TYPE0_PIN(92, "GPIO92"), + MT8189_TYPE0_PIN(93, "GPIO93"), + MT8189_TYPE0_PIN(94, "GPIO94"), + MT8189_TYPE0_PIN(95, "GPIO95"), + MT8189_TYPE0_PIN(96, "GPIO96"), + MT8189_TYPE0_PIN(97, "GPIO97"), + MT8189_TYPE0_PIN(98, "GPIO98"), + MT8189_TYPE0_PIN(99, "GPIO99"), + MT8189_TYPE0_PIN(100, "GPIO100"), + MT8189_TYPE0_PIN(101, "GPIO101"), + MT8189_TYPE0_PIN(102, "GPIO102"), + MT8189_TYPE0_PIN(103, "GPIO103"), + MT8189_TYPE0_PIN(104, "GPIO104"), + MT8189_TYPE0_PIN(105, "GPIO105"), + MT8189_TYPE0_PIN(106, "GPIO106"), + MT8189_TYPE0_PIN(107, "GPIO107"), + MT8189_TYPE0_PIN(108, "GPIO108"), + MT8189_TYPE0_PIN(109, "GPIO109"), + MT8189_TYPE0_PIN(110, "GPIO110"), + MT8189_TYPE0_PIN(111, "GPIO111"), + MT8189_TYPE0_PIN(112, "GPIO112"), + MT8189_TYPE0_PIN(113, "GPIO113"), + MT8189_TYPE0_PIN(114, "GPIO114"), + MT8189_TYPE0_PIN(115, "GPIO115"), + MT8189_TYPE0_PIN(116, "GPIO116"), + MT8189_TYPE0_PIN(117, "GPIO117"), + MT8189_TYPE0_PIN(118, "GPIO118"), + MT8189_TYPE0_PIN(119, "GPIO119"), + MT8189_TYPE0_PIN(120, "GPIO120"), + MT8189_TYPE0_PIN(121, "GPIO121"), + MT8189_TYPE0_PIN(122, "GPIO122"), + MT8189_TYPE0_PIN(123, "GPIO123"), + MT8189_TYPE0_PIN(124, "GPIO124"), + MT8189_TYPE0_PIN(125, "GPIO125"), + MT8189_TYPE0_PIN(126, "GPIO126"), + MT8189_TYPE0_PIN(127, "GPIO127"), + MT8189_TYPE0_PIN(128, "GPIO128"), + MT8189_TYPE0_PIN(129, "GPIO129"), + MT8189_TYPE0_PIN(130, "GPIO130"), + MT8189_TYPE0_PIN(131, "GPIO131"), + MT8189_TYPE0_PIN(132, "GPIO132"), + MT8189_TYPE0_PIN(133, "GPIO133"), + MT8189_TYPE0_PIN(134, "GPIO134"), + MT8189_TYPE0_PIN(135, "GPIO135"), + MT8189_TYPE0_PIN(136, "GPIO136"), + MT8189_TYPE0_PIN(137, "GPIO137"), + MT8189_TYPE0_PIN(138, "GPIO138"), + MT8189_TYPE0_PIN(139, "GPIO139"), + MT8189_TYPE0_PIN(140, "GPIO140"), + MT8189_TYPE0_PIN(141, "GPIO141"), + MT8189_TYPE0_PIN(142, "GPIO142"), + MT8189_TYPE0_PIN(143, "GPIO143"), + MT8189_TYPE0_PIN(144, "GPIO144"), + MT8189_TYPE0_PIN(145, "GPIO145"), + MT8189_TYPE0_PIN(146, "GPIO146"), + MT8189_TYPE0_PIN(147, "GPIO147"), + MT8189_TYPE0_PIN(148, "GPIO148"), + MT8189_TYPE0_PIN(149, "GPIO149"), + MT8189_TYPE0_PIN(150, "GPIO150"), + MT8189_TYPE0_PIN(151, "GPIO151"), + MT8189_TYPE0_PIN(152, "GPIO152"), + MT8189_TYPE0_PIN(153, "GPIO153"), + MT8189_TYPE0_PIN(154, "GPIO154"), + MT8189_TYPE0_PIN(155, "GPIO155"), + MT8189_TYPE1_PIN(156, "GPIO156"), + MT8189_TYPE1_PIN(157, "GPIO157"), + MT8189_TYPE1_PIN(158, "GPIO158"), + MT8189_TYPE1_PIN(159, "GPIO159"), + MT8189_TYPE1_PIN(160, "GPIO160"), + MT8189_TYPE1_PIN(161, "GPIO161"), + MT8189_TYPE1_PIN(162, "GPIO162"), + MT8189_TYPE1_PIN(163, "GPIO163"), + MT8189_TYPE1_PIN(164, "GPIO164"), + MT8189_TYPE1_PIN(165, "GPIO165"), + MT8189_TYPE1_PIN(166, "GPIO166"), + MT8189_TYPE1_PIN(167, "GPIO167"), + MT8189_TYPE1_PIN(168, "GPIO168"), + MT8189_TYPE1_PIN(169, "GPIO169"), + MT8189_TYPE1_PIN(170, "GPIO170"), + MT8189_TYPE1_PIN(171, "GPIO171"), + MT8189_TYPE1_PIN(172, "GPIO172"), + MT8189_TYPE1_PIN(173, "GPIO173"), + MT8189_TYPE1_PIN(174, "GPIO174"), + MT8189_TYPE1_PIN(175, "GPIO175"), + MT8189_TYPE1_PIN(176, "GPIO176"), + MT8189_TYPE1_PIN(177, "GPIO177"), + MT8189_TYPE1_PIN(178, "GPIO178"), + MT8189_TYPE1_PIN(179, "GPIO179"), + MT8189_TYPE2_PIN(180, "GPIO180"), + MT8189_TYPE2_PIN(181, "GPIO181"), + MT8189_TYPE0_PIN(182, "GPIO182"), }; static const struct mtk_io_type_desc mt8189_io_type_desc[] = { [IO_TYPE_GRP0] = { .name = "mt8189", - .bias_set = mtk_pinconf_bias_set_v1, + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd, + }, + [IO_TYPE_GRP1] = { + .name = "MSDC", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pupd_r1_r0, + }, + [IO_TYPE_GRP2] = { + .name = "I2C", + .bias_set = mtk_pinconf_bias_set_pu_pd_rsel, .drive_set = mtk_pinconf_drive_set_v1, .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd_rsel, }, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index d152e216634..cfffbaeef84 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -237,9 +237,39 @@ static int mtk_get_pin_io_type(struct udevice *dev, int pin, io_type->bias_set = priv->soc->io_type[io_n].bias_set; io_type->drive_set = priv->soc->io_type[io_n].drive_set; io_type->input_enable = priv->soc->io_type[io_n].input_enable; + io_type->get_pinconf = priv->soc->io_type[io_n].get_pinconf; return 0; } + +static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + struct mtk_io_type_desc io_type; + int err, pos; + + /* If we fail to get the type, then we just don't add any more info. */ + if (mtk_get_pin_io_type(dev, pin, &io_type)) + return 0; + + pos = snprintf(buf, size, " (%s)", io_type.name); + if (pos >= size) + return pos; + + if (io_type.get_pinconf) { + err = io_type.get_pinconf(dev, pin, buf + pos, size - pos); + if (err < 0) + return err; + + pos += err; + } + + return pos; +} +#else +static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + return 0; +} #endif static int mtk_get_groups_count(struct udevice *dev) @@ -270,12 +300,20 @@ static int mtk_get_pins_count(struct udevice *dev) static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector, char *buf, int size) { - int val, err; + int val, err, pos; + err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val); if (err) return err; - snprintf(buf, size, "Aux Func.%d", val); + pos = snprintf(buf, size, "Aux Func.%d", val); + if (pos >= size) + return 0; + + err = mtk_pinconf_get(dev, selector, buf + pos, size - pos); + if (err < 0) + return err; + return 0; } @@ -450,6 +488,20 @@ int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, return 0; } +int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) +{ + int err; + + /* val is expected to be one of MTK_PULL_SET_RSEL_XXX */ + + err = mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val); + if (err) + return err; + + return mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_RSEL, val & 0x7); +} + int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val) { int err; @@ -656,6 +708,55 @@ static int mtk_pinconf_group_set(struct udevice *dev, return 0; } + +int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int err, pu, pd; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PU, &pu); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PD, &pd); + if (err) + return err; + + return snprintf(buf, size, " PU:%d PD:%d", pu, pd); +} + +int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int err, r0, r1, pupd; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PUPD, &pupd); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R1, &r1); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R0, &r0); + if (err) + return err; + + return snprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); +} + +int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int pos, err, rsel; + + pos = mtk_pinconf_get_pu_pd(dev, pin, buf, size); + if (pos < 0 || pos >= size) + return pos; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_RSEL, &rsel); + if (err) + return err; + + return pos + snprintf(buf + pos, size - pos, " RSEL:%d", rsel); +} #endif static int mtk_pinctrl_pinmux_property_set(struct udevice *dev, u32 pinmux_group) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 58f13613633..bd17964090a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -67,6 +67,7 @@ enum { PINCTRL_PIN_REG_PUPD, PINCTRL_PIN_REG_R0, PINCTRL_PIN_REG_R1, + PINCTRL_PIN_REG_RSEL, PINCTRL_PIN_REG_MAX, }; @@ -203,6 +204,7 @@ struct mtk_io_type_desc { bool pullup, u32 val); int (*drive_set)(struct udevice *dev, u32 pin, u32 arg); int (*input_enable)(struct udevice *dev, u32 pin, u32 arg); + int (*get_pinconf)(struct udevice *dev, u32 pin, char *buf, size_t size); #endif }; @@ -253,6 +255,8 @@ int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); +int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, @@ -260,6 +264,9 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg); int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg); int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg); +int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size); +int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size); +int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size); #endif |