diff options
Diffstat (limited to 'arch/arm/dts/mt8371-genio-common.dtsi')
| -rw-r--r-- | arch/arm/dts/mt8371-genio-common.dtsi | 243 |
1 files changed, 243 insertions, 0 deletions
diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi new file mode 100644 index 00000000000..58322193aef --- /dev/null +++ b/arch/arm/dts/mt8371-genio-common.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Macpaul Lin <[email protected]> + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "mt8189.dtsi" +#include "mt8189-pinfunc.h" +#include "mt6359.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + memory@40000000 { + /* 8GB */ + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + dsi_reserved: dsi@60000000 { + reg = <0 0x60000000 0 0x02000000>; + no-map; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc0 { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x1481b>; + cap-mmc-hw-reset; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + max-frequency = <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; + status = "okay"; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&pio { + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO165__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO164__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO163__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO161__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO165__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO164__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO163__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO161__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO167__FUNC_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO171__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO168__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_GPIO2>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO171__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO172__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO173__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO168__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_GPIO2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_UTXD0>, + <PINMUX_GPIO32__FUNC_URXD0>; + bias-pull-up; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>; +}; |