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-rw-r--r--arch/arm/cpu/arm926ejs/mxs/Makefile14
-rw-r--r--arch/arm/cpu/armv7/Kconfig26
-rw-r--r--arch/arm/cpu/armv7/ls102xa/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c7
-rw-r--r--arch/arm/cpu/armv8/Kconfig18
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c187
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig6
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c148
-rw-r--r--arch/arm/cpu/armv8/fwcall.c15
-rw-r--r--arch/arm/cpu/u-boot.lds2
10 files changed, 253 insertions, 178 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 0df501e91db..6bd95a5185b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -26,7 +26,7 @@ MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
#
quiet_cmd_mkivt_mxs = MXSIVT $@
cmd_mkivt_mxs = \
- sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \
+ sz=`expr \`stat -c "%s" $<\` + 64 + 3904 + 128` ; \
echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \
tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \
sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
@@ -34,15 +34,15 @@ cmd_mkivt_mxs = \
# Align binary to 64B
quiet_cmd_mkalign_mxs = MXSALGN $@
cmd_mkalign_mxs = \
- dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \
- mv $@ $^
+ dd if=$< of=$@ ibs=64 conv=sync 2>/dev/null && \
+ mv $@ $<
# Assemble the CSF file
quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
cmd_mkcsfreq_mxs = \
- ivt=$(word 1,$^) ; \
- bin=$(word 2,$^) ; \
- csf=$(word 3,$^) ; \
+ ivt=$(word 1,$(real-prereqs)) ; \
+ bin=$(word 2,$(real-prereqs)) ; \
+ csf=$(word 3,$(real-prereqs)) ; \
sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \
sed '/^\#\#Blocks/ d' > $@ ; \
echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
@@ -50,7 +50,7 @@ cmd_mkcsfreq_mxs = \
# Sign files
quiet_cmd_mkcst_mxs = MXSCST $@
-cmd_mkcst_mxs = cst -o $@ < $^ \
+cmd_mkcst_mxs = cst -o $@ < $< \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 3a3c1784e18..18e7aed94d9 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -13,19 +13,19 @@ config ARMV7_NONSEC
bool "Enable support for booting in non-secure mode" if EXPERT
depends on CPU_V7_HAS_NONSEC
default y
- ---help---
- Say Y here to enable support for booting in non-secure / SVC mode.
+ help
+ Say Y here to enable support for booting in non-secure / SVC mode.
config ARMV7_BOOT_SEC_DEFAULT
bool "Boot in secure mode by default" if EXPERT
depends on ARMV7_NONSEC
default y if ARCH_TEGRA
- ---help---
- Say Y here to boot in secure mode by default even if non-secure mode
- is supported. This option is useful to boot kernels which do not
- suppport booting in non-secure mode. Only set this if you need it.
- This can be overridden at run-time by setting the bootm_boot_mode env.
- variable to "sec" or "nonsec".
+ help
+ Say Y here to boot in secure mode by default even if non-secure mode
+ is supported. This option is useful to boot kernels which do not
+ support booting in non-secure mode. Only set this if you need it.
+ This can be overridden at run-time by setting the bootm_boot_mode env.
+ variable to "sec" or "nonsec".
config HAS_ARMV7_SECURE_BASE
bool "Enable support for a hardware secure memory area"
@@ -74,8 +74,8 @@ config ARMV7_VIRT
bool "Enable support for hardware virtualization" if EXPERT
depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
default y
- ---help---
- Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+ help
+ Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
config ARMV7_PSCI
bool "Enable PSCI support" if EXPERT
@@ -115,9 +115,9 @@ config ARMV7_LPAE
bool "Use LPAE page table format" if EXPERT
depends on CPU_V7A
default y if ARMV7_VIRT
- ---help---
- Say Y here to use the long descriptor page table format. This is
- required if U-Boot runs in HYP mode.
+ help
+ Say Y here to use the long descriptor page table format. This is
+ required if U-Boot runs in HYP mode.
config ARMV7_SET_CORTEX_SMPEN
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 5c8839583aa..9ce94555ed0 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -100,9 +100,9 @@ config SYS_FSL_ERRATUM_A008407
config SYS_FSL_QSPI_SKIP_CLKSEL
bool "Skip setting QSPI clock during SoC init"
help
- To improve startup times when booting from QSPI flash, the QSPI
- frequency can be set very early in the boot process. If this option
- is enabled, the QSPI frequency will not be changed by U-Boot during
- SoC initialization.
+ To improve startup times when booting from QSPI flash, the QSPI
+ frequency can be set very early in the boot process. If this option
+ is enabled, the QSPI frequency will not be changed by U-Boot during
+ SoC initialization.
endmenu
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 34eea22eb92..09092ea7b7f 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -16,7 +16,6 @@
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
#include <dm.h>
@@ -26,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
struct udevice *dev;
- struct tsec_private *priv;
+ struct eth_pdata *pdata;
const char *enet_path, *phy_path;
char enet[16];
char phy[16];
@@ -45,8 +44,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
continue;
}
- priv = dev_get_priv(dev);
- if (priv->flags & TSEC_SGMII)
+ pdata = dev_get_plat(dev);
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII)
continue;
enet_path = fdt_get_alias(fdt, enet);
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index dfc4ce851c3..7e4e3bdd66c 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -23,11 +23,11 @@ config ARMV8_SPL_EXCEPTION_VECTORS
and want to save some space at the cost of less debugging info.
config ARMV8_MULTIENTRY
- bool "Enable multiple CPUs to enter into U-Boot"
+ bool "Enable multiple CPUs to enter into U-Boot"
config ARMV8_SET_SMPEN
- bool "Enable data coherency with other cores in cluster"
- help
+ bool "Enable data coherency with other cores in cluster"
+ help
Say Y here if there is not any trust firmware to set
CPUECTLR_EL1.SMPEN bit before U-Boot.
@@ -79,12 +79,12 @@ config ARMV8_SEC_FIRMWARE_SUPPORT
process brief.
Note: Only FIT format image is supported.
You should prepare and provide the below information:
- - Address of secure firmware.
- - Address to hold the return address from secure firmware.
- - Secure firmware FIT image related information.
- Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
- - The target exception level that secure monitor firmware will
- return to.
+ - Address of secure firmware.
+ - Address to hold the return address from secure firmware.
+ - Secure firmware FIT image related information.
+ Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
+ - The target exception level that secure monitor firmware will
+ return to.
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 39479df7b21..e59528e576e 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- mem_map[index].virt = gd->bd->bi_dram[i].start;
- mem_map[index].phys = gd->bd->bi_dram[i].start;
- mem_map[index].size = gd->bd->bi_dram[i].size;
+ mem_map[index].virt = gd->dram[i].start;
+ mem_map[index].phys = gd->dram[i].start;
+ mem_map[index].size = gd->dram[i].size;
mem_map[index].attrs = attrs;
index++;
}
@@ -163,7 +163,7 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
static int pte_type(u64 *pte)
{
- return *pte & PTE_TYPE_MASK;
+ return *pte & PTE_TYPE_VALID ? *pte & PTE_TYPE_MASK : PTE_TYPE_FAULT;
}
/* Returns the LSB number for a PTE on level <level> */
@@ -534,7 +534,7 @@ static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, v
if (exit)
return;
- if (pte_type(&pte) == PTE_TYPE_FAULT)
+ if (!pte)
continue;
attrs = pte & ALL_ATTRS;
@@ -573,7 +573,7 @@ static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, v
/* Go down a level */
__pagetable_walk(_addr, tcr, level + 1, cb, priv);
state[level] = WALKER_STATE_START;
- } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) {
+ } else {
/* We foud a block or page, start walking */
entry_start = pte;
state[level] = WALKER_STATE_REGION;
@@ -734,6 +734,66 @@ void dump_pagetable(u64 ttbr, u64 tcr)
walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL);
}
+/* Do a software pagetable walk for the given address */
+void tlb_debug_lookup(u64 addr)
+{
+ u64 va_bits;
+ u64 ttbr = gd->arch.tlb_addr, *pte;
+ int lshift, level;
+
+ get_tcr(NULL, &va_bits);
+ level = va_bits < 39 ? 1 : 0;
+
+ printf("Performing software TLB lookup of address %#010llx va_bits: %lld\n",
+ addr, va_bits);
+
+ addr = ALIGN_DOWN(addr, 0x1000);
+ pte = ((u64 *)ttbr);
+ for (int i = level; i < 4; i++) {
+ int indent = (i - level + 1) * 2;
+ u32 idx;
+ u64 _addr;
+
+ lshift = level2shift(i);
+ idx = (addr >> lshift) & 0x1FF;
+
+ printf("%*sPTE: %#010llx. addr[%d:%d]: %#05x (offset %#07x)\n", indent, "", (u64)pte,
+ lshift + 8, lshift, idx, idx * 8);
+ printf("%*sL%d: %#010llx -> ", indent, "", i, (u64)(&pte[idx]));
+
+ pte = &pte[idx];
+ _addr = *pte & GENMASK_ULL(va_bits, PAGE_SHIFT);
+
+ /*
+ * Check the PTE and either descend if it's a table or print
+ * the mapping and return.
+ */
+ switch (pte_type(pte)) {
+ case PTE_TYPE_FAULT:
+ printf("UNMAPPED!\n");
+ return;
+ case PTE_TYPE_BLOCK:
+ printf("BLOCK (%#010llx)\n", _addr);
+ break;
+ case PTE_TYPE_TABLE:
+ if (i < 3) {
+ printf("TABLE (%#010llx)\n", _addr);
+ pte = (u64 *)_addr;
+ continue;
+ } else { /* PTE_TYPE_PAGE */
+ printf("PAGE (%#010llx)\n", _addr);
+ }
+ break;
+ default:
+ printf("Unknown (%#010llx)\n", _addr);
+ break;
+ }
+
+ printf("%*s[%#010llx - %#010llx]\n", indent + 2, "", _addr, _addr + (1 << lshift));
+ return;
+ }
+}
+
/* Returns the estimated required size of all page tables */
__weak u64 get_page_table_size(void)
{
@@ -810,8 +870,10 @@ __weak void mmu_setup(void)
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
+}
- /* enable the mmu */
+void mmu_enable(void)
+{
set_sctlr(get_sctlr() | CR_M);
}
@@ -881,6 +943,7 @@ void dcache_enable(void)
if (!mmu_status()) {
__asm_invalidate_tlb_all();
mmu_setup();
+ mmu_enable();
}
/* Set up page tables only once (it is done also by mmu_setup()) */
@@ -928,9 +991,10 @@ u64 *__weak arch_get_page_table(void) {
return NULL;
}
+/* Checks if the current PTE is an aligned subset of the region */
static bool is_aligned(u64 addr, u64 size, u64 align)
{
- return !(addr & (align - 1)) && !(size & (align - 1));
+ return !(addr & (align - 1)) && size >= align;
}
/* Use flag to indicate if attrs has more than d-cache attributes */
@@ -940,9 +1004,14 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
u64 levelsize = 1ULL << levelshift;
u64 *pte = find_pte(start, level);
- /* Can we can just modify the current level block PTE? */
+ /* Can we can just modify the current level block/page? */
if (is_aligned(start, size, levelsize)) {
- if (flag) {
+ if (attrs == PTE_TYPE_FAULT) {
+ if (pte_type(pte) == PTE_TYPE_TABLE && level < 3)
+ *pte = 0;
+ else
+ *pte &= ~(PTE_TYPE_MASK);
+ } else if (flag) {
*pte &= ~PMD_ATTRMASK;
*pte |= attrs & PMD_ATTRMASK;
} else {
@@ -970,6 +1039,28 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
return 0;
}
+static void set_regions(u64 start, u64 size, u64 attrs, bool flag)
+{
+ int level;
+ u64 r;
+
+ /*
+ * Loop through the address range until we find a page granule that fits
+ * our alignment constraints, then set it to the new cache attributes
+ */
+ while (size > 0) {
+ for (level = 1; level < 4; level++) {
+ r = set_one_region(start, size, attrs, flag, level);
+ if (r) {
+ /* PTE successfully replaced */
+ size -= r;
+ start += r;
+ break;
+ }
+ }
+ }
+}
+
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
@@ -989,26 +1080,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
*/
__asm_switch_ttbr(gd->arch.tlb_emerg);
- /*
- * Loop through the address range until we find a page granule that fits
- * our alignment constraints, then set it to the new cache attributes
- */
- while (size > 0) {
- int level;
- u64 r;
-
- for (level = 1; level < 4; level++) {
- /* Set d-cache attributes only */
- r = set_one_region(start, size, attrs, false, level);
- if (r) {
- /* PTE successfully replaced */
- size -= r;
- start += r;
- break;
- }
- }
-
- }
+ set_regions(start, size, attrs, false);
/* We're done modifying page tables, switch back to our primary ones */
__asm_switch_ttbr(gd->arch.tlb_addr);
@@ -1020,29 +1092,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
flush_dcache_range(real_start, real_start + real_size);
}
-void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)
+void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs)
{
- int level;
- u64 r, size, start;
-
- /*
- * Loop through the address range until we find a page granule that fits
- * our alignment constraints and set the new permissions
- */
- start = addr;
- size = siz;
- while (size > 0) {
- for (level = 1; level < 4; level++) {
- /* Set PTE to new attributes */
- r = set_one_region(start, size, attrs, true, level);
- if (r) {
- /* PTE successfully updated */
- size -= r;
- start += r;
- break;
- }
- }
- }
+ set_regions(addr, size, attrs, true);
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
@@ -1053,36 +1105,19 @@ void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)
* The procecess is break-before-make. The target region will be marked as
* invalid during the process of changing.
*/
-void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
+void mmu_change_region_attr(phys_addr_t addr, size_t size, u64 attrs)
{
- int level;
- u64 r, size, start;
-
- start = addr;
- size = siz;
- /*
- * Loop through the address range until we find a page granule that fits
- * our alignment constraints, then set it to "invalid".
- */
- while (size > 0) {
- for (level = 1; level < 4; level++) {
- /* Set PTE to fault */
- r = set_one_region(start, size, PTE_TYPE_FAULT, true,
- level);
- if (r) {
- /* PTE successfully invalidated */
- size -= r;
- start += r;
- break;
- }
- }
- }
+ set_regions(addr, size, PTE_TYPE_FAULT, true);
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
- mmu_change_region_attr_nobreak(addr, siz, attrs);
+ /* If we were unmapping a region then we have nothing to make and can return. */
+ if (attrs == PTE_TYPE_FAULT)
+ return;
+
+ mmu_change_region_attr_nobreak(addr, size, attrs);
}
int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4c5b38e3b65..2335c776c2e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -440,8 +440,8 @@ config MAX_CPUS
config EMC2305
bool "Fan controller"
help
- Enable the EMC2305 fan controller for configuration of fan
- speed.
+ Enable the EMC2305 fan controller for configuration of fan
+ speed.
config QSPI_AHB_INIT
bool "Init the QSPI AHB bus"
@@ -548,7 +548,7 @@ config SYS_FSL_PCLK_DIV
help
This is the divider that is used to derive Platform clock from
Platform PLL, in another word:
- Platform_clk = Platform_PLL_freq / this_divider
+ Platform_clk = Platform_PLL_freq / this_divider
config SYS_FSL_DSPI_CLK_DIV
int "DSPI clock divider"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index cfbaa475701..88adcf35432 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,16 +538,16 @@ static inline void final_mmu_setup(void)
*/
switch (final_map[index].virt) {
case CFG_SYS_FSL_DRAM_BASE1:
- final_map[index].virt = gd->bd->bi_dram[0].start;
- final_map[index].phys = gd->bd->bi_dram[0].start;
- final_map[index].size = gd->bd->bi_dram[0].size;
+ final_map[index].virt = gd->dram[0].start;
+ final_map[index].phys = gd->dram[0].start;
+ final_map[index].size = gd->dram[0].size;
break;
#ifdef CFG_SYS_FSL_DRAM_BASE2
case CFG_SYS_FSL_DRAM_BASE2:
#if (CONFIG_NR_DRAM_BANKS >= 2)
- final_map[index].virt = gd->bd->bi_dram[1].start;
- final_map[index].phys = gd->bd->bi_dram[1].start;
- final_map[index].size = gd->bd->bi_dram[1].size;
+ final_map[index].virt = gd->dram[1].start;
+ final_map[index].phys = gd->dram[1].start;
+ final_map[index].size = gd->dram[1].size;
#else
final_map[index].size = 0;
#endif
@@ -556,9 +556,9 @@ static inline void final_mmu_setup(void)
#ifdef CFG_SYS_FSL_DRAM_BASE3
case CFG_SYS_FSL_DRAM_BASE3:
#if (CONFIG_NR_DRAM_BANKS >= 3)
- final_map[index].virt = gd->bd->bi_dram[2].start;
- final_map[index].phys = gd->bd->bi_dram[2].start;
- final_map[index].size = gd->bd->bi_dram[2].size;
+ final_map[index].virt = gd->dram[2].start;
+ final_map[index].phys = gd->dram[2].start;
+ final_map[index].size = gd->dram[2].size;
#else
final_map[index].size = 0;
#endif
@@ -986,6 +986,27 @@ uint get_svr(void)
}
#endif
+/*
+ * Layerscape mirror of the i.MX get_cpu_temp_grade(). i.MX reads the
+ * OCOTP "CPU temp grade" fuses; Layerscape has no such fuse, so the
+ * limits come from the data sheet instead. LX2160A Reference Manual
+ * Rev. 1 (10/2021) section 1.12.1 specifies the maximum operating
+ * junction temperature at 105 degC for commercial / embedded parts;
+ * the lower bound is the standard -40 degC commercial low.
+ *
+ * The TMU itself is documented as accurate within +/- 3 degC (RM
+ * section 28.1), which the thermal driver clears by setting its
+ * alert threshold 10 degC below critical.
+ */
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ if (minc)
+ *minc = -40;
+ if (maxc)
+ *maxc = 105;
+ return 0; /* commercial */
+}
+
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
@@ -1143,7 +1164,7 @@ int arch_early_init_r(void)
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
+#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET)
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
@@ -1158,6 +1179,10 @@ int arch_early_init_r(void)
* function of SOC, the dpmac will be enabled as RGMII even if it was
* also enabled before as SGMII. If ECx_PMUX is not configured for
* RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
+ *
+ * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET
+ * (drivers/net/ldpaa_eth/); gate the call the same way so builds
+ * without MC-ENET still link.
*/
fsl_rgmii_init();
#endif
@@ -1371,10 +1396,10 @@ static int tfa_dram_init_banksize(void)
}
debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
- gd->bd->bi_dram[i].start = res.a1;
- gd->bd->bi_dram[i].size = res.a2;
+ gd->dram[i].start = res.a1;
+ gd->dram[i].size = res.a2;
- dram_size -= gd->bd->bi_dram[i].size;
+ dram_size -= gd->dram[i].size;
i++;
} while (dram_size);
@@ -1385,24 +1410,24 @@ static int tfa_dram_init_banksize(void)
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bd->bi_dram[2].size >=
- board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[2].start +
- gd->bd->bi_dram[2].size -
- board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ if (gd->dram[2].size >=
+ board_reserve_ram_top(gd->dram[2].size)) {
+ gd->arch.resv_ram = gd->dram[2].start +
+ gd->dram[2].size -
+ board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
- if (gd->bd->bi_dram[1].size >=
- board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[1].start +
- gd->bd->bi_dram[1].size -
- board_reserve_ram_top(gd->bd->bi_dram[1].size);
- } else if (gd->bd->bi_dram[0].size >
- board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size -
- board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ if (gd->dram[1].size >=
+ board_reserve_ram_top(gd->dram[1].size)) {
+ gd->arch.resv_ram = gd->dram[1].start +
+ gd->dram[1].size -
+ board_reserve_ram_top(gd->dram[1].size);
+ } else if (gd->dram[0].size >
+ board_reserve_ram_top(gd->dram[0].size)) {
+ gd->arch.resv_ram = gd->dram[0].start +
+ gd->dram[0].size -
+ board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
@@ -1439,30 +1464,30 @@ int dram_init_banksize(void)
}
#endif
- gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
+ gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+ gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
+ gd->dram[1].size = gd->ram_size -
CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
- gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
+ if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
+ gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
+ gd->dram[2].size = gd->dram[1].size -
CONFIG_SYS_DDR_BLOCK2_SIZE;
- gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
+ gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
}
#endif
} else {
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->dram[0].size = gd->ram_size;
}
#ifdef CFG_SYS_MEM_RESERVE_SECURE
- if (gd->bd->bi_dram[0].size >
+ if (gd->dram[0].size >
CFG_SYS_MEM_RESERVE_SECURE) {
- gd->bd->bi_dram[0].size -=
+ gd->dram[0].size -=
CFG_SYS_MEM_RESERVE_SECURE;
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size;
+ gd->arch.secure_ram = gd->dram[0].start +
+ gd->dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
@@ -1471,24 +1496,24 @@ int dram_init_banksize(void)
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
- if (gd->bd->bi_dram[2].size >=
- board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[2].start +
- gd->bd->bi_dram[2].size -
- board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ if (gd->dram[2].size >=
+ board_reserve_ram_top(gd->dram[2].size)) {
+ gd->arch.resv_ram = gd->dram[2].start +
+ gd->dram[2].size -
+ board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
- if (gd->bd->bi_dram[1].size >=
- board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[1].start +
- gd->bd->bi_dram[1].size -
- board_reserve_ram_top(gd->bd->bi_dram[1].size);
- } else if (gd->bd->bi_dram[0].size >
- board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
- gd->arch.resv_ram = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size -
- board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ if (gd->dram[1].size >=
+ board_reserve_ram_top(gd->dram[1].size)) {
+ gd->arch.resv_ram = gd->dram[1].start +
+ gd->dram[1].size -
+ board_reserve_ram_top(gd->dram[1].size);
+ } else if (gd->dram[0].size >
+ board_reserve_ram_top(gd->dram[0].size)) {
+ gd->arch.resv_ram = gd->dram[0].start +
+ gd->dram[0].size -
+ board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
@@ -1510,8 +1535,8 @@ int dram_init_banksize(void)
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
+ gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->dram[2].size = dp_ddr_size;
} else {
puts("Not detected");
}
@@ -1542,14 +1567,15 @@ void lmb_arch_add_memory(void)
if (i == 2)
continue; /* skip DP-DDR */
#endif
- ram_start = gd->bd->bi_dram[i].start;
- ram_size = gd->bd->bi_dram[i].size;
+ ram_start = gd->dram[i].start;
+ ram_size = gd->dram[i].size;
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram >= ram_start &&
gd->arch.resv_ram < ram_start + ram_size)
ram_size = gd->arch.resv_ram - ram_start;
#endif
- lmb_add(ram_start, ram_size);
+ if (ram_size > 0)
+ lmb_add(ram_start, ram_size);
}
}
#endif
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 87de09979b1..f834d770dd6 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -129,3 +129,18 @@ void __noreturn psci_system_off(void)
while (1)
;
}
+
+int psci_features(u32 psci_func_id)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_1_0_FN_PSCI_FEATURES;
+ regs.regs[1] = psci_func_id;
+
+ if (use_smc_for_psci)
+ smc_call(&regs);
+ else
+ hvc_call(&regs);
+
+ return regs.regs[0];
+}
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 8e2266a90fe..98b0306f3b2 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -96,7 +96,7 @@ SECTIONS
{
KEEP(*(.__secure_stack_start))
- /* Skip addreses for stack */
+ /* Skip addresses for stack */
. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
/* Align end of stack section to page boundary */
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-11 17:36:26 +0000