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-rw-r--r--arch/powerpc/config.mk2
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig46
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/liodn.c2
-rw-r--r--arch/powerpc/dts/Makefile1
-rw-r--r--arch/powerpc/dts/p2041.dtsi138
-rw-r--r--arch/powerpc/dts/p2041rdb-u-boot.dtsi19
-rw-r--r--arch/powerpc/dts/p2041rdb.dts127
-rw-r--r--arch/powerpc/dts/p2041si-post.dtsi43
9 files changed, 49 insertions, 335 deletions
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 6e30df6504e..32e86d84a12 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -32,7 +32,7 @@ archprepare: checkgcc4
# GCC 3.x is reported to have problems generating the type of relocation
# that U-Boot wants.
-# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+# See https://patch.msgid.link/1348500648.2514.2.camel@petert/
checkgcc4:
@if test "$(call cc-name)" = "gcc" -a \
$(call cc-version) -lt 0400; then \
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 55152ab227e..32a140b0913 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -966,14 +966,14 @@ config E500
bool
default y
help
- Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+ Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
config E500MC
bool
select BTB
imply CMD_PCI
help
- Enble PowerPC E500MC core
+ Enable PowerPC E500MC core
config E5500
bool
@@ -982,7 +982,7 @@ config E6500
bool
select BTB
help
- Enable PowerPC E6500 core
+ Enable PowerPC E6500 core
config NOBQFMAN
bool
@@ -990,7 +990,7 @@ config NOBQFMAN
config FSL_LAW
bool
help
- Use Freescale common code for Local Access Window
+ Use Freescale common code for Local Access Window
config HETROGENOUS_CLUSTERS
bool
@@ -1054,10 +1054,10 @@ config SYS_CCSRBAR_DEFAULT
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
help
- Default value of CCSRBAR comes from power-on-reset. It
- is fixed on each SoC. Some SoCs can have different value
- if changed by pre-boot regime. The value here must match
- the current value in SoC. If not sure, do not change.
+ Default value of CCSRBAR comes from power-on-reset. It
+ is fixed on each SoC. Some SoCs can have different value
+ if changed by pre-boot regime. The value here must match
+ the current value in SoC. If not sure, do not change.
config SYS_DPAA_PME
bool
@@ -1287,8 +1287,8 @@ config SYS_FSL_NUM_LAWS
default 8 if ARCH_MPC8540 || \
ARCH_MPC8560
help
- Number of local access windows. This is fixed per SoC.
- If not sure, do not change.
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
config SYS_FSL_CORES_PER_CLUSTER
int
@@ -1308,8 +1308,8 @@ config SYS_NUM_TLBCAMS
default 64 if E500MC
default 16
help
- Number of TLB CAM entries for Book-E chips. 64 for E500MC,
- 16 for other E500 SoCs.
+ Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+ 16 for other E500 SoCs.
config L2_CACHE
bool "Enable L2 cache support"
@@ -1375,7 +1375,7 @@ config SYS_L3_SIZE
int
default 262144 if SYS_L3_SIZE_256KB
default 524288 if SYS_L3_SIZE_512KB
- default 1048576 if SYS_L3_SIZE_512KB
+ default 1048576 if SYS_L3_SIZE_1024KB
config SYS_PPC64
bool
@@ -1401,12 +1401,12 @@ config SYS_PPC_E500_DEBUG_TLB
ARCH_BSC9132 || \
ARCH_C29X
help
- Select a temporary TLB entry to be used during boot to work
- around limitations in e500v1 and e500v2 external debugger
- support. This reduces the portions of the boot code where
- breakpoints and single stepping do not work. The value of this
- symbol should be set to the TLB1 entry to be used for this
- purpose. If unsure, do not change.
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
config SYS_FSL_IFC_CLK_DIV
int "Divider of platform clock"
@@ -1419,8 +1419,8 @@ config SYS_FSL_IFC_CLK_DIV
ARCH_T4240
default 1
help
- Defines divider of platform clock(clock input to
- IFC controller).
+ Defines divider of platform clock(clock input to
+ IFC controller).
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
@@ -1435,8 +1435,8 @@ config SYS_FSL_LBC_CLK_DIV
default 1
help
- Defines divider of platform clock(clock input to
- eLBC controller).
+ Defines divider of platform clock(clock input to
+ eLBC controller).
config ENABLE_36BIT_PHYS
bool "Enable 36bit physical address space support"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 739d14f8002..414782c835f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -41,10 +41,12 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
-#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_FSL_CORENET)
#include <asm/fsl_pamu.h>
+#if defined(CONFIG_NXP_ESBC)
#include <fsl_secboot_err.h>
#endif
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
@@ -899,6 +901,8 @@ int cpu_init_r(void)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#elif defined(CONFIG_FSL_CORENET)
+ pamu_init();
#endif
#ifdef CONFIG_FSL_CAAM
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index af6731cbb3a..ddf0ac99cf6 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -110,7 +110,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
break;
#endif
default:
- printf("Error: Invalid device type to %s\n", __FUNCTION__);
+ printf("Error: Invalid device type to %s\n", __func__);
return;
}
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 766b0c05951..4fd3478ac2f 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
-dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
deleted file mode 100644
index ad09b138fc8..00000000000
--- a/arch/powerpc/dts/p2041.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500mc_power_isa.dtsi"
-
-/ {
- compatible = "fsl,P2041";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e500mc@0 {
- device_type = "cpu";
- reg = <0>;
- fsl,portid-mapping = <0x80000000>;
- };
- cpu1: PowerPC,e500mc@1 {
- device_type = "cpu";
- reg = <1>;
- fsl,portid-mapping = <0x40000000>;
- };
- cpu2: PowerPC,e500mc@2 {
- device_type = "cpu";
- reg = <2>;
- fsl,portid-mapping = <0x20000000>;
- };
- cpu3: PowerPC,e500mc@3 {
- device_type = "cpu";
- reg = <3>;
- fsl,portid-mapping = <0x10000000>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- usb0: usb@210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- usb1: usb@211000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- sata: sata@220000 {
- compatible = "fsl,pq-sata-v2";
- reg = <0x220000 0x1000>;
- interrupts = <68 0x2 0 0>;
- sata-offset = <0x1000>;
- sata-number = <2>;
- sata-fpdma = <0>;
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
-
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe200000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe201000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe202000 {
- compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi
new file mode 100644
index 00000000000..1dc83cf846b
--- /dev/null
+++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&serial0 {
+ bootph-all;
+};
+
+&soc {
+ i2c@118000 {
+ bootph-all;
+ };
+
+ spi@110000 {
+ flash@0 {
+ spi-max-frequency = <10000000>;
+ };
+ };
+};
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
deleted file mode 100644
index 0fa1f098524..00000000000
--- a/arch/powerpc/dts/p2041rdb.dts
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2041RDB Device Tree Source
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p2041.dtsi"
-
-/ {
- model = "fsl,P2041RDB";
- compatible = "fsl,P2041RDB";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases {
- phy_rgmii_0 = &phy_rgmii_0;
- phy_rgmii_1 = &phy_rgmii_1;
- phy_sgmii_2 = &phy_sgmii_2;
- phy_sgmii_3 = &phy_sgmii_3;
- phy_sgmii_4 = &phy_sgmii_4;
- phy_sgmii_1c = &phy_sgmii_1c;
- phy_sgmii_1d = &phy_sgmii_1d;
- phy_sgmii_1e = &phy_sgmii_1e;
- phy_sgmii_1f = &phy_sgmii_1f;
- phy_xgmii_2 = &phy_xgmii_2;
- spi0 = &espi0;
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
-
- fman@400000 {
- ethernet@e0000 {
- phy-handle = <&phy_sgmii_2>;
- phy-connection-type = "sgmii";
- };
-
- mdio@e1120 {
- phy_rgmii_0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- phy_rgmii_1: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- phy_sgmii_2: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- phy_sgmii_3: ethernet-phy@3 {
- reg = <0x3>;
- };
-
- phy_sgmii_4: ethernet-phy@4 {
- reg = <0x4>;
- };
-
- phy_sgmii_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- ethernet@e2000 {
- phy-handle = <&phy_sgmii_3>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy_sgmii_4>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy_rgmii_1>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_0>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy_xgmii_2>;
- phy-connection-type = "xgmii";
- };
-
- mdio@f1000 {
- phy_xgmii_2: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- };
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- /* input clock */
- spi-max-frequency = <10000000>;
- };
-};
-
-/include/ "p2041si-post.dtsi"
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
deleted file mode 100644
index 8819199646f..00000000000
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P2041/P2040 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec4.2-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-1g-4.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
- fman@400000 {
- enet0: ethernet@e0000 {
- };
-
- enet1: ethernet@e2000 {
- };
-
- enet2: ethernet@e4000 {
- };
-
- enet3: ethernet@e6000 {
- };
-
- enet4: ethernet@e8000 {
- };
-
- enet5: ethernet@f0000 {
- };
- };
-};
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-10 12:54:20 +0000