diff options
Diffstat (limited to 'board/nxp')
99 files changed, 2695 insertions, 3255 deletions
diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile index ed102ae7bf7..dafd3717948 100644 --- a/board/nxp/common/Makefile +++ b/board/nxp/common/Makefile @@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) obj-y += mmc.o diff --git a/board/nxp/common/i2c_mux.h b/board/nxp/common/i2c_mux.h index 0870c1918e6..ef7ce8e2e51 100644 --- a/board/nxp/common/i2c_mux.h +++ b/board/nxp/common/i2c_mux.h @@ -10,6 +10,11 @@ #ifdef CONFIG_FSL_USE_PCA9547_MUX int select_i2c_ch_pca9547(u8 ch, int bus); +#else +static inline int select_i2c_ch_pca9547(u8 ch, int bus) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c index 0d7a94fd232..179cc605da0 100644 --- a/board/nxp/common/pfuze.c +++ b/board/nxp/common/pfuze.c @@ -7,14 +7,14 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -#ifndef CONFIG_DM_PMIC_PFUZE100 -int pfuze_mode_init(struct pmic *p, u32 mode) +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) +int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return ret; } -struct pmic *pfuze_common_init(unsigned char i2cbus) +struct udevice *pfuze_common_init(void) { - struct pmic *p; + struct udevice *dev; int ret; - unsigned int reg; - - ret = power_pfuze100_init(i2cbus); - if (ret) - return NULL; + unsigned int reg, dev_id, rev_id; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) return NULL; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); - return p; + return dev; } -#elif defined(CONFIG_DM_PMIC) -int pfuze_mode_init(struct udevice *dev, u32 mode) +#else +int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - id = pmic_reg_read(dev, PFUZE100_DEVICEID); + pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; if (id == 0) { @@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return -EINVAL; } - ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return ret; } -struct udevice *pfuze_common_init(void) +struct pmic *pfuze_common_init(unsigned char i2cbus) { - struct udevice *dev; + struct pmic *p; int ret; - unsigned int reg, dev_id, rev_id; + unsigned int reg; - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) + ret = power_pfuze100_init(i2cbus); + if (ret) return NULL; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); /* Set SW1AB stanby volage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - return dev; + return p; } #endif diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h index 45b49afaeb7..da89853bd20 100644 --- a/board/nxp/common/pfuze.h +++ b/board/nxp/common/pfuze.h @@ -6,7 +6,7 @@ #ifndef __PFUZE_BOARD_HELPER__ #define __PFUZE_BOARD_HELPER__ -#ifdef CONFIG_DM_PMIC_PFUZE100 +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) struct udevice *pfuze_common_init(void); int pfuze_mode_init(struct udevice *dev, u32 mode); #else diff --git a/board/nxp/common/vid.c b/board/nxp/common/vid.c index 84cb43fad56..70c3b3ecfd8 100644 --- a/board/nxp/common/vid.c +++ b/board/nxp/common/vid.c @@ -11,6 +11,7 @@ #include <i2c.h> #include <irq_func.h> #include <log.h> +#include <pmbus.h> #include <vsprintf.h> #include <asm/io.h> #ifdef CONFIG_FSL_LSCH2 @@ -260,45 +261,38 @@ static int read_voltage_from_IR(int i2caddress) */ #define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" -/* Checks the PMBus voltage monitor for the format used for voltage values */ -static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +/* + * Read VOUT_MODE for downstream LINEAR16 decode/encode through the + * tree level <pmbus.h> helpers (pmbus_reg2data_linear16, + * pmbus_data2reg_linear16). Stores the raw VOUT_MODE byte in *mode + * and returns 0 on success, or the negative bus error (a failed read + * must not be decoded: raw 0 aliases Linear mode with exponent 0). + * Emits VOUT_WARNING on Linear mode chips with a non negative + * exponent (resolution >= 1 V is unusable for sub volt SoC rails) + * and an informational note on the unsupported VID format. + */ +static int vid_read_vout_mode(DEVICE_HANDLE_T dev, u8 *mode) { - u8 mode; - int exponent, multiplier, ret; + int ret; - ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); + ret = pmbus_read_byte(dev, PMBUS_VOUT_MODE, mode); if (ret) { printf("VID: unable to determine voltage multiplier\n"); - return 1; + return ret; } - /* Upper 3 bits is mode, lower 5 bits is exponent */ - exponent = (int)mode & 0x1F; - mode >>= 5; - switch (mode) { - case 0: - /* Linear, 5 bit twos component exponent */ - if (exponent & 0x10) { - multiplier = 1 << (16 - (exponent & 0xF)); - } else { - /* If exponent is >= 0, then resolution is 1 V! */ + switch (*mode & PB_VOUT_MODE_MODE_MASK) { + case PB_VOUT_MODE_LINEAR: + if (!(*mode & 0x10)) printf(VOUT_WARNING); - multiplier = 1; - } break; - case 1: - /* VID code identifier */ + case PB_VOUT_MODE_VID: printf("VID: custom VID codes are not supported\n"); - multiplier = MV_PER_V; break; default: - /* Direct, in mV */ - multiplier = MV_PER_V; break; } - - debug("VID: calculated multiplier is %d\n", multiplier); - return multiplier; + return 0; } #endif @@ -306,8 +300,8 @@ static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) defined(CONFIG_VOL_MONITOR_LTC3882_READ) static int read_voltage_from_pmbus(int i2caddress) { - int ret, multiplier, vout; - u8 channel = PWM_CHANNEL0; + int ret, vout; + u8 channel = PWM_CHANNEL0, vout_mode; u16 vcode; DEVICE_HANDLE_T dev; @@ -317,25 +311,33 @@ static int read_voltage_from_pmbus(int i2caddress) return ret; /* Select the right page */ - ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); + ret = pmbus_write_byte(dev, PMBUS_PAGE, channel); if (ret) { printf("VID: failed to select VDD page %d\n", channel); return ret; } - /* VOUT is little endian */ - ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); + ret = pmbus_read_word(dev, PMBUS_READ_VOUT, &vcode); if (ret) { printf("VID: failed to read core voltage\n"); return ret; } - /* Scale down to the real mV */ - multiplier = get_pmbus_multiplier(dev); - vout = (int)vcode; - /* Multiplier 1000 (direct mode) requires no change to convert */ - if (multiplier != MV_PER_V) - vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + /* + * Decode LINEAR16 via the tree level helper from <pmbus.h>. For + * non Linear VOUT_MODE settings the helper returns 0; fall back + * to the historic mV pass through so existing LSCH boards keep. + */ + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) { + s64 uv = pmbus_reg2data_linear16(vcode, vout_mode); + + vout = (int)((uv + 500) / 1000); /* round to mV */ + } else { + vout = (int)vcode; + } return vout - board_vdd_drop_compensation(); } #endif @@ -463,11 +465,13 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_pmbus(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; - int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0; + u8 vout_mode; + u16 raw; unsigned char value; /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ - u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, 0, 0 }; DEVICE_HANDLE_T dev; /* Open device handle */ @@ -475,24 +479,32 @@ static int set_voltage_to_pmbus(int i2caddress, int vdd) if (ret) return ret; - /* Scale up to the proper value for the VOUT command, little endian */ - multiplier = get_pmbus_multiplier(dev); + /* + * Encode target mV as LINEAR16 raw via the tree level helper + * from <pmbus.h>. For non Linear VOUT_MODE settings the helper + * returns 0; fall back to the historic mV pass through. A failed + * VOUT_MODE read aborts: never write a voltage code whose + * encoding could not be determined. + */ vdd += board_vdd_drop_compensation(); - if (multiplier != MV_PER_V) - vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); - buffer[3] = vdd & 0xFF; - buffer[4] = (vdd & 0xFF00) >> 8; + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) + raw = pmbus_data2reg_linear16((s64)vdd * 1000LL, vout_mode); + else + raw = (u16)vdd; + buffer[3] = raw & 0xFF; + buffer[4] = (raw & 0xFF00) >> 8; /* Check write protect state */ - ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, - sizeof(value)); + ret = pmbus_read_byte(dev, PMBUS_WRITE_PROTECT, &value); if (ret) goto exit; if (value != EN_WRITE_ALL_CMD) { value = EN_WRITE_ALL_CMD; - ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); + ret = pmbus_write_byte(dev, PMBUS_WRITE_PROTECT, value); if (ret) goto exit; } diff --git a/board/nxp/common/vid.h b/board/nxp/common/vid.h index b34c080b4ba..72c1c089aa1 100644 --- a/board/nxp/common/vid.h +++ b/board/nxp/common/vid.h @@ -22,8 +22,9 @@ #define IR_VDD_STEP_UP 5 /* LTC3882 */ -#define PMBUS_CMD_WRITE_PROTECT 0x10 /* + * PMBUS_WRITE_PROTECT (10h) provided by <pmbus.h> + * * WRITE_PROTECT command supported values * 0x80: Disable all writes except WRITE_PROTECT, PAGE, * STORE_USER_ALL and MFR_EE_UNLOCK commands. @@ -51,12 +52,14 @@ #define VDD_MV_MAX 925 #endif -/* PM Bus commands code for LTC3882*/ +/* + * PM Bus commands code for LTC3882. PMBUS_PAGE / PMBUS_READ_VOUT / + * PMBUS_VOUT_MODE / PMBUS_VOUT_COMMAND are provided by <pmbus.h>. + * PMBUS_CMD_PAGE_PLUS_WRITE (05h) is the LTC3882 SMBus block write + * transaction not in <pmbus.h>'s standard subset, so keep its + * definition here. + */ #define PWM_CHANNEL0 0x0 -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_VOUT_MODE 0x20 -#define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index d59bd6fd5ed..88eefaa35e5 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index cffa83bf792..fbdf202c573 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index e994b93b168..dfc922e6215 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -10,6 +10,8 @@ fdt_addr=0x43000000 fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c index 27cd82e745a..cd7d79b382d 100644 --- a/board/nxp/imx8mp_evk/spl.c +++ b/board/nxp/imx8mp_evk/spl.c @@ -65,7 +65,7 @@ int power_init_board(void) * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index 6575dd7cb07..dd674afac91 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -10,6 +10,8 @@ initrd_addr=0x43800000 image=Image ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c index 5116d806bb6..80322a2ed19 100644 --- a/board/nxp/imx8mq_evk/spl.c +++ b/board/nxp/imx8mq_evk/spl.c @@ -9,23 +9,16 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <fsl_esdhc_imx.h> -#include <fsl_sec.h> -#include <mmc.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <dm/uclass.h> +#include <dm/device.h> #include <spl.h> #include "../common/pfuze.h" @@ -40,166 +33,52 @@ static void spl_dram_init(void) ddr_init(&dram_timing_b0); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void spl_board_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { - if (sec_init()) - printf("\nsec_init failed!\n"); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); } puts("Normal Boot\n"); } @@ -218,8 +97,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -229,25 +108,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index b2ed1901a2b..76fadc00eeb 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -10,13 +10,16 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile index 9612b1fa55b..751ebfc9458 100644 --- a/board/nxp/imx93_frdm/Makefile +++ b/board/nxp/imx93_frdm/Makefile @@ -7,5 +7,5 @@ obj-y += imx93_frdm.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o endif diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 9af3bdfd714..96096bc51a0 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -10,12 +10,15 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=1 mmcpart=1 mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h index 192bc9e1519..3ff50d8519b 100644 --- a/board/nxp/imx93_frdm/lpddr4_timing.h +++ b/board/nxp/imx93_frdm/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; +extern struct dram_timing_info dram_timing_1CS_2GB; +extern struct dram_timing_info dram_timing_2CS_2GB; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c index cd129e12959..5439a039c3d 100644 --- a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c +++ b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c @@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { +struct dram_timing_info dram_timing_1CS_2GB = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, diff --git a/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c new file mode 100644 index 00000000000..79539941412 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c @@ -0,0 +1,2006 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Generated code from DDR Gear + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44104001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x80000412 }, + { 0x4e300114, 0x1002 }, + { 0x4e300260, 0x80 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x43b30002 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xfaee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x5c18b }, + { 0x4e300124, 0x1c790000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0xfe00fe }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x224f2213 }, + { 0x4e300304, 0xfe2213 }, + { 0x4e300308, 0xa380e3c }, + }, + { + { 0x01, 0xe4 }, + { 0x02, 0x36 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x124f2100 }, + { 0x4e300104, 0xf877000e }, + { 0x4e300108, 0x1816e4aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0x7b007b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0xb4 }, + { 0x02, 0x1b }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x51000 }, + { 0x4e300104, 0xf855000a }, + { 0x4e300108, 0x6e620a48 }, + { 0x4e30010c, 0x31010d }, + { 0x4e300124, 0x4c50000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30000000 }, + { 0x4e300170, 0x89090408 }, + { 0x4e300250, 0x7 }, + { 0x4e300254, 0x240024 }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0x94 }, + { 0x02, 0x09 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 1, + }, +}; + +/* Auto Generated by SNPS PHY Init code + * which inlcude PHYINIT, 1D/2D message block + * rerention CSR, PIE + */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { +/* ADDR mapping is from ds file. */ + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, +/* End of ADDR mapping. */ + { 0x1005f, 0x5ff}, + { 0x1015f, 0x5ff}, + { 0x1105f, 0x5ff}, + { 0x1115f, 0x5ff}, + { 0x11005f, 0x5ff}, + { 0x11015f, 0x5ff}, + { 0x11105f, 0x5ff}, + { 0x11115f, 0x5ff}, + { 0x21005f, 0x5ff}, + { 0x21015f, 0x5ff}, + { 0x21105f, 0x5ff}, + { 0x21115f, 0x5ff}, + { 0x55, 0x1ff}, + { 0x1055, 0x1ff}, + { 0x2055, 0x1ff}, + { 0x200c5, 0x19}, + { 0x1200c5, 0xb}, + { 0x2200c5, 0x7}, + { 0x2002e, 0x2}, + { 0x12002e, 0x2}, + { 0x22002e, 0x2}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x2007d, 0x212}, + { 0x2007c, 0x61}, + { 0x120024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x12007d, 0x212}, + { 0x12007c, 0x61}, + { 0x220024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x22007d, 0x212}, + { 0x22007c, 0x61}, + { 0x20056, 0x3}, + { 0x120056, 0x3}, + { 0x220056, 0x3}, + { 0x1004d, 0x600}, + { 0x1014d, 0x600}, + { 0x1104d, 0x600}, + { 0x1114d, 0x600}, + { 0x11004d, 0x600}, + { 0x11014d, 0x600}, + { 0x11104d, 0x600}, + { 0x11114d, 0x600}, + { 0x21004d, 0x600}, + { 0x21014d, 0x600}, + { 0x21104d, 0x600}, + { 0x21114d, 0x600}, + { 0x10049, 0xe00}, + { 0x10149, 0xe00}, + { 0x11049, 0xe00}, + { 0x11149, 0xe00}, + { 0x110049, 0xe00}, + { 0x110149, 0xe00}, + { 0x111049, 0xe00}, + { 0x111149, 0xe00}, + { 0x210049, 0xe00}, + { 0x210149, 0xe00}, + { 0x211049, 0xe00}, + { 0x211149, 0xe00}, + { 0x43, 0x60}, + { 0x1043, 0x60}, + { 0x2043, 0x60}, + { 0x20018, 0x1}, + { 0x20075, 0x4}, + { 0x20050, 0x0}, + { 0x2009b, 0x2}, + { 0x20008, 0x3a5}, + { 0x120008, 0x1d3}, + { 0x220008, 0x9c}, + { 0x20088, 0x9}, + { 0x200b2, 0x10c}, + { 0x10043, 0x5a1}, + { 0x10143, 0x5a1}, + { 0x11043, 0x5a1}, + { 0x11143, 0x5a1}, + { 0x1200b2, 0x10c}, + { 0x110043, 0x5a1}, + { 0x110143, 0x5a1}, + { 0x111043, 0x5a1}, + { 0x111143, 0x5a1}, + { 0x2200b2, 0x10c}, + { 0x210043, 0x5a1}, + { 0x210143, 0x5a1}, + { 0x211043, 0x5a1}, + { 0x211143, 0x5a1}, + { 0x200fa, 0x2}, + { 0x1200fa, 0x2}, + { 0x2200fa, 0x2}, + { 0x20019, 0x1}, + { 0x120019, 0x1}, + { 0x220019, 0x1}, + { 0x200f0, 0x600}, + { 0x200f1, 0x0}, + { 0x200f2, 0x4444}, + { 0x200f3, 0x8888}, + { 0x200f4, 0x5655}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0xf000}, + { 0x1004a, 0x500}, + { 0x1104a, 0x500}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + /* workaround STAR_3141216 marker */ + { 0x20021, 0x0}, + /* workaround STAR_3975199 marker */ + { 0x200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x200ca, 0x24}, + /* workaround STAR_3975199 marker */ + { 0x1200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x1200ca, 0x24}, +}; + +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x1005f, 0x0}, + { 0x1015f, 0x0}, + { 0x1105f, 0x0}, + { 0x1115f, 0x0}, + { 0x11005f, 0x0}, + { 0x11015f, 0x0}, + { 0x11105f, 0x0}, + { 0x11115f, 0x0}, + { 0x21005f, 0x0}, + { 0x21015f, 0x0}, + { 0x21105f, 0x0}, + { 0x21115f, 0x0}, + { 0x55, 0x0}, + { 0x1055, 0x0}, + { 0x2055, 0x0}, + { 0x200c5, 0x0}, + { 0x1200c5, 0x0}, + { 0x2200c5, 0x0}, + { 0x2002e, 0x0}, + { 0x12002e, 0x0}, + { 0x22002e, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x0}, + { 0x2003a, 0x0}, + { 0x2007d, 0x0}, + { 0x2007c, 0x0}, + { 0x120024, 0x0}, + { 0x12007d, 0x0}, + { 0x12007c, 0x0}, + { 0x220024, 0x0}, + { 0x22007d, 0x0}, + { 0x22007c, 0x0}, + { 0x20056, 0x0}, + { 0x120056, 0x0}, + { 0x220056, 0x0}, + { 0x1004d, 0x0}, + { 0x1014d, 0x0}, + { 0x1104d, 0x0}, + { 0x1114d, 0x0}, + { 0x11004d, 0x0}, + { 0x11014d, 0x0}, + { 0x11104d, 0x0}, + { 0x11114d, 0x0}, + { 0x21004d, 0x0}, + { 0x21014d, 0x0}, + { 0x21104d, 0x0}, + { 0x21114d, 0x0}, + { 0x10049, 0x0}, + { 0x10149, 0x0}, + { 0x11049, 0x0}, + { 0x11149, 0x0}, + { 0x110049, 0x0}, + { 0x110149, 0x0}, + { 0x111049, 0x0}, + { 0x111149, 0x0}, + { 0x210049, 0x0}, + { 0x210149, 0x0}, + { 0x211049, 0x0}, + { 0x211149, 0x0}, + { 0x43, 0x0}, + { 0x1043, 0x0}, + { 0x2043, 0x0}, + { 0x20018, 0x0}, + { 0x20075, 0x0}, + { 0x20050, 0x0}, + { 0x2009b, 0x0}, + { 0x20008, 0x0}, + { 0x120008, 0x0}, + { 0x220008, 0x0}, + { 0x20088, 0x0}, + { 0x200b2, 0x0}, + { 0x10043, 0x0}, + { 0x10143, 0x0}, + { 0x11043, 0x0}, + { 0x11143, 0x0}, + { 0x1200b2, 0x0}, + { 0x110043, 0x0}, + { 0x110143, 0x0}, + { 0x111043, 0x0}, + { 0x111143, 0x0}, + { 0x2200b2, 0x0}, + { 0x210043, 0x0}, + { 0x210143, 0x0}, + { 0x211043, 0x0}, + { 0x211143, 0x0}, + { 0x200fa, 0x0}, + { 0x1200fa, 0x0}, + { 0x2200fa, 0x0}, + { 0x20019, 0x0}, + { 0x120019, 0x0}, + { 0x220019, 0x0}, + { 0x200f0, 0x0}, + { 0x200f1, 0x0}, + { 0x200f2, 0x0}, + { 0x200f3, 0x0}, + { 0x200f4, 0x0}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0x0}, + { 0x1004a, 0x0}, + { 0x1104a, 0x0}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + { 0xd0000, 0x0}, + { 0x90000, 0x0}, + { 0x90001, 0x0}, + { 0x90002, 0x0}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x0}, + { 0x90029, 0x0}, + { 0x9002a, 0x0}, + { 0x9002b, 0x0}, + { 0x9002c, 0x0}, + { 0x9002d, 0x0}, + { 0x9002e, 0x0}, + { 0x9002f, 0x0}, + { 0x90030, 0x0}, + { 0x90031, 0x0}, + { 0x90032, 0x0}, + { 0x90033, 0x0}, + { 0x90034, 0x0}, + { 0x90035, 0x0}, + { 0x90036, 0x0}, + { 0x90037, 0x0}, + { 0x90038, 0x0}, + { 0x90039, 0x0}, + { 0x9003a, 0x0}, + { 0x9003b, 0x0}, + { 0x9003c, 0x0}, + { 0x9003d, 0x0}, + { 0x9003e, 0x0}, + { 0x9003f, 0x0}, + { 0x90040, 0x0}, + { 0x90041, 0x0}, + { 0x90042, 0x0}, + { 0x90043, 0x0}, + { 0x90044, 0x0}, + { 0x90045, 0x0}, + { 0x90046, 0x0}, + { 0x90047, 0x0}, + { 0x90048, 0x0}, + { 0x90049, 0x0}, + { 0x9004a, 0x0}, + { 0x9004b, 0x0}, + { 0x9004c, 0x0}, + { 0x9004d, 0x0}, + { 0x9004e, 0x0}, + { 0x9004f, 0x0}, + { 0x90050, 0x0}, + { 0x90051, 0x0}, + { 0x90052, 0x0}, + { 0x90053, 0x0}, + { 0x90054, 0x0}, + { 0x90055, 0x0}, + { 0x90056, 0x0}, + { 0x90057, 0x0}, + { 0x90058, 0x0}, + { 0x90059, 0x0}, + { 0x9005a, 0x0}, + { 0x9005b, 0x0}, + { 0x9005c, 0x0}, + { 0x9005d, 0x0}, + { 0x9005e, 0x0}, + { 0x9005f, 0x0}, + { 0x90060, 0x0}, + { 0x90061, 0x0}, + { 0x90062, 0x0}, + { 0x90063, 0x0}, + { 0x90064, 0x0}, + { 0x90065, 0x0}, + { 0x90066, 0x0}, + { 0x90067, 0x0}, + { 0x90068, 0x0}, + { 0x90069, 0x0}, + { 0x9006a, 0x0}, + { 0x9006b, 0x0}, + { 0x9006c, 0x0}, + { 0x9006d, 0x0}, + { 0x9006e, 0x0}, + { 0x9006f, 0x0}, + { 0x90070, 0x0}, + { 0x90071, 0x0}, + { 0x90072, 0x0}, + { 0x90073, 0x0}, + { 0x90074, 0x0}, + { 0x90075, 0x0}, + { 0x90076, 0x0}, + { 0x90077, 0x0}, + { 0x90078, 0x0}, + { 0x90079, 0x0}, + { 0x9007a, 0x0}, + { 0x9007b, 0x0}, + { 0x9007c, 0x0}, + { 0x9007d, 0x0}, + { 0x9007e, 0x0}, + { 0x9007f, 0x0}, + { 0x90080, 0x0}, + { 0x90081, 0x0}, + { 0x90082, 0x0}, + { 0x90083, 0x0}, + { 0x90084, 0x0}, + { 0x90085, 0x0}, + { 0x90086, 0x0}, + { 0x90087, 0x0}, + { 0x90088, 0x0}, + { 0x90089, 0x0}, + { 0x9008a, 0x0}, + { 0x9008b, 0x0}, + { 0x9008c, 0x0}, + { 0x9008d, 0x0}, + { 0x9008e, 0x0}, + { 0x9008f, 0x0}, + { 0x90090, 0x0}, + { 0x90091, 0x0}, + { 0x90092, 0x0}, + { 0x90093, 0x0}, + { 0x90094, 0x0}, + { 0x90095, 0x0}, + { 0x90096, 0x0}, + { 0x90097, 0x0}, + { 0x90098, 0x0}, + { 0x90099, 0x0}, + { 0x9009a, 0x0}, + { 0x9009b, 0x0}, + { 0x9009c, 0x0}, + { 0x9009d, 0x0}, + { 0x9009e, 0x0}, + { 0x9009f, 0x0}, + { 0x900a0, 0x0}, + { 0x900a1, 0x0}, + { 0x900a2, 0x0}, + { 0x900a3, 0x0}, + { 0x900a4, 0x0}, + { 0x900a5, 0x0}, + { 0x900a6, 0x0}, + { 0x900a7, 0x0}, + { 0x900a8, 0x0}, + { 0x900a9, 0x0}, + { 0x40000, 0x0}, + { 0x40020, 0x0}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x0}, + { 0x40021, 0x0}, + { 0x40041, 0x0}, + { 0x40061, 0x0}, + { 0x40002, 0x0}, + { 0x40022, 0x0}, + { 0x40042, 0x0}, + { 0x40062, 0x0}, + { 0x40003, 0x0}, + { 0x40023, 0x0}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x0}, + { 0x40024, 0x0}, + { 0x40044, 0x0}, + { 0x40064, 0x0}, + { 0x40005, 0x0}, + { 0x40025, 0x0}, + { 0x40045, 0x0}, + { 0x40065, 0x0}, + { 0x40006, 0x0}, + { 0x40026, 0x0}, + { 0x40046, 0x0}, + { 0x40066, 0x0}, + { 0x40007, 0x0}, + { 0x40027, 0x0}, + { 0x40047, 0x0}, + { 0x40067, 0x0}, + { 0x40008, 0x0}, + { 0x40028, 0x0}, + { 0x40048, 0x0}, + { 0x40068, 0x0}, + { 0x40009, 0x0}, + { 0x40029, 0x0}, + { 0x40049, 0x0}, + { 0x40069, 0x0}, + { 0x4000a, 0x0}, + { 0x4002a, 0x0}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x0}, + { 0x4002b, 0x0}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x0}, + { 0x4002c, 0x0}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0x0}, + { 0x4002d, 0x0}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x0}, + { 0x4002e, 0x0}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x0}, + { 0x4002f, 0x0}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x0}, + { 0x40030, 0x0}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x0}, + { 0x40031, 0x0}, + { 0x40051, 0x0}, + { 0x40071, 0x0}, + { 0x40012, 0x0}, + { 0x40032, 0x0}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x0}, + { 0x40033, 0x0}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x0}, + { 0x40034, 0x0}, + { 0x40054, 0x0}, + { 0x40074, 0x0}, + { 0x40015, 0x0}, + { 0x40035, 0x0}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x0}, + { 0x40036, 0x0}, + { 0x40056, 0x0}, + { 0x40076, 0x0}, + { 0x40017, 0x0}, + { 0x40037, 0x0}, + { 0x40057, 0x0}, + { 0x40077, 0x0}, + { 0x40018, 0x0}, + { 0x40038, 0x0}, + { 0x40058, 0x0}, + { 0x40078, 0x0}, + { 0x40019, 0x0}, + { 0x40039, 0x0}, + { 0x40059, 0x0}, + { 0x40079, 0x0}, + { 0x4001a, 0x0}, + { 0x4003a, 0x0}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x0}, + { 0x900ac, 0x0}, + { 0x900ad, 0x0}, + { 0x900ae, 0x0}, + { 0x900af, 0x0}, + { 0x900b0, 0x0}, + { 0x900b1, 0x0}, + { 0x900b2, 0x0}, + { 0x900b3, 0x0}, + { 0x900b4, 0x0}, + { 0x900b5, 0x0}, + { 0x900b6, 0x0}, + { 0x900b7, 0x0}, + { 0x900b8, 0x0}, + { 0x900b9, 0x0}, + { 0x900ba, 0x0}, + { 0x900bb, 0x0}, + { 0x900bc, 0x0}, + { 0x900bd, 0x0}, + { 0x900be, 0x0}, + { 0x900bf, 0x0}, + { 0x900c0, 0x0}, + { 0x900c1, 0x0}, + { 0x900c2, 0x0}, + { 0x900c3, 0x0}, + { 0x900c4, 0x0}, + { 0x900c5, 0x0}, + { 0x900c6, 0x0}, + { 0x900c7, 0x0}, + { 0x900c8, 0x0}, + { 0x900c9, 0x0}, + { 0x900ca, 0x0}, + { 0x900cb, 0x0}, + { 0x900cc, 0x0}, + { 0x900cd, 0x0}, + { 0x900ce, 0x0}, + { 0x900cf, 0x0}, + { 0x900d0, 0x0}, + { 0x900d1, 0x0}, + { 0x900d2, 0x0}, + { 0x900d3, 0x0}, + { 0x900d4, 0x0}, + { 0x900d5, 0x0}, + { 0x900d6, 0x0}, + { 0x900d7, 0x0}, + { 0x900d8, 0x0}, + { 0x900d9, 0x0}, + { 0x900da, 0x0}, + { 0x900db, 0x0}, + { 0x900dc, 0x0}, + { 0x900dd, 0x0}, + { 0x900de, 0x0}, + { 0x900df, 0x0}, + { 0x900e0, 0x0}, + { 0x900e1, 0x0}, + { 0x900e2, 0x0}, + { 0x900e3, 0x0}, + { 0x900e4, 0x0}, + { 0x900e5, 0x0}, + { 0x900e6, 0x0}, + { 0x900e7, 0x0}, + { 0x900e8, 0x0}, + { 0x900e9, 0x0}, + { 0x900ea, 0x0}, + { 0x900eb, 0x0}, + { 0x900ec, 0x0}, + { 0x900ed, 0x0}, + { 0x900ee, 0x0}, + { 0x900ef, 0x0}, + { 0x900f0, 0x0}, + { 0x900f1, 0x0}, + { 0x900f2, 0x0}, + { 0x900f3, 0x0}, + { 0x900f4, 0x0}, + { 0x900f5, 0x0}, + { 0x900f6, 0x0}, + { 0x900f7, 0x0}, + { 0x900f8, 0x0}, + { 0x900f9, 0x0}, + { 0x900fa, 0x0}, + { 0x900fb, 0x0}, + { 0x900fc, 0x0}, + { 0x900fd, 0x0}, + { 0x900fe, 0x0}, + { 0x900ff, 0x0}, + { 0x90100, 0x0}, + { 0x90101, 0x0}, + { 0x90102, 0x0}, + { 0x90103, 0x0}, + { 0x90104, 0x0}, + { 0x90105, 0x0}, + { 0x90106, 0x0}, + { 0x90107, 0x0}, + { 0x90108, 0x0}, + { 0x90109, 0x0}, + { 0x9010a, 0x0}, + { 0x9010b, 0x0}, + { 0x9010c, 0x0}, + { 0x9010d, 0x0}, + { 0x9010e, 0x0}, + { 0x9010f, 0x0}, + { 0x90110, 0x0}, + { 0x90111, 0x0}, + { 0x90112, 0x0}, + { 0x90113, 0x0}, + { 0x90114, 0x0}, + { 0x90115, 0x0}, + { 0x90116, 0x0}, + { 0x90117, 0x0}, + { 0x90118, 0x0}, + { 0x90119, 0x0}, + { 0x9011a, 0x0}, + { 0x9011b, 0x0}, + { 0x9011c, 0x0}, + { 0x9011d, 0x0}, + { 0x9011e, 0x0}, + { 0x9011f, 0x0}, + { 0x90120, 0x0}, + { 0x90121, 0x0}, + { 0x90122, 0x0}, + { 0x90123, 0x0}, + { 0x90124, 0x0}, + { 0x90125, 0x0}, + { 0x90126, 0x0}, + { 0x90127, 0x0}, + { 0x90128, 0x0}, + { 0x90129, 0x0}, + { 0x9012a, 0x0}, + { 0x9012b, 0x0}, + { 0x9012c, 0x0}, + { 0x9012d, 0x0}, + { 0x9012e, 0x0}, + { 0x9012f, 0x0}, + { 0x90130, 0x0}, + { 0x90131, 0x0}, + { 0x90132, 0x0}, + { 0x90133, 0x0}, + { 0x90134, 0x0}, + { 0x90135, 0x0}, + { 0x90136, 0x0}, + { 0x90137, 0x0}, + { 0x90138, 0x0}, + { 0x90139, 0x0}, + { 0x9013a, 0x0}, + { 0x9013b, 0x0}, + { 0x9013c, 0x0}, + { 0x9013d, 0x0}, + { 0x9013e, 0x0}, + { 0x9013f, 0x0}, + { 0x90140, 0x0}, + { 0x90141, 0x0}, + { 0x90142, 0x0}, + { 0x90143, 0x0}, + { 0x90144, 0x0}, + { 0x90145, 0x0}, + { 0x90146, 0x0}, + { 0x90147, 0x0}, + { 0x90148, 0x0}, + { 0x90149, 0x0}, + { 0x9014a, 0x0}, + { 0x9014b, 0x0}, + { 0x9014c, 0x0}, + { 0x9014d, 0x0}, + { 0x9014e, 0x0}, + { 0x9014f, 0x0}, + { 0x90150, 0x0}, + { 0x90151, 0x0}, + { 0x90152, 0x0}, + { 0x90153, 0x0}, + { 0x90154, 0x0}, + { 0x90155, 0x0}, + { 0x90156, 0x0}, + { 0x90157, 0x0}, + { 0x90158, 0x0}, + { 0x90159, 0x0}, + { 0x9015a, 0x0}, + { 0x9015b, 0x0}, + { 0x9015c, 0x0}, + { 0x9015d, 0x0}, + { 0x9015e, 0x0}, + { 0x9015f, 0x0}, + { 0x90160, 0x0}, + { 0x90161, 0x0}, + { 0x90162, 0x0}, + { 0x90163, 0x0}, + { 0x90164, 0x0}, + { 0x90165, 0x0}, + { 0x90166, 0x0}, + { 0x90167, 0x0}, + { 0x90168, 0x0}, + { 0x90169, 0x0}, + { 0x9016a, 0x0}, + { 0x9016b, 0x0}, + { 0x9016c, 0x0}, + { 0x9016d, 0x0}, + { 0x9016e, 0x0}, + { 0x9016f, 0x0}, + { 0x90170, 0x0}, + { 0x90171, 0x0}, + { 0x90172, 0x0}, + { 0x90173, 0x0}, + { 0x90174, 0x0}, + { 0x90175, 0x0}, + { 0x90176, 0x0}, + { 0x90177, 0x0}, + { 0x90178, 0x0}, + { 0x90179, 0x0}, + { 0x9017a, 0x0}, + { 0x9017b, 0x0}, + { 0x9017c, 0x0}, + { 0x9017d, 0x0}, + { 0x9017e, 0x0}, + { 0x9017f, 0x0}, + { 0x90180, 0x0}, + { 0x90181, 0x0}, + { 0x90182, 0x0}, + { 0x90183, 0x0}, + { 0x90184, 0x0}, + { 0x90006, 0x0}, + { 0x90007, 0x0}, + { 0x90008, 0x0}, + { 0x90009, 0x0}, + { 0x9000a, 0x0}, + { 0x9000b, 0x0}, + { 0xd00e7, 0x0}, + { 0x90017, 0x0}, + { 0x9001f, 0x0}, + { 0x90026, 0x0}, + { 0x400d0, 0x0}, + { 0x400d1, 0x0}, + { 0x400d2, 0x0}, + { 0x400d3, 0x0}, + { 0x400d4, 0x0}, + { 0x400d5, 0x0}, + { 0x400d6, 0x0}, + { 0x400d7, 0x0}, + { 0x200be, 0x0}, + { 0x2000b, 0x0}, + { 0x2000c, 0x0}, + { 0x2000d, 0x0}, + { 0x2000e, 0x0}, + { 0x12000b, 0x0}, + { 0x12000c, 0x0}, + { 0x12000d, 0x0}, + { 0x12000e, 0x0}, + { 0x22000b, 0x0}, + { 0x22000c, 0x0}, + { 0x22000d, 0x0}, + { 0x22000e, 0x0}, + { 0x9000c, 0x0}, + { 0x9000d, 0x0}, + { 0x9000e, 0x0}, + { 0x9000f, 0x0}, + { 0x90010, 0x0}, + { 0x90011, 0x0}, + { 0x90012, 0x0}, + { 0x90013, 0x0}, + { 0x20010, 0x0}, + { 0x20011, 0x0}, + { 0x120010, 0x0}, + { 0x120011, 0x0}, + { 0x40080, 0x0}, + { 0x40081, 0x0}, + { 0x40082, 0x0}, + { 0x40083, 0x0}, + { 0x40084, 0x0}, + { 0x40085, 0x0}, + { 0x140080, 0x0}, + { 0x140081, 0x0}, + { 0x140082, 0x0}, + { 0x140083, 0x0}, + { 0x140084, 0x0}, + { 0x140085, 0x0}, + { 0x240080, 0x0}, + { 0x240081, 0x0}, + { 0x240082, 0x0}, + { 0x240083, 0x0}, + { 0x240084, 0x0}, + { 0x240085, 0x0}, + { 0x400fd, 0x0}, + { 0x400f1, 0x0}, + { 0x10011, 0x0}, + { 0x10012, 0x0}, + { 0x10013, 0x0}, + { 0x10018, 0x0}, + { 0x10002, 0x0}, + { 0x100b2, 0x0}, + { 0x101b4, 0x0}, + { 0x102b4, 0x0}, + { 0x103b4, 0x0}, + { 0x104b4, 0x0}, + { 0x105b4, 0x0}, + { 0x106b4, 0x0}, + { 0x107b4, 0x0}, + { 0x108b4, 0x0}, + { 0x11011, 0x0}, + { 0x11012, 0x0}, + { 0x11013, 0x0}, + { 0x11018, 0x0}, + { 0x11002, 0x0}, + { 0x110b2, 0x0}, + { 0x111b4, 0x0}, + { 0x112b4, 0x0}, + { 0x113b4, 0x0}, + { 0x114b4, 0x0}, + { 0x115b4, 0x0}, + { 0x116b4, 0x0}, + { 0x117b4, 0x0}, + { 0x118b4, 0x0}, + { 0x20089, 0x0}, + { 0xc0080, 0x0}, + { 0x200cb, 0x0}, + { 0x10068, 0x0}, + { 0x10069, 0x0}, + { 0x10168, 0x0}, + { 0x10169, 0x0}, + { 0x10268, 0x0}, + { 0x10269, 0x0}, + { 0x10368, 0x0}, + { 0x10369, 0x0}, + { 0x10468, 0x0}, + { 0x10469, 0x0}, + { 0x10568, 0x0}, + { 0x10569, 0x0}, + { 0x10668, 0x0}, + { 0x10669, 0x0}, + { 0x10768, 0x0}, + { 0x10769, 0x0}, + { 0x10868, 0x0}, + { 0x10869, 0x0}, + { 0x100aa, 0x0}, + { 0x10062, 0x0}, + { 0x10001, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x11068, 0x0}, + { 0x11069, 0x0}, + { 0x11168, 0x0}, + { 0x11169, 0x0}, + { 0x11268, 0x0}, + { 0x11269, 0x0}, + { 0x11368, 0x0}, + { 0x11369, 0x0}, + { 0x11468, 0x0}, + { 0x11469, 0x0}, + { 0x11568, 0x0}, + { 0x11569, 0x0}, + { 0x11668, 0x0}, + { 0x11669, 0x0}, + { 0x11768, 0x0}, + { 0x11769, 0x0}, + { 0x11868, 0x0}, + { 0x11869, 0x0}, + { 0x110aa, 0x0}, + { 0x11062, 0x0}, + { 0x11001, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x80, 0x0}, + { 0x1080, 0x0}, + { 0x2080, 0x0}, + { 0x10020, 0x0}, + { 0x10080, 0x0}, + { 0x10081, 0x0}, + { 0x100d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1008c, 0x0}, + { 0x1008d, 0x0}, + { 0x10180, 0x0}, + { 0x10181, 0x0}, + { 0x101d0, 0x0}, + { 0x101d1, 0x0}, + { 0x1018c, 0x0}, + { 0x1018d, 0x0}, + { 0x100c0, 0x0}, + { 0x100c1, 0x0}, + { 0x101c0, 0x0}, + { 0x101c1, 0x0}, + { 0x102c0, 0x0}, + { 0x102c1, 0x0}, + { 0x103c0, 0x0}, + { 0x103c1, 0x0}, + { 0x104c0, 0x0}, + { 0x104c1, 0x0}, + { 0x105c0, 0x0}, + { 0x105c1, 0x0}, + { 0x106c0, 0x0}, + { 0x106c1, 0x0}, + { 0x107c0, 0x0}, + { 0x107c1, 0x0}, + { 0x108c0, 0x0}, + { 0x108c1, 0x0}, + { 0x100ae, 0x0}, + { 0x100af, 0x0}, + { 0x11020, 0x0}, + { 0x11080, 0x0}, + { 0x11081, 0x0}, + { 0x110d0, 0x0}, + { 0x110d1, 0x0}, + { 0x1108c, 0x0}, + { 0x1108d, 0x0}, + { 0x11180, 0x0}, + { 0x11181, 0x0}, + { 0x111d0, 0x0}, + { 0x111d1, 0x0}, + { 0x1118c, 0x0}, + { 0x1118d, 0x0}, + { 0x110c0, 0x0}, + { 0x110c1, 0x0}, + { 0x111c0, 0x0}, + { 0x111c1, 0x0}, + { 0x112c0, 0x0}, + { 0x112c1, 0x0}, + { 0x113c0, 0x0}, + { 0x113c1, 0x0}, + { 0x114c0, 0x0}, + { 0x114c1, 0x0}, + { 0x115c0, 0x0}, + { 0x115c1, 0x0}, + { 0x116c0, 0x0}, + { 0x116c1, 0x0}, + { 0x117c0, 0x0}, + { 0x117c1, 0x0}, + { 0x118c0, 0x0}, + { 0x118c1, 0x0}, + { 0x110ae, 0x0}, + { 0x110af, 0x0}, + { 0x90201, 0x0}, + { 0x90202, 0x0}, + { 0x90203, 0x0}, + { 0x90205, 0x0}, + { 0x90206, 0x0}, + { 0x90207, 0x0}, + { 0x90208, 0x0}, + { 0x20020, 0x0}, + { 0x100080, 0x0}, + { 0x101080, 0x0}, + { 0x102080, 0x0}, + { 0x110020, 0x0}, + { 0x110080, 0x0}, + { 0x110081, 0x0}, + { 0x1100d0, 0x0}, + { 0x1100d1, 0x0}, + { 0x11008c, 0x0}, + { 0x11008d, 0x0}, + { 0x110180, 0x0}, + { 0x110181, 0x0}, + { 0x1101d0, 0x0}, + { 0x1101d1, 0x0}, + { 0x11018c, 0x0}, + { 0x11018d, 0x0}, + { 0x1100c0, 0x0}, + { 0x1100c1, 0x0}, + { 0x1101c0, 0x0}, + { 0x1101c1, 0x0}, + { 0x1102c0, 0x0}, + { 0x1102c1, 0x0}, + { 0x1103c0, 0x0}, + { 0x1103c1, 0x0}, + { 0x1104c0, 0x0}, + { 0x1104c1, 0x0}, + { 0x1105c0, 0x0}, + { 0x1105c1, 0x0}, + { 0x1106c0, 0x0}, + { 0x1106c1, 0x0}, + { 0x1107c0, 0x0}, + { 0x1107c1, 0x0}, + { 0x1108c0, 0x0}, + { 0x1108c1, 0x0}, + { 0x1100ae, 0x0}, + { 0x1100af, 0x0}, + { 0x111020, 0x0}, + { 0x111080, 0x0}, + { 0x111081, 0x0}, + { 0x1110d0, 0x0}, + { 0x1110d1, 0x0}, + { 0x11108c, 0x0}, + { 0x11108d, 0x0}, + { 0x111180, 0x0}, + { 0x111181, 0x0}, + { 0x1111d0, 0x0}, + { 0x1111d1, 0x0}, + { 0x11118c, 0x0}, + { 0x11118d, 0x0}, + { 0x1110c0, 0x0}, + { 0x1110c1, 0x0}, + { 0x1111c0, 0x0}, + { 0x1111c1, 0x0}, + { 0x1112c0, 0x0}, + { 0x1112c1, 0x0}, + { 0x1113c0, 0x0}, + { 0x1113c1, 0x0}, + { 0x1114c0, 0x0}, + { 0x1114c1, 0x0}, + { 0x1115c0, 0x0}, + { 0x1115c1, 0x0}, + { 0x1116c0, 0x0}, + { 0x1116c1, 0x0}, + { 0x1117c0, 0x0}, + { 0x1117c1, 0x0}, + { 0x1118c0, 0x0}, + { 0x1118c1, 0x0}, + { 0x1110ae, 0x0}, + { 0x1110af, 0x0}, + { 0x190201, 0x0}, + { 0x190202, 0x0}, + { 0x190203, 0x0}, + { 0x190205, 0x0}, + { 0x190206, 0x0}, + { 0x190207, 0x0}, + { 0x190208, 0x0}, + { 0x120020, 0x0}, + { 0x200080, 0x0}, + { 0x201080, 0x0}, + { 0x202080, 0x0}, + { 0x210020, 0x0}, + { 0x210080, 0x0}, + { 0x210081, 0x0}, + { 0x2100d0, 0x0}, + { 0x2100d1, 0x0}, + { 0x21008c, 0x0}, + { 0x21008d, 0x0}, + { 0x210180, 0x0}, + { 0x210181, 0x0}, + { 0x2101d0, 0x0}, + { 0x2101d1, 0x0}, + { 0x21018c, 0x0}, + { 0x21018d, 0x0}, + { 0x2100c0, 0x0}, + { 0x2100c1, 0x0}, + { 0x2101c0, 0x0}, + { 0x2101c1, 0x0}, + { 0x2102c0, 0x0}, + { 0x2102c1, 0x0}, + { 0x2103c0, 0x0}, + { 0x2103c1, 0x0}, + { 0x2104c0, 0x0}, + { 0x2104c1, 0x0}, + { 0x2105c0, 0x0}, + { 0x2105c1, 0x0}, + { 0x2106c0, 0x0}, + { 0x2106c1, 0x0}, + { 0x2107c0, 0x0}, + { 0x2107c1, 0x0}, + { 0x2108c0, 0x0}, + { 0x2108c1, 0x0}, + { 0x2100ae, 0x0}, + { 0x2100af, 0x0}, + { 0x211020, 0x0}, + { 0x211080, 0x0}, + { 0x211081, 0x0}, + { 0x2110d0, 0x0}, + { 0x2110d1, 0x0}, + { 0x21108c, 0x0}, + { 0x21108d, 0x0}, + { 0x211180, 0x0}, + { 0x211181, 0x0}, + { 0x2111d0, 0x0}, + { 0x2111d1, 0x0}, + { 0x21118c, 0x0}, + { 0x21118d, 0x0}, + { 0x2110c0, 0x0}, + { 0x2110c1, 0x0}, + { 0x2111c0, 0x0}, + { 0x2111c1, 0x0}, + { 0x2112c0, 0x0}, + { 0x2112c1, 0x0}, + { 0x2113c0, 0x0}, + { 0x2113c1, 0x0}, + { 0x2114c0, 0x0}, + { 0x2114c1, 0x0}, + { 0x2115c0, 0x0}, + { 0x2115c1, 0x0}, + { 0x2116c0, 0x0}, + { 0x2116c1, 0x0}, + { 0x2117c0, 0x0}, + { 0x2117c1, 0x0}, + { 0x2118c0, 0x0}, + { 0x2118c1, 0x0}, + { 0x2110ae, 0x0}, + { 0x2110af, 0x0}, + { 0x290201, 0x0}, + { 0x290202, 0x0}, + { 0x290203, 0x0}, + { 0x290205, 0x0}, + { 0x290206, 0x0}, + { 0x290207, 0x0}, + { 0x290208, 0x0}, + { 0x220020, 0x0}, + { 0x20077, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x400c0, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, +}; + +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x131f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x1}, + { 0x54003, 0x74a}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x1bb4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x1bb4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xb400}, + { 0x54033, 0x321b}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xb400}, + { 0x54039, 0x321b}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x102}, + { 0x54003, 0x270}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x994}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1100}, + { 0x5401e, 0x4}, + { 0x5401f, 0x994}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1100}, + { 0x54024, 0x4}, + { 0x54032, 0x9400}, + { 0x54033, 0x3209}, + { 0x54034, 0x2600}, + { 0x54035, 0x11}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0x9400}, + { 0x54039, 0x3209}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x11}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x61}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54010, 0x2080}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0}, + { 0x90000, 0x10}, + { 0x90001, 0x400}, + { 0x90002, 0x10e}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x8}, + { 0x90029, 0xb}, + { 0x9002a, 0x480}, + { 0x9002b, 0x109}, + { 0x9002c, 0x8}, + { 0x9002d, 0x448}, + { 0x9002e, 0x139}, + { 0x9002f, 0x8}, + { 0x90030, 0x478}, + { 0x90031, 0x109}, + { 0x90032, 0x0}, + { 0x90033, 0xe8}, + { 0x90034, 0x109}, + { 0x90035, 0x2}, + { 0x90036, 0x10}, + { 0x90037, 0x139}, + { 0x90038, 0xb}, + { 0x90039, 0x7c0}, + { 0x9003a, 0x139}, + { 0x9003b, 0x44}, + { 0x9003c, 0x633}, + { 0x9003d, 0x159}, + { 0x9003e, 0x14f}, + { 0x9003f, 0x630}, + { 0x90040, 0x159}, + { 0x90041, 0x47}, + { 0x90042, 0x633}, + { 0x90043, 0x149}, + { 0x90044, 0x4f}, + { 0x90045, 0x633}, + { 0x90046, 0x179}, + { 0x90047, 0x8}, + { 0x90048, 0xe0}, + { 0x90049, 0x109}, + { 0x9004a, 0x0}, + { 0x9004b, 0x7c8}, + { 0x9004c, 0x109}, + { 0x9004d, 0x0}, + { 0x9004e, 0x1}, + { 0x9004f, 0x8}, + { 0x90050, 0x30}, + { 0x90051, 0x65a}, + { 0x90052, 0x9}, + { 0x90053, 0x0}, + { 0x90054, 0x45a}, + { 0x90055, 0x9}, + { 0x90056, 0x0}, + { 0x90057, 0x448}, + { 0x90058, 0x109}, + { 0x90059, 0x40}, + { 0x9005a, 0x633}, + { 0x9005b, 0x179}, + { 0x9005c, 0x1}, + { 0x9005d, 0x618}, + { 0x9005e, 0x109}, + { 0x9005f, 0x40c0}, + { 0x90060, 0x633}, + { 0x90061, 0x149}, + { 0x90062, 0x8}, + { 0x90063, 0x4}, + { 0x90064, 0x48}, + { 0x90065, 0x4040}, + { 0x90066, 0x633}, + { 0x90067, 0x149}, + { 0x90068, 0x0}, + { 0x90069, 0x4}, + { 0x9006a, 0x48}, + { 0x9006b, 0x40}, + { 0x9006c, 0x633}, + { 0x9006d, 0x149}, + { 0x9006e, 0x0}, + { 0x9006f, 0x658}, + { 0x90070, 0x109}, + { 0x90071, 0x10}, + { 0x90072, 0x4}, + { 0x90073, 0x18}, + { 0x90074, 0x0}, + { 0x90075, 0x4}, + { 0x90076, 0x78}, + { 0x90077, 0x549}, + { 0x90078, 0x633}, + { 0x90079, 0x159}, + { 0x9007a, 0xd49}, + { 0x9007b, 0x633}, + { 0x9007c, 0x159}, + { 0x9007d, 0x94a}, + { 0x9007e, 0x633}, + { 0x9007f, 0x159}, + { 0x90080, 0x441}, + { 0x90081, 0x633}, + { 0x90082, 0x149}, + { 0x90083, 0x42}, + { 0x90084, 0x633}, + { 0x90085, 0x149}, + { 0x90086, 0x1}, + { 0x90087, 0x633}, + { 0x90088, 0x149}, + { 0x90089, 0x0}, + { 0x9008a, 0xe0}, + { 0x9008b, 0x109}, + { 0x9008c, 0xa}, + { 0x9008d, 0x10}, + { 0x9008e, 0x109}, + { 0x9008f, 0x9}, + { 0x90090, 0x3c0}, + { 0x90091, 0x149}, + { 0x90092, 0x9}, + { 0x90093, 0x3c0}, + { 0x90094, 0x159}, + { 0x90095, 0x18}, + { 0x90096, 0x10}, + { 0x90097, 0x109}, + { 0x90098, 0x0}, + { 0x90099, 0x3c0}, + { 0x9009a, 0x109}, + { 0x9009b, 0x18}, + { 0x9009c, 0x4}, + { 0x9009d, 0x48}, + { 0x9009e, 0x18}, + { 0x9009f, 0x4}, + { 0x900a0, 0x58}, + { 0x900a1, 0xb}, + { 0x900a2, 0x10}, + { 0x900a3, 0x109}, + { 0x900a4, 0x1}, + { 0x900a5, 0x10}, + { 0x900a6, 0x109}, + { 0x900a7, 0x5}, + { 0x900a8, 0x7c0}, + { 0x900a9, 0x109}, + { 0x40000, 0x811}, + { 0x40020, 0x880}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x4008}, + { 0x40021, 0x83}, + { 0x40041, 0x4f}, + { 0x40061, 0x0}, + { 0x40002, 0x4040}, + { 0x40022, 0x83}, + { 0x40042, 0x51}, + { 0x40062, 0x0}, + { 0x40003, 0x811}, + { 0x40023, 0x880}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x720}, + { 0x40024, 0xf}, + { 0x40044, 0x1740}, + { 0x40064, 0x0}, + { 0x40005, 0x16}, + { 0x40025, 0x83}, + { 0x40045, 0x4b}, + { 0x40065, 0x0}, + { 0x40006, 0x716}, + { 0x40026, 0xf}, + { 0x40046, 0x2001}, + { 0x40066, 0x0}, + { 0x40007, 0x716}, + { 0x40027, 0xf}, + { 0x40047, 0x2800}, + { 0x40067, 0x0}, + { 0x40008, 0x716}, + { 0x40028, 0xf}, + { 0x40048, 0xf00}, + { 0x40068, 0x0}, + { 0x40009, 0x720}, + { 0x40029, 0xf}, + { 0x40049, 0x1400}, + { 0x40069, 0x0}, + { 0x4000a, 0xe08}, + { 0x4002a, 0xc15}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x625}, + { 0x4002b, 0x15}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x4028}, + { 0x4002c, 0x80}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0xe08}, + { 0x4002d, 0xc1a}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x625}, + { 0x4002e, 0x1a}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x4040}, + { 0x4002f, 0x80}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x2604}, + { 0x40030, 0x15}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x708}, + { 0x40031, 0x5}, + { 0x40051, 0x0}, + { 0x40071, 0x2002}, + { 0x40012, 0x8}, + { 0x40032, 0x80}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x2604}, + { 0x40033, 0x1a}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x708}, + { 0x40034, 0xa}, + { 0x40054, 0x0}, + { 0x40074, 0x2002}, + { 0x40015, 0x4040}, + { 0x40035, 0x80}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x60a}, + { 0x40036, 0x15}, + { 0x40056, 0x1200}, + { 0x40076, 0x0}, + { 0x40017, 0x61a}, + { 0x40037, 0x15}, + { 0x40057, 0x1300}, + { 0x40077, 0x0}, + { 0x40018, 0x60a}, + { 0x40038, 0x1a}, + { 0x40058, 0x1200}, + { 0x40078, 0x0}, + { 0x40019, 0x642}, + { 0x40039, 0x1a}, + { 0x40059, 0x1300}, + { 0x40079, 0x0}, + { 0x4001a, 0x4808}, + { 0x4003a, 0x880}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x790}, + { 0x900ac, 0x11a}, + { 0x900ad, 0x8}, + { 0x900ae, 0x7aa}, + { 0x900af, 0x2a}, + { 0x900b0, 0x10}, + { 0x900b1, 0x7b2}, + { 0x900b2, 0x2a}, + { 0x900b3, 0x0}, + { 0x900b4, 0x7c8}, + { 0x900b5, 0x109}, + { 0x900b6, 0x10}, + { 0x900b7, 0x10}, + { 0x900b8, 0x109}, + { 0x900b9, 0x10}, + { 0x900ba, 0x2a8}, + { 0x900bb, 0x129}, + { 0x900bc, 0x8}, + { 0x900bd, 0x370}, + { 0x900be, 0x129}, + { 0x900bf, 0xa}, + { 0x900c0, 0x3c8}, + { 0x900c1, 0x1a9}, + { 0x900c2, 0xc}, + { 0x900c3, 0x408}, + { 0x900c4, 0x199}, + { 0x900c5, 0x14}, + { 0x900c6, 0x790}, + { 0x900c7, 0x11a}, + { 0x900c8, 0x8}, + { 0x900c9, 0x4}, + { 0x900ca, 0x18}, + { 0x900cb, 0xe}, + { 0x900cc, 0x408}, + { 0x900cd, 0x199}, + { 0x900ce, 0x8}, + { 0x900cf, 0x8568}, + { 0x900d0, 0x108}, + { 0x900d1, 0x18}, + { 0x900d2, 0x790}, + { 0x900d3, 0x16a}, + { 0x900d4, 0x8}, + { 0x900d5, 0x1d8}, + { 0x900d6, 0x169}, + { 0x900d7, 0x10}, + { 0x900d8, 0x8558}, + { 0x900d9, 0x168}, + { 0x900da, 0x1ff8}, + { 0x900db, 0x85a8}, + { 0x900dc, 0x1e8}, + { 0x900dd, 0x50}, + { 0x900de, 0x798}, + { 0x900df, 0x16a}, + { 0x900e0, 0x60}, + { 0x900e1, 0x7a0}, + { 0x900e2, 0x16a}, + { 0x900e3, 0x8}, + { 0x900e4, 0x8310}, + { 0x900e5, 0x168}, + { 0x900e6, 0x8}, + { 0x900e7, 0xa310}, + { 0x900e8, 0x168}, + { 0x900e9, 0xa}, + { 0x900ea, 0x408}, + { 0x900eb, 0x169}, + { 0x900ec, 0x6e}, + { 0x900ed, 0x0}, + { 0x900ee, 0x68}, + { 0x900ef, 0x0}, + { 0x900f0, 0x408}, + { 0x900f1, 0x169}, + { 0x900f2, 0x0}, + { 0x900f3, 0x8310}, + { 0x900f4, 0x168}, + { 0x900f5, 0x0}, + { 0x900f6, 0xa310}, + { 0x900f7, 0x168}, + { 0x900f8, 0x1ff8}, + { 0x900f9, 0x85a8}, + { 0x900fa, 0x1e8}, + { 0x900fb, 0x68}, + { 0x900fc, 0x798}, + { 0x900fd, 0x16a}, + { 0x900fe, 0x78}, + { 0x900ff, 0x7a0}, + { 0x90100, 0x16a}, + { 0x90101, 0x68}, + { 0x90102, 0x790}, + { 0x90103, 0x16a}, + { 0x90104, 0x8}, + { 0x90105, 0x8b10}, + { 0x90106, 0x168}, + { 0x90107, 0x8}, + { 0x90108, 0xab10}, + { 0x90109, 0x168}, + { 0x9010a, 0xa}, + { 0x9010b, 0x408}, + { 0x9010c, 0x169}, + { 0x9010d, 0x58}, + { 0x9010e, 0x0}, + { 0x9010f, 0x68}, + { 0x90110, 0x0}, + { 0x90111, 0x408}, + { 0x90112, 0x169}, + { 0x90113, 0x0}, + { 0x90114, 0x8b10}, + { 0x90115, 0x168}, + { 0x90116, 0x1}, + { 0x90117, 0xab10}, + { 0x90118, 0x168}, + { 0x90119, 0x0}, + { 0x9011a, 0x1d8}, + { 0x9011b, 0x169}, + { 0x9011c, 0x80}, + { 0x9011d, 0x790}, + { 0x9011e, 0x16a}, + { 0x9011f, 0x18}, + { 0x90120, 0x7aa}, + { 0x90121, 0x6a}, + { 0x90122, 0xa}, + { 0x90123, 0x0}, + { 0x90124, 0x1e9}, + { 0x90125, 0x8}, + { 0x90126, 0x8080}, + { 0x90127, 0x108}, + { 0x90128, 0xf}, + { 0x90129, 0x408}, + { 0x9012a, 0x169}, + { 0x9012b, 0xc}, + { 0x9012c, 0x0}, + { 0x9012d, 0x68}, + { 0x9012e, 0x9}, + { 0x9012f, 0x0}, + { 0x90130, 0x1a9}, + { 0x90131, 0x0}, + { 0x90132, 0x408}, + { 0x90133, 0x169}, + { 0x90134, 0x0}, + { 0x90135, 0x8080}, + { 0x90136, 0x108}, + { 0x90137, 0x8}, + { 0x90138, 0x7aa}, + { 0x90139, 0x6a}, + { 0x9013a, 0x0}, + { 0x9013b, 0x8568}, + { 0x9013c, 0x108}, + { 0x9013d, 0xb7}, + { 0x9013e, 0x790}, + { 0x9013f, 0x16a}, + { 0x90140, 0x1f}, + { 0x90141, 0x0}, + { 0x90142, 0x68}, + { 0x90143, 0x8}, + { 0x90144, 0x8558}, + { 0x90145, 0x168}, + { 0x90146, 0xf}, + { 0x90147, 0x408}, + { 0x90148, 0x169}, + { 0x90149, 0xd}, + { 0x9014a, 0x0}, + { 0x9014b, 0x68}, + { 0x9014c, 0x0}, + { 0x9014d, 0x408}, + { 0x9014e, 0x169}, + { 0x9014f, 0x0}, + { 0x90150, 0x8558}, + { 0x90151, 0x168}, + { 0x90152, 0x8}, + { 0x90153, 0x3c8}, + { 0x90154, 0x1a9}, + { 0x90155, 0x3}, + { 0x90156, 0x370}, + { 0x90157, 0x129}, + { 0x90158, 0x20}, + { 0x90159, 0x2aa}, + { 0x9015a, 0x9}, + { 0x9015b, 0x8}, + { 0x9015c, 0xe8}, + { 0x9015d, 0x109}, + { 0x9015e, 0x0}, + { 0x9015f, 0x8140}, + { 0x90160, 0x10c}, + { 0x90161, 0x10}, + { 0x90162, 0x8138}, + { 0x90163, 0x104}, + { 0x90164, 0x8}, + { 0x90165, 0x448}, + { 0x90166, 0x109}, + { 0x90167, 0xf}, + { 0x90168, 0x7c0}, + { 0x90169, 0x109}, + { 0x9016a, 0x0}, + { 0x9016b, 0xe8}, + { 0x9016c, 0x109}, + { 0x9016d, 0x47}, + { 0x9016e, 0x630}, + { 0x9016f, 0x109}, + { 0x90170, 0x8}, + { 0x90171, 0x618}, + { 0x90172, 0x109}, + { 0x90173, 0x8}, + { 0x90174, 0xe0}, + { 0x90175, 0x109}, + { 0x90176, 0x0}, + { 0x90177, 0x7c8}, + { 0x90178, 0x109}, + { 0x90179, 0x8}, + { 0x9017a, 0x8140}, + { 0x9017b, 0x10c}, + { 0x9017c, 0x0}, + { 0x9017d, 0x478}, + { 0x9017e, 0x109}, + { 0x9017f, 0x0}, + { 0x90180, 0x1}, + { 0x90181, 0x8}, + { 0x90182, 0x8}, + { 0x90183, 0x4}, + { 0x90184, 0x0}, + { 0x90006, 0x8}, + { 0x90007, 0x7c8}, + { 0x90008, 0x109}, + { 0x90009, 0x0}, + { 0x9000a, 0x400}, + { 0x9000b, 0x106}, + { 0xd00e7, 0x400}, + { 0x90017, 0x0}, + { 0x9001f, 0x2b}, + { 0x90026, 0x69}, + { 0x400d0, 0x0}, + { 0x400d1, 0x101}, + { 0x400d2, 0x105}, + { 0x400d3, 0x107}, + { 0x400d4, 0x10f}, + { 0x400d5, 0x202}, + { 0x400d6, 0x20a}, + { 0x400d7, 0x20b}, + { 0x2003a, 0x2}, + { 0x200be, 0x3}, + { 0x2000b, 0x75}, + { 0x2000c, 0xe9}, + { 0x2000d, 0x91c}, + { 0x2000e, 0x2c}, + { 0x12000b, 0x3b}, + { 0x12000c, 0x74}, + { 0x12000d, 0x48e}, + { 0x12000e, 0x2c}, + { 0x22000b, 0x14}, + { 0x22000c, 0x27}, + { 0x22000d, 0x186}, + { 0x22000e, 0x10}, + { 0x9000c, 0x0}, + { 0x9000d, 0x173}, + { 0x9000e, 0x60}, + { 0x9000f, 0x6110}, + { 0x90010, 0x2152}, + { 0x90011, 0xdfbd}, + { 0x90012, 0x2060}, + { 0x90013, 0x6152}, + { 0x20010, 0x5a}, + { 0x20011, 0x3}, + { 0x120010, 0x5a}, + { 0x120011, 0x3}, + { 0x40080, 0xe0}, + { 0x40081, 0x12}, + { 0x40082, 0xe0}, + { 0x40083, 0x12}, + { 0x40084, 0xe0}, + { 0x40085, 0x12}, + { 0x140080, 0xe0}, + { 0x140081, 0x12}, + { 0x140082, 0xe0}, + { 0x140083, 0x12}, + { 0x140084, 0xe0}, + { 0x140085, 0x12}, + { 0x240080, 0xe0}, + { 0x240081, 0x12}, + { 0x240082, 0xe0}, + { 0x240083, 0x12}, + { 0x240084, 0xe0}, + { 0x240085, 0x12}, + { 0x400fd, 0xf}, + { 0x400f1, 0xe}, + { 0x10011, 0x1}, + { 0x10012, 0x1}, + { 0x10013, 0x180}, + { 0x10018, 0x1}, + { 0x10002, 0x6209}, + { 0x100b2, 0x1}, + { 0x101b4, 0x1}, + { 0x102b4, 0x1}, + { 0x103b4, 0x1}, + { 0x104b4, 0x1}, + { 0x105b4, 0x1}, + { 0x106b4, 0x1}, + { 0x107b4, 0x1}, + { 0x108b4, 0x1}, + { 0x11011, 0x1}, + { 0x11012, 0x1}, + { 0x11013, 0x180}, + { 0x11018, 0x1}, + { 0x11002, 0x6209}, + { 0x110b2, 0x1}, + { 0x111b4, 0x1}, + { 0x112b4, 0x1}, + { 0x113b4, 0x1}, + { 0x114b4, 0x1}, + { 0x115b4, 0x1}, + { 0x116b4, 0x1}, + { 0x117b4, 0x1}, + { 0x118b4, 0x1}, + { 0x20089, 0x1}, + { 0x20088, 0x19}, + { 0xc0080, 0x0}, + /* workaround STAR_3256585 marker */ + { 0x2000b, 0x41a}, + /* workaround STAR_3256585 marker */ + { 0x12000b, 0x20d}, + /* workaround STAR_3256585 marker */ + { 0x22000b, 0xb0}, + { 0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2CS_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 068091ba0e9..40054ff72d0 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -33,9 +33,10 @@ static struct _drams { u8 mr8; struct dram_timing_info *pdram_timing; char *name; -} frdm_drams[2] = { +} frdm_drams[3] = { {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, + {0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" }, + {0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" }, }; int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index d669c6e3133..d14a1b6c9bd 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -10,6 +10,10 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c index 4731b79b55d..02149afae87 100644 --- a/board/nxp/imx94_evk/imx94_evk.c +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -7,7 +7,7 @@ #include <fdt_support.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/sys_proto.h> +#include <asm/arch/sys_proto.h> int board_init(void) { @@ -26,3 +26,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 894f5975812..c2006c95529 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -19,7 +19,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c index 6eb0fff99f4..739a5f1f559 100644 --- a/board/nxp/imx94_evk/spl.c +++ b/board/nxp/imx94_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c index 2a61817939e..b5c2da032a8 100644 --- a/board/nxp/imx952_evk/imx952_evk.c +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -24,3 +24,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env index 6ecaf9724c1..07faeb9fc9a 100644 --- a/board/nxp/imx952_evk/imx952_evk.env +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -52,7 +52,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c index de9256dc267..615c3b67fb6 100644 --- a/board/nxp/imx952_evk/spl.c +++ b/board/nxp/imx952_evk/spl.c @@ -8,6 +8,7 @@ #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> #include <asm/sections.h> #include <hang.h> #include <init.h> @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c index 99a37e0593f..394d6fd459c 100644 --- a/board/nxp/imx95_evk/imx95_evk.c +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -5,7 +5,7 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/sys_proto.h> +#include <asm/arch/sys_proto.h> int board_late_init(void) { @@ -14,3 +14,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index 19f9bd5c16e..1d63a74aefa 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -3,8 +3,11 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 splashimage=0xA0000000 console=ttyLP0,115200 earlycon fdt_addr_r=0x93000000 diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c index 761a1a4a0f6..2fd69447e1e 100644 --- a/board/nxp/imx95_evk/spl.c +++ b/board/nxp/imx95_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -13,6 +13,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } void board_init_f(ulong dummy) diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c index c431e5e611b..8761ec7845e 100644 --- a/board/nxp/ls1012afrdm/eth.c +++ b/board/nxp/ls1012afrdm/eth.c @@ -7,16 +7,6 @@ #include <dm.h> #include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1012ardb/Kconfig b/board/nxp/ls1012ardb/Kconfig index bbe5ce21109..ff5a57aaa41 100644 --- a/board/nxp/ls1012ardb/Kconfig +++ b/board/nxp/ls1012ardb/Kconfig @@ -63,7 +63,7 @@ config SYS_BOARD default "ls1012ardb" config SYS_VENDOR - default "nxp" + default "nxp" config SYS_SOC default "fsl-layerscape" diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c index 71cb2988a56..6a6f4608fd1 100644 --- a/board/nxp/ls1012ardb/eth.c +++ b/board/nxp/ls1012ardb/eth.c @@ -6,18 +6,6 @@ #include <config.h> #include <dm.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c index c92430c0896..277506fdbb8 100644 --- a/board/nxp/ls1021atsn/ls1021atsn.c +++ b/board/nxp/ls1021atsn/ls1021atsn.c @@ -123,11 +123,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c index 0758e5eae25..135497f7c5d 100644 --- a/board/nxp/ls1021atwr/ls1021atwr.c +++ b/board/nxp/ls1021atwr/ls1021atwr.c @@ -239,11 +239,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_serdes_mux(int type, int need_reset) { diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index db94d9c1fa8..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -26,7 +26,9 @@ #include <fdtdec.h> #include <miiphy.h> #include "../common/qixis.h" +#ifdef CONFIG_FSL_ENETC #include "../drivers/net/fsl_enetc.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -103,11 +105,6 @@ int board_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { @@ -152,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -205,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env new file mode 100644 index 00000000000..dc1cb01e50a --- /dev/null +++ b/board/nxp/ls1028a/ls1028ardb.env @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +board=ls1028ardb +hwconfig=fsl_ddr:bank_intlv=auto +fdtfile=fsl-ls1028a-rdb.dtb +image=Image +extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0 +othbootargs=video=1920x1080-32@60 cma=640M +ramdisk_addr=0x800000 +ramdisk_size=0x2000000 +bootm_size=0x10000000 +kernel_addr=0x01000000 +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +fdtheader_addr_r=0x80100000 +kernelheader_addr_r=0x80200000 +load_addr=0xa0000000 +kernel_addr_r=0x81000000 +fdt_addr_r=0x90000000 +ramdisk_addr_r=0xa0000000 +kernel_start=0x1000000 +kernelheader_start=0x600000 +kernel_load=0xa0000000 +kernel_size=0x2800000 +kernelheader_size=0x40000 +kernel_addr_sd=0x8000 +kernel_size_sd=0x14000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +console=ttyS0,115200 +console_dbg=earlycon=uart8250,mmio,0x21c0500 +boot_script_hdr=hdr_ls1028ardb_bs.out +xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr + $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r + $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm + $load_addr#$board +xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read + $load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000 +sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd + $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd + $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board +sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 +emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr + $kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r + $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm + $load_addr#$board +emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile index ff830788fd7..98ad49f6f0c 100644 --- a/board/nxp/ls1043aqds/Makefile +++ b/board/nxp/ls1043aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1043aqds.o diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c deleted file mode 100644 index 5a8ca27b327..00000000000 --- a/board/nxp/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <linux/libfdt.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index f043599fbb8..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,18 +542,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile index 95745bf3a9c..13e0411c1ba 100644 --- a/board/nxp/ls1043ardb/Makefile +++ b/board/nxp/ls1043ardb/Makefile @@ -5,6 +5,5 @@ obj-y += ddr.o obj-y += ls1043ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c deleted file mode 100644 index cacc49c0584..00000000000 --- a/board/nxp/ls1043ardb/eth.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <config.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/Makefile b/board/nxp/ls1046afrwy/Makefile index c70f5cda797..8594658d2fb 100644 --- a/board/nxp/ls1046afrwy/Makefile +++ b/board/nxp/ls1046afrwy/Makefile @@ -4,4 +4,4 @@ obj-y += ddr.o obj-y += ls1046afrwy.o -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c index 8efc7f68424..d76841c6ab4 100644 --- a/board/nxp/ls1046afrwy/eth.c +++ b/board/nxp/ls1046afrwy/eth.c @@ -4,64 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info dtsec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x3040: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(FM1_DTSEC6, dev); - fm_info_set_mdio(FM1_DTSEC5, dev); - fm_info_set_mdio(FM1_DTSEC10, dev); - fm_info_set_mdio(FM1_DTSEC1, dev); - - fm_disable_port(FM1_DTSEC9); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile index 365247d92bc..8292726b0e4 100644 --- a/board/nxp/ls1046aqds/Makefile +++ b/board/nxp/ls1046aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1046aqds.o diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c deleted file mode 100644 index cd3500c2e96..00000000000 --- a/board/nxp/ls1046aqds/eth.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2020 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1046aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT4 4 - -static const char * const mdio_names[] = { - "LS1046AQDS_MDIO_RGMII1", - "LS1046AQDS_MDIO_RGMII2", - "LS1046AQDS_MDIO_SLOT1", - "LS1046AQDS_MDIO_SLOT2", - "LS1046AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes 1 & 2 lanes to default slot. */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; -#endif - -static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI1_SLOT4) - return NULL; - - name = ls1046aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1046aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1046aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1046aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1046aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1046aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1046aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1046aqds_mdio_read; - bus->write = ls1046aqds_mdio_write; - bus->reset = ls1046aqds_mdio_reset; - sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - const char *phyconn; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - switch (port) { - case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); - break; - default: - break; - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII on QDS */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - (port == FM1_10GEC1 || port == FM1_10GEC2)) { - phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", port); - } else { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "xgmii"); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1, srds_s2; - u8 brdcfg12; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - srds_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x3333: - /* SGMII on slot 1, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - case 0x1333: - case 0x2333: - /* SGMII on slot 1, MAC 10 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1133: - case 0x2233: - /* SGMII on slot 1, MAC 5/6 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x1040: - case 0x2040: - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x3363: - /* SGMII on slot 1, MAC 9/10 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1163: - case 0x2263: - case 0x2223: - /* SGMII on slot 1, MAC 6 */ - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", - srds_s1); - break; - } - - if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) - /* SGMII on slot 4, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - if (i == FM1_DTSEC5) { - /* route lane 2 to slot1 so to have - * one sgmii riser card supports - * MAC5 and MAC6. - */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], - brdcfg12 | 0x80); - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else { - /* clear the bit 7 to route lane B on slot2. */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); - - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - lane_to_slot[lane] = 2; - } - - if (i == FM1_DTSEC2) - lane = 5; - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 7df12550868..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,18 +426,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1046ardb/Makefile b/board/nxp/ls1046ardb/Makefile index 9e5d24f53c8..355ccf59257 100644 --- a/board/nxp/ls1046ardb/Makefile +++ b/board/nxp/ls1046ardb/Makefile @@ -5,6 +5,6 @@ obj-y += ddr.o obj-y += ls1046ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c index fee8e0e21d4..ce9b7b81e3d 100644 --- a/board/nxp/ls1046ardb/eth.c +++ b/board/nxp/ls1046ardb/eth.c @@ -4,78 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* Set the two on-board SGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); - - /* Set the on-board AQ PHY address */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - - switch (srds_s1) { - case 0x1133: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 51ec055be63..8ea76fe3760 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -7,6 +7,7 @@ #include <display_options.h> #include <env.h> #include <i2c.h> +#include <pmbus.h> #include <init.h> #include <log.h> #include <malloc.h> @@ -667,13 +668,13 @@ int get_serdes_volt(void) /* Select the PAGE 0 using PMBus commands PAGE for VDD */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_write(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); + PMBUS_PAGE, 1, &chan, 1); #else struct udevice *dev; ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + ret = dm_i2c_write(dev, PMBUS_PAGE, &chan, 1); #endif @@ -685,9 +686,9 @@ int get_serdes_volt(void) /* Read the output voltage using PMBus command READ_VOUT */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_read(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); + PMBUS_READ_VOUT, 1, (void *)&vcode, 2); #else - dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + dm_i2c_read(dev, PMBUS_READ_VOUT, (void *)&vcode, 2); #endif if (ret) { printf("VID: failed to read the voltage\n"); @@ -700,7 +701,7 @@ int get_serdes_volt(void) int set_serdes_volt(int svdd) { int ret, vdd_last; - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ @@ -830,7 +831,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +960,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM @@ -974,7 +975,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c index 7d5beb32417..6a8859fd0c5 100644 --- a/board/nxp/ls2080ardb/eth_ls2080rdb.c +++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c @@ -9,25 +9,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ - -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index 6f824f57c47..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ @@ -503,7 +503,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c index 9939bb6f89e..4c16f565b69 100644 --- a/board/nxp/lx2160a/eth_lx2160aqds.c +++ b/board/nxp/lx2160a/eth_lx2160aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c index 90e7c9100e1..31bbac6310e 100644 --- a/board/nxp/lx2160a/eth_lx2160ardb.c +++ b/board/nxp/lx2160a/eth_lx2160ardb.c @@ -11,23 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c index 805aa705be9..81b81d47978 100644 --- a/board/nxp/lx2160a/eth_lx2162aqds.c +++ b/board/nxp/lx2160a/eth_lx2162aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index 341f82ce724..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -242,13 +242,17 @@ int init_func_vid(void) return 0; } -#endif EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); +#endif int checkboard(void) { - enum boot_src src = get_boot_src(); char buf[64]; + + cpu_name(buf); + +#if IS_ENABLED(CONFIG_FSL_QIXIS) + enum boot_src src = get_boot_src(); u8 sw; #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; @@ -258,7 +262,6 @@ int checkboard(void) "100 separate SSCG"}; #endif - cpu_name(buf); #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else @@ -325,7 +328,10 @@ int checkboard(void) clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); #endif -#endif +#endif /* LX2160ARDB-inside-QIXIS switch */ +#else /* !CONFIG_FSL_QIXIS */ + printf("Board: %s\n", buf); +#endif /* CONFIG_FSL_QIXIS */ return 0; } @@ -554,7 +560,7 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) pci_init(); #endif return 0; @@ -567,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); +#if IS_ENABLED(CONFIG_FSL_MC_ENET) fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); +#endif if (mc_memory_base != 0) mc_memory_bank++; @@ -800,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM @@ -818,7 +826,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c index 50c5320b55c..7d4b60b283e 100644 --- a/board/nxp/m5253demo/m5253demo.c +++ b/board/nxp/m5253demo/m5253demo.c @@ -133,10 +133,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_IDE */ - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/board/nxp/m53017evb/README b/board/nxp/m53017evb/README index 25831629266..c6dc020af37 100644 --- a/board/nxp/m53017evb/README +++ b/board/nxp/m53017evb/README @@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/m5373evb/README b/board/nxp/m5373evb/README index c7130b32251..7217886fdfa 100644 --- a/board/nxp/m5373evb/README +++ b/board/nxp/m5373evb/README @@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/mx6memcal/Kconfig b/board/nxp/mx6memcal/Kconfig index a6c39d5e4d1..03d8422242f 100644 --- a/board/nxp/mx6memcal/Kconfig +++ b/board/nxp/mx6memcal/Kconfig @@ -35,30 +35,30 @@ choice The choices below reflect the most commonly used options for your UART. - config UART2_EIM_D26_27 - bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" - depends on SERIAL_CONSOLE_UART2 - help - Choose this configuration if you're using pads - EIM_D26 and D27 for a console on UART2. - This is typical for designs that are based on the - NXP SABRELite. +config UART2_EIM_D26_27 + bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" + depends on SERIAL_CONSOLE_UART2 + help + Choose this configuration if you're using pads + EIM_D26 and D27 for a console on UART2. + This is typical for designs that are based on the + NXP SABRELite. - config UART1_CSI0_DAT10_11 - bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - CSI0_DAT10 and DAT11 for a console on UART1 as - is done on the i.MX6 Wand board and i.MX6 SabreSD. +config UART1_CSI0_DAT10_11 + bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + CSI0_DAT10 and DAT11 for a console on UART1 as + is done on the i.MX6 Wand board and i.MX6 SabreSD. - config UART1_UART1 - bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - UART1_TXD/RXD for a console on UART1 as is done - on most i.MX6SL designs. +config UART1_UART1 + bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + UART1_TXD/RXD for a console on UART1 as is done + on most i.MX6SL designs. endchoice @@ -215,12 +215,12 @@ config REFR range 0 7 default 7 help - This selects the number of refreshes (-1) during each period. - i.e.: - 0 == 1 refresh (tRFC) - 7 == 8 refreshes (tRFC*8) - See the description of MDREF[REFR] in the reference manual for - details. + This selects the number of refreshes (-1) during each period. + i.e.: + 0 == 1 refresh (tRFC) + 7 == 8 refreshes (tRFC*8) + See the description of MDREF[REFR] in the reference manual for + details. endmenu diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.c b/board/nxp/mx6sabreauto/mx6sabreauto.c index 8ca57e0b2ac..aef8bc0ad90 100644 --- a/board/nxp/mx6sabreauto/mx6sabreauto.c +++ b/board/nxp/mx6sabreauto/mx6sabreauto.c @@ -465,6 +465,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -488,6 +489,7 @@ int power_init_board(void) return pfuze_mode_init(dev, APS_PFM); } +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sabresd/mx6sabresd.c b/board/nxp/mx6sabresd/mx6sabresd.c index dff3a9c33bf..9404535104c 100644 --- a/board/nxp/mx6sabresd/mx6sabresd.c +++ b/board/nxp/mx6sabresd/mx6sabresd.c @@ -437,6 +437,7 @@ int board_init(void) return 0; } +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -468,6 +469,7 @@ int power_init_board(void) return 0; } +#endif #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index ac91da3f4f6..036deb464b5 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,16 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ PAD_CTL_SRE_FAST) @@ -55,48 +45,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); - - ret = fecmxc_initialize_multi(bis, 1, - CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); - - return ret; -} - int board_phy_config(struct phy_device *phydev) { /* diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c index e3353feec68..cab0892affc 100644 --- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c +++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c @@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = { static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - - /* ENET PHY Power */ - MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* AR8031 PHY Reset */ - MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg, ret; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); - - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); - - return cpu_eth_init(bis); -} - int power_init_board(void) { struct udevice *dev; diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile index ebd0982b5db..5512458832d 100644 --- a/board/nxp/p2041rdb/Makefile +++ b/board/nxp/p2041rdb/Makefile @@ -7,4 +7,3 @@ obj-y += p2041rdb.o obj-y += cpld.o obj-y += ddr.o -obj-y += eth.o diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README deleted file mode 100644 index ae770277372..00000000000 --- a/board/nxp/p2041rdb/README +++ /dev/null @@ -1,138 +0,0 @@ -Overview -========= -The P2041 Processor combines four Power Architecture processor cores -with high-performance datapath acceleration architecture(DPAA), CoreNet -fabric infrastructure, as well as network and peripheral bus interfaces -required for networking, telecom/datacom, wireless infrastructure, and -military/aerospace applications. - -P2041RDB board is a quad core platform supporting the P2041 processor -of QorIQ DPAA series. - -Boot from NOR flash -=================== -1. Build image - make P2041RDB_config - make all - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase eff00000 eff3ffff - => cp.b 1000000 eff00000 2000 - -5. Change DIP-switch - SW1[1-5] = 10110 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SDCard -=================== -1. Build image - make P2041RDB_SDCARD_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SDCard which contains RCW and U-Boot image. - -3. Program the PBL image to SDCard - => tftp 1000000 pbl_sd.bin - => mmcinfo - => mmc write 1000000 8 672 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => mmc write 1000000 690 10 - -5. Change DIP-switch - SW1[1-5] = 01100 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SPI flash -=================== -1. Build image - make P2041RDB_SPIFLASH_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SPI flash which contains RCW and U-Boot image. - -3. Program the PBL image to SPI flash - => tftp 1000000 pbl_spi.bin - => spi probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => sf erase 110000 10000 - => sf write 1000000 110000 $filesize - -5. Change DIP-switch - SW1[1-5] = 10100 - Note: 1 stands for 'on', 0 stands for 'off' - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p2041rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -CPLD command -============ -The CPLD is used to control the power sequence and some serdes lane -mux function. - -cpld reset - hard reset to default bank -cpld reset altbank - reset to alternate bank -cpld lane_mux <lane> <mux_value> - set multiplexed lane pin - lane 6: 0 -> slot1 (Default) - 1 -> SGMII - lane a: 0 -> slot2 (Default) - 1 -> AURORA - lane c: 0 -> slot2 (Default) - 1 -> SATA0 - lane d: 0 -> slot2 (Default) - 1 -> SATA1 - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb - -Or use the following command: - {linux-2.6}/make p2041rdb.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p2041rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst new file mode 100644 index 00000000000..8b8214adc57 --- /dev/null +++ b/board/nxp/p2041rdb/README.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0 + +P2041-RDB Board Overview +======================== + +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== + +1. Build image:: + + make P2041RDB_config + make all + +2. Program image:: + + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +3. Program RCW:: + + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => protect off all + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 + +5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +================ + +1. Build image:: + + make P2041RDB_SDCARD_config + make all + +2. Program the PBL image to SDCard:: + + => tftp 1000000 u-boot.pbl + => mmc info + => mmc write 1000000 8 672 + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => mmc write 1000000 690 10 + +4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== + +1. Build image:: + + make P2041RDB_SPIFLASH_config + make all + +2. Program the PBL image to SPI flash:: + + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf update $fileaddr 0 $filesize + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => sf update $fileaddr 110000 $filesize + +4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off' + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- + +Device tree support is available for p2041rdb for below mentioned boot, + +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, + +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +CPLD command +============ + +The CPLD is used to control the power sequence and some serdes lane +mux function:: + + cpld reset - hard reset to default bank + cpld reset altbank - reset to alternate bank + cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this:: + + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command:: + + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory:: + + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= + +Place a linux uImage in the TFTP disk area:: + + => tftp 1000000 uImage + => tftp 2000000 rootfs.ext2.gz.uboot + => tftp 3000000 p2041rdb.dtb + => bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c deleted file mode 100644 index 65850866777..00000000000 --- a/board/nxp/p2041rdb/eth.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu <[email protected]> - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs - * are provided by the three on-board PHY or by the standard Freescale - * four-port SGMII riser card. We need to change the phy-handle in the - * kernel dts file to point to the correct PHY according to serdes mux - * and serdes protocol selection. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> - -#include "cpld.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 -}; - -static int riser_phy_addr[] = { - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* - * Initialize the lane_to_slot[] array. - * - * On the P2040RDB board the mapping is controlled by CPLD register. - */ -static void initialize_lane_to_slot(void) -{ - u8 mux = CPLD_READ(serdes_mux); - - lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; - lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; - lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; - lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - int lane; - u8 slot; - - switch (intf) { - /* The RGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - break; - /* The SGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } else { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* XAUI */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - default: - break; - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* - * Program the three on-board SGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(i, riser_phy_addr[i]); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CFG_SYS_FM1_DTSEC5_PHY_ADDR : - CFG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - break; - } - - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(FM1_10GEC1, - CFG_SYS_FM1_10GEC1_PHY_ADDR); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg new file mode 100644 index 00000000000..f22f3335e73 --- /dev/null +++ b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 68000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000 diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg index 8df19dd3fe4..8df19dd3fe4 100644 --- a/board/nxp/p2041rdb/rcw_p2041rdb.cfg +++ b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile index b0f27c47191..2a360227418 100644 --- a/board/nxp/t102xrdb/Makefile +++ b/board/nxp/t102xrdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_TARGET_T1024RDB) += cpld.o -obj-y += eth_t102xrdb.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c deleted file mode 100644 index 7185a0abd52..00000000000 --- a/board/nxp/t102xrdb/eth_t102xrdb.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { -#ifdef CONFIG_TARGET_T1024RDB - case 0x95: - /* set the on-board RGMII2 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - - /* set 10GBase-R with Aquantia AQR105 PHY */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - break; -#endif - case 0x6a: - case 0x6b: - case 0x77: - case 0x135: - /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_TARGET_T1023RDB - /* set the on-board 1G SGMII RTL8211F PHY */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); -#endif - break; - default: - printf("SerDes protocol 0x%x is not supported on T102xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_TARGET_T1023RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_TARGET_T1024RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); -#endif - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ -#if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && - (port == FM1_DTSEC3)) { - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); - } -#endif -} - -void fdt_fixup_board_enet(void *fdt) -{ -} diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c index 0a29e27b42c..02223497dd3 100644 --- a/board/nxp/t102xrdb/t102xrdb.c +++ b/board/nxp/t102xrdb/t102xrdb.c @@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif #ifdef CONFIG_TARGET_T1023RDB diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h index 33df0f24df8..71e2cfea22e 100644 --- a/board/nxp/t102xrdb/t102xrdb.h +++ b/board/nxp/t102xrdb/t102xrdb.h @@ -6,7 +6,6 @@ #ifndef __T1024_RDB_H__ #define __T1024_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #ifdef CONFIG_TARGET_T1023RDB static u32 t1023rdb_ctrl(u32 ctrl_type); diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile index 9bca1a1fbcc..cee574aabb9 100644 --- a/board/nxp/t104xrdb/Makefile +++ b/board/nxp/t104xrdb/Makefile @@ -7,7 +7,6 @@ obj-y += spl.o else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c deleted file mode 100644 index c35ec368a45..00000000000 --- a/board/nxp/t104xrdb/eth.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <asm/immap_85xx.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> -#include <vsc9953.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; - int phy_addr = 0; - - printf("Initializing Fman\n"); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* - * Program on board RGMII, SGMII PHY addresses. - */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_TARGET_T1042D4RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 - * & DTSEC3 - */ - if (FM1_DTSEC1 == i) - phy_addr = CFG_SYS_SGMII1_PHY_ADDR; - if (FM1_DTSEC2 == i) - phy_addr = CFG_SYS_SGMII2_PHY_ADDR; - if (FM1_DTSEC3 == i) - phy_addr = CFG_SYS_SGMII3_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; -#endif - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (FM1_DTSEC4 == i) - phy_addr = CFG_SYS_RGMII1_PHY_ADDR; - if (FM1_DTSEC5 == i) - phy_addr = CFG_SYS_RGMII2_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || - fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) - fm_info_set_mdio(i, NULL); - else - fm_info_set_mdio(i, - miiphy_get_dev_by_name( - DEFAULT_FM_MDIO_NAME)); - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h index 678724c7e2b..5825e69cdb4 100644 --- a/board/nxp/t104xrdb/t104xrdb.h +++ b/board/nxp/t104xrdb/t104xrdb.h @@ -6,7 +6,6 @@ #ifndef __T104x_RDB_H__ #define __T104x_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile index eb99d921b4a..4bfd2b50d8f 100644 --- a/board/nxp/t208xqds/Makefile +++ b/board/nxp/t208xqds/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_XPL_BUILD obj-y += spl.o else -obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o endif obj-y += ddr.o diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c deleted file mode 100644 index b55078c8fe1..00000000000 --- a/board/nxp/t208xqds/eth_t208xqds.c +++ /dev/null @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t208xqds_qixis.h" -#include <linux/libfdt.h> - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#if defined(CONFIG_TARGET_T2080QDS) -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 -#endif - -#define PCCR1_SGMIIA_KX_MASK 0x00008000 -#define PCCR1_SGMIIB_KX_MASK 0x00004000 -#define PCCR1_SGMIIC_KX_MASK 0x00002000 -#define PCCR1_SGMIID_KX_MASK 0x00001000 -#define PCCR1_SGMIIE_KX_MASK 0x00000800 -#define PCCR1_SGMIIF_KX_MASK 0x00000400 -#define PCCR1_SGMIIG_KX_MASK 0x00000200 -#define PCCR1_SGMIIH_KX_MASK 0x00000100 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { -#if defined(CONFIG_TARGET_T2080QDS) - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -#endif -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_TARGET_T2080QDS) -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#endif - -static const char *t208xqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t208xqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t208xqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t208xqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 8) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t208xqds_mdio_reset(struct mii_dev *bus) -{ - struct t208xqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t208xqds_mdio_init(char *realbusname, u8 muxval) -{ - struct t208xqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t208xqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t208xqds private data\n"); - free(bus); - return -1; - } - - bus->read = t208xqds_mdio_read; - bus->write = t208xqds_mdio_write; - bus->reset = t208xqds_mdio_reset; - strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; - char buf[32] = "serdes-1,"; - struct fixed_link f_link; - int media_type = 0; - const char *phyconn; - int off; - - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_TARGET_T2080QDS - serdes_corenet_t *srds_regs = - (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); -#endif - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { -#if defined(CONFIG_TARGET_T2080QDS) - case FM1_DTSEC1: - if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx1"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIH_KX_MASK); - break; - } - case FM1_DTSEC2: - if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx2"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIG_KX_MASK); - break; - } - case FM1_DTSEC9: - if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx9"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIE_KX_MASK); - break; - } - case FM1_DTSEC10: - if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx10"); - fdt_status_okay_by_alias(fdt, - "1gkx_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIF_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } - break; - case FM1_DTSEC5: - if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx5"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - strcat(buf, "lane-g,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIC_KX_MASK); - break; - } - case FM1_DTSEC6: - if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx6"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - strcat(buf, "lane-h,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIID_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; -#endif - default: - break; - } - if (media_type) { - /* set property for 1000BASE-KX in dtb */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, "lane-instance", buf); - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* 10GBase-R interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - /* - * Check hwconfig to see what is the media type, there - * are two types, fiber or copper, fix the dtb - * accordingly. - */ - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - /* it's MAC9 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi9"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - /* it's MAC10 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi10"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC3: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { - /* it's MAC1 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi1"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC4: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { - /* it's MAC2 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi2"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - default: - return; - } - - if (!media_type) { - phyconn = fdt_getprop(fdt, offset, - "phy-connection-type", - NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", - port); - } else { - /* fixed-link for 10GBase-R fiber cable */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", - &f_link, sizeof(f_link)); - } - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, - "lane-instance", buf); - } - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{A:H} is configured - * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { -#if defined(CONFIG_TARGET_T2080QDS) - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; -#endif - default: - break; - } -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_TARGET_T2080QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); -#endif - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1b: - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x50: - case 0x51: - case 0x5e: - case 0x5f: - case 0x64: - case 0x65: - /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - case 0x67: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the 10GBase-R MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6a: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x70: - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; -#endif - case 0xf2: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6a) || (srds_s1 == 0x70) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As 10GBase-R is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c index 5e71da0e163..329cf59793f 100644 --- a/board/nxp/t208xqds/t208xqds.c +++ b/board/nxp/t208xqds/t208xqds.c @@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h index 50ebb6f6f98..4086f8c010a 100644 --- a/board/nxp/t208xqds/t208xqds.h +++ b/board/nxp/t208xqds/t208xqds.h @@ -6,7 +6,6 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c index 5223eccb280..c9e415bc446 100644 --- a/board/nxp/t208xrdb/eth_t208xrdb.c +++ b/board/nxp/t208xrdb/eth_t208xrdb.c @@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt) printf("Unable to rename node ethernet-phy@1: %s\n", fdt_strerror(ret)); } - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c index d93edf007ad..d47ec91e7d0 100644 --- a/board/nxp/t208xrdb/t208xrdb.c +++ b/board/nxp/t208xrdb/t208xrdb.c @@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); - fdt_fixup_board_enet(blob); fdt_fixup_board_phy(blob); #endif diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h index 26998898e82..e800270a0e2 100644 --- a/board/nxp/t208xrdb/t208xrdb.h +++ b/board/nxp/t208xrdb/t208xrdb.h @@ -10,7 +10,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); void fdt_fixup_board_phy(void *blob); diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile index 8d94faaba1c..6d9b8df2fc1 100644 --- a/board/nxp/t4rdb/Makefile +++ b/board/nxp/t4rdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c deleted file mode 100644 index e7646365d7d..00000000000 --- a/board/nxp/t4rdb/eth.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Chunhe Lan <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> - -#include "../common/fman.h" -#include "t4rdb.h" - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { - /* SGMII */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); - } else { - puts("Invalid SerDes1 protocol for T4240RDB\n"); - } - - fm_disable_port(FM1_DTSEC5); - fm_disable_port(FM1_DTSEC6); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - -#if (CFG_SYS_NUM_FMAN == 2) - if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && 10GBase-R */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); - } else { - puts("Invalid SerDes2 protocol for T4240RDB\n"); - } - - fm_disable_port(FM2_DTSEC5); - fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } -#endif /* CFG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c index 5cacfd27380..11e2c0f78b7 100644 --- a/board/nxp/t4rdb/t4240rdb.c +++ b/board/nxp/t4rdb/t4240rdb.c @@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h index bb3ce216d7d..9ec190c03cb 100644 --- a/board/nxp/t4rdb/t4rdb.h +++ b/board/nxp/t4rdb/t4rdb.h @@ -14,7 +14,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif |