summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/mediatek/clk-mt8189.c289
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8189.c416
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c105
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.h7
4 files changed, 631 insertions, 186 deletions
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index fec908728c0..9e640059f11 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -287,12 +287,16 @@ enum {
CLK_PAD_CLK32K,
CLK_PAD_CLK26M,
CLK_PAD_ULPOSC,
+ CLK_PAD_CLK13M,
+ CLK_PAD_AUD_ADC_EXT,
};
static ulong ext_clock_rates[] = {
[CLK_PAD_CLK32K] = 32000,
[CLK_PAD_CLK26M] = 26 * MHZ,
[CLK_PAD_ULPOSC] = 260 * MHZ,
+ [CLK_PAD_CLK13M] = 13 * MHZ,
+ [CLK_PAD_AUD_ADC_EXT] = 260 * MHZ,
};
#define MT8189_PLL_FMAX (3800UL * MHZ)
@@ -1637,6 +1641,258 @@ static const struct mtk_gate mminfra_config_clks[] = {
GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17),
};
+static const struct mtk_parent vlp_26m_oscd10_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_vadsp_vowpll_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_VOWPLL),
+};
+
+static const struct mtk_parent vlp_sspm_ulposc_parents[] = {
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_aud_adc_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_VOWPLL),
+ EXT_PARENT(CLK_PAD_AUD_ADC_EXT),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_scp_iic_spi_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_vadsp_uarthub_b_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2),
+};
+
+static const struct mtk_parent vlp_axi_kp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D2),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D2),
+};
+
+static const struct mtk_parent vlp_sspm_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D2),
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+};
+
+static const struct mtk_parent vlp_pwm_vlp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D4),
+ EXT_PARENT(CLK_PAD_CLK32K),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4_D8),
+};
+
+static const struct mtk_parent vlp_pwrap_ulposc_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D7),
+ TOP_PARENT(CLK_TOP_OSC_D8),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D8),
+};
+
+static const struct mtk_parent vlp_vadsp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_OSC_D20),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D2),
+ EXT_PARENT(CLK_PAD_ULPOSC),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4_D2),
+};
+
+static const struct mtk_parent vlp_scp_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D3),
+ TOP_PARENT(CLK_TOP_MAINPLL_D3),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+ APMIXED_PARENT(CLK_APMIXED_APLL1),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+};
+
+static const struct mtk_parent vlp_spmi_p_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_F26M_CK_D2),
+ TOP_PARENT(CLK_TOP_OSC_D8),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_OSC_D7),
+ EXT_PARENT(CLK_PAD_CLK32K),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5_D8),
+};
+
+static const struct mtk_parent vlp_camtg_parents[] = {
+ EXT_PARENT(CLK_PAD_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4),
+ TOP_PARENT(CLK_TOP_OSC_D16),
+ TOP_PARENT(CLK_TOP_OSC_D20),
+ TOP_PARENT(CLK_TOP_OSC_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16),
+ TOP_PARENT(CLK_TOP_TVDPLL1_D16),
+ TOP_PARENT(CLK_TOP_F26M_CK_D2),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16),
+ TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32),
+};
+
+static const struct mtk_composite vlp_ck_muxes[] = {
+ /* VLP_CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, vlp_scp_parents,
+ 0x008, 0x00c, 0x010, 0, 4, 7, 0x04, 0),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_pwrap_ulposc_parents,
+ 0x008, 0x00c, 0x010, 8, 3, 0x04, 1),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_spmi_p_parents,
+ 0x008, 0x00c, 0x010, 16, 4, 0x04, 2),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_26m_oscd10_parents,
+ 0x008, 0x00c, 0x010, 24, 1, 0x04, 3),
+ /* VLP_CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_pwm_vlp_parents,
+ 0x014, 0x018, 0x01c, 0, 3, 0x04, 4),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_axi_kp_parents,
+ 0x014, 0x018, 0x01c, 8, 3, 0x04, 5),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_26m_oscd10_parents,
+ 0x014, 0x018, 0x01c, 16, 1, 0x04, 6),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, vlp_sspm_parents,
+ 0x014, 0x018, 0x01c, 24, 3, 0x04, 7),
+ /* VLP_CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_26m_oscd10_parents,
+ 0x020, 0x024, 0x028, 0, 1, 0x04, 8),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, vlp_26m_oscd10_parents,
+ 0x020, 0x024, 0x028, 8, 1, 0x04, 9),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_scp_iic_spi_parents,
+ 0x020, 0x024, 0x028, 16, 2, 0x04, 10),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_scp_iic_spi_parents,
+ 0x020, 0x024, 0x028, 24, 2, 0x04, 11),
+ /* VLP_CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL,
+ vlp_scp_iic_spi_parents,
+ 0x02c, 0x030, 0x034, 0, 2, 0x04, 12),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
+ vlp_scp_iic_spi_parents,
+ 0x02c, 0x030, 0x034, 8, 2, 0x04, 13),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_sspm_ulposc_parents,
+ 0x02c, 0x030, 0x034, 16, 2, 0x04, 14),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_26m_oscd10_parents,
+ 0x02c, 0x030, 0x034, 24, 1, 0x04, 15),
+ /* VLP_CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, vlp_vadsp_parents,
+ 0x038, 0x03c, 0x040, 0, 3, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL,
+ vlp_vadsp_vowpll_parents,
+ 0x038, 0x03c, 0x040, 8, 1, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL,
+ vlp_vadsp_uarthub_b_parents,
+ 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_camtg_parents,
+ 0x038, 0x03c, 0x040, 24, 4, 31, 0x04, 19),
+ /* VLP_CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_camtg_parents,
+ 0x044, 0x048, 0x04c, 0, 4, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_camtg_parents,
+ 0x044, 0x048, 0x04c, 8, 4, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_aud_adc_parents,
+ 0x044, 0x048, 0x04c, 16, 2, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_axi_kp_parents,
+ 0x044, 0x048, 0x04c, 24, 3, 31, 0x04, 23),
+};
+
+static const struct mtk_gate_regs vlp_ck_gate_regs = {
+ .set_ofs = 0x1f4,
+ .clr_ofs = 0x1f8,
+ .sta_ofs = 0x1f0,
+};
+
+#define GATE_VLP_CK(id, parent, shift, flags) \
+ GATE_FLAGS(id, parent, &vlp_ck_gate_regs, shift, flags | CLK_GATE_NO_SETCLR_INV)
+
+#define GATE_VLP_CK_EXT(id, parent, shift) \
+ GATE_VLP_CK(id, parent, shift, CLK_PARENT_EXT)
+
+#define GATE_VLP_CK_TOP(id, parent, shift) \
+ GATE_VLP_CK(id, parent, shift, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_gate vlp_ck_gates[] = {
+ GATE_VLP_CK_EXT(CLK_VLP_CK_VADSYS_VLP_26M_EN, CLK_PAD_CLK26M, 1),
+ GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_13M_EN, CLK_PAD_CLK13M, 4),
+ GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_26M_EN, CLK_PAD_CLK26M, 5),
+ GATE_VLP_CK_TOP(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, CLK_TOP_OSC_D10, 11),
+};
+
+static const struct mtk_gate_regs vlpcfg_ao_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+/*
+ * REVISIT: this is currently the only clock tree using the infrasys ops so we
+ * are using it instead of introducing a new parent in the core code. Instead,
+ * we should eventually rework the core code to do a better job of supporting
+ * arbitrary parent trees.
+ */
+#define CLK_PARENT_VLP_CK CLK_PARENT_INFRASYS
+
+#define GATE_VLPCFG_AO(id, parent, shift, flags) \
+ GATE_FLAGS(id, parent, &vlpcfg_ao_regs, shift, flags | CLK_GATE_NO_SETCLR_INV)
+
+#define GATE_VLPCFG_AO_EXT(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_EXT)
+
+#define GATE_VLPCFG_AO_TOP(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_TOPCKGEN)
+
+#define GATE_VLPCFG_AO_VLP(id, parent, shift) \
+ GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_VLP_CK)
+
+static const struct mtk_gate vlpcfg_ao_clks[] = {
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 12),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 11),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 10),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DVFSRC, CLK_VLP_CK_DVFSRC_SEL, 9),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PWM_VLP, CLK_VLP_CK_PWM_VLP_SEL, 8),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SRCK, CLK_VLP_CK_SRCK_SEL, 7),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_F26M, CLK_VLP_CK_SSPM_F26M_SEL, 4),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SSPM_F32K, CLK_PAD_CLK32K, 3),
+ GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_ULPOSC, CLK_VLP_CK_SSPM_ULPOSC_SEL, 2),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_32K_COM, CLK_PAD_CLK32K, 1),
+ GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_26M_COM, CLK_PAD_CLK26M, 0),
+};
+
static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {
.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clock_rates,
@@ -1659,6 +1915,17 @@ static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {
.num_gates = ARRAY_SIZE(top_gates),
};
+static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+ .muxes_offs = CLK_VLP_CK_SCP_SEL,
+ .gates_offs = CLK_VLP_CK_VADSYS_VLP_26M_EN,
+ .muxes = vlp_ck_muxes,
+ .gates = vlp_ck_gates,
+ .num_muxes = ARRAY_SIZE(vlp_ck_muxes),
+ .num_gates = ARRAY_SIZE(vlp_ck_gates),
+};
+
static const struct udevice_id mt8189_apmixed[] = {
{ .compatible = "mediatek,mt8189-apmixedsys", },
{ }
@@ -1669,6 +1936,11 @@ static const struct udevice_id mt8189_topckgen_compat[] = {
{ }
};
+static const struct udevice_id mt8189_vlpckgen[] = {
+ { .compatible = "mediatek,mt8189-vlpckgen", },
+ { }
+};
+
struct mt8189_gate_clk_data {
const struct mtk_gate *gates;
int num_gates;
@@ -1683,12 +1955,14 @@ GATE_CLK_DATA(perao_clks);
GATE_CLK_DATA(imp_clks);
GATE_CLK_DATA(mm_clks);
GATE_CLK_DATA(mminfra_config_clks);
+GATE_CLK_DATA(vlpcfg_ao_clks);
static const struct udevice_id of_match_mt8189_clk_gate[] = {
{ .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data },
{ .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data },
{ .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data },
{ .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data },
+ { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data },
{ }
};
@@ -1702,6 +1976,11 @@ static int mt8189_topckgen_probe(struct udevice *dev)
return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree);
}
+static int mt8189_infrasys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_infrasys_init(dev, &mt8189_vlpckgen_clk_tree);
+}
+
static int mt8189_clk_gate_probe(struct udevice *dev)
{
struct mt8189_gate_clk_data *data;
@@ -1733,6 +2012,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
+ .name = "mt8189-vlpckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8189_vlpckgen,
+ .probe = mt8189_infrasys_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_infrasys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
U_BOOT_DRIVER(mtk_clk_gate) = {
.name = "mt8189-gate-clk",
.id = UCLASS_CLK,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
index a64440d8bb3..b01533ed80b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
@@ -1015,6 +1015,29 @@ static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = {
PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3),
};
+static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = {
+ PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00B0, 0, 3), /* SCP_SCL0 */
+ PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00B0, 6, 3), /* SCP_SDA0 */
+ PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00B0, 3, 3), /* SCP_SCL1 */
+ PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00B0, 9, 3), /* SCP_SDA1 */
+ PIN_FIELD_BASE(55, IO_BASE_LM, 0x00B0, 0, 3), /* SCL2 */
+ PIN_FIELD_BASE(56, IO_BASE_LM, 0x00B0, 3, 3), /* SDA2 */
+ PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00B0, 0, 3), /* SCL3 */
+ PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00B0, 12, 3), /* SDA3 */
+ PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00B0, 3, 3), /* SCL4 */
+ PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00B0, 15, 3), /* SDA4 */
+ PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00B0, 6, 3), /* SCL5 */
+ PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00B0, 18, 3), /* SDA5 */
+ PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00B0, 9, 3), /* SCL6 */
+ PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00B0, 21, 3), /* SDA6 */
+ PIN_FIELD_BASE(65, IO_BASE_RT, 0x00E0, 0, 3), /* SCL7 */
+ PIN_FIELD_BASE(66, IO_BASE_RT, 0x00E0, 6, 3), /* SDA7 */
+ PIN_FIELD_BASE(67, IO_BASE_RT, 0x00E0, 3, 3), /* SCL8 */
+ PIN_FIELD_BASE(68, IO_BASE_RT, 0x00E0, 9, 3), /* SDA8 */
+ PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0110, 0, 3), /* SPMI_P_SCL */
+ PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0110, 3, 3), /* SPMI_P_SDA */
+};
+
static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range),
@@ -1028,6 +1051,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range),
+ [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range),
};
static const char * const mt8189_pinctrl_register_base_names[] = {
@@ -1048,198 +1072,222 @@ static const char * const mt8189_pinctrl_register_base_names[] = {
[IO_BASE_EINT4] = "eint4",
};
+#define MT8189_TYPE0_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
+
+#define MT8189_TYPE1_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
+
+#define MT8189_TYPE2_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2)
+
static const struct mtk_pin_desc mt8189_pins[] = {
- MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0),
+ MT8189_TYPE0_PIN(0, "GPIO00"),
+ MT8189_TYPE0_PIN(1, "GPIO01"),
+ MT8189_TYPE0_PIN(2, "GPIO02"),
+ MT8189_TYPE0_PIN(3, "GPIO03"),
+ MT8189_TYPE0_PIN(4, "GPIO04"),
+ MT8189_TYPE0_PIN(5, "GPIO05"),
+ MT8189_TYPE0_PIN(6, "GPIO06"),
+ MT8189_TYPE0_PIN(7, "GPIO07"),
+ MT8189_TYPE0_PIN(8, "GPIO08"),
+ MT8189_TYPE0_PIN(9, "GPIO09"),
+ MT8189_TYPE0_PIN(10, "GPIO10"),
+ MT8189_TYPE0_PIN(11, "GPIO11"),
+ MT8189_TYPE0_PIN(12, "GPIO12"),
+ MT8189_TYPE0_PIN(13, "GPIO13"),
+ MT8189_TYPE0_PIN(14, "GPIO14"),
+ MT8189_TYPE0_PIN(15, "GPIO15"),
+ MT8189_TYPE0_PIN(16, "GPIO16"),
+ MT8189_TYPE0_PIN(17, "GPIO17"),
+ MT8189_TYPE0_PIN(18, "GPIO18"),
+ MT8189_TYPE0_PIN(19, "GPIO19"),
+ MT8189_TYPE0_PIN(20, "GPIO20"),
+ MT8189_TYPE0_PIN(21, "GPIO21"),
+ MT8189_TYPE0_PIN(22, "GPIO22"),
+ MT8189_TYPE0_PIN(23, "GPIO23"),
+ MT8189_TYPE0_PIN(24, "GPIO24"),
+ MT8189_TYPE0_PIN(25, "GPIO25"),
+ MT8189_TYPE0_PIN(26, "GPIO26"),
+ MT8189_TYPE0_PIN(27, "GPIO27"),
+ MT8189_TYPE0_PIN(28, "GPIO28"),
+ MT8189_TYPE0_PIN(29, "GPIO29"),
+ MT8189_TYPE0_PIN(30, "GPIO30"),
+ MT8189_TYPE0_PIN(31, "GPIO31"),
+ MT8189_TYPE0_PIN(32, "GPIO32"),
+ MT8189_TYPE0_PIN(33, "GPIO33"),
+ MT8189_TYPE0_PIN(34, "GPIO34"),
+ MT8189_TYPE0_PIN(35, "GPIO35"),
+ MT8189_TYPE0_PIN(36, "GPIO36"),
+ MT8189_TYPE0_PIN(37, "GPIO37"),
+ MT8189_TYPE0_PIN(38, "GPIO38"),
+ MT8189_TYPE0_PIN(39, "GPIO39"),
+ MT8189_TYPE0_PIN(40, "GPIO40"),
+ MT8189_TYPE0_PIN(41, "GPIO41"),
+ MT8189_TYPE0_PIN(42, "GPIO42"),
+ MT8189_TYPE0_PIN(43, "GPIO43"),
+ MT8189_TYPE1_PIN(44, "GPIO44"),
+ MT8189_TYPE1_PIN(45, "GPIO45"),
+ MT8189_TYPE1_PIN(46, "GPIO46"),
+ MT8189_TYPE1_PIN(47, "GPIO47"),
+ MT8189_TYPE0_PIN(48, "GPIO48"),
+ MT8189_TYPE0_PIN(49, "GPIO49"),
+ MT8189_TYPE0_PIN(50, "GPIO50"),
+ MT8189_TYPE2_PIN(51, "GPIO51"),
+ MT8189_TYPE2_PIN(52, "GPIO52"),
+ MT8189_TYPE2_PIN(53, "GPIO53"),
+ MT8189_TYPE2_PIN(54, "GPIO54"),
+ MT8189_TYPE2_PIN(55, "GPIO55"),
+ MT8189_TYPE2_PIN(56, "GPIO56"),
+ MT8189_TYPE2_PIN(57, "GPIO57"),
+ MT8189_TYPE2_PIN(58, "GPIO58"),
+ MT8189_TYPE2_PIN(59, "GPIO59"),
+ MT8189_TYPE2_PIN(60, "GPIO60"),
+ MT8189_TYPE2_PIN(61, "GPIO61"),
+ MT8189_TYPE2_PIN(62, "GPIO62"),
+ MT8189_TYPE2_PIN(63, "GPIO63"),
+ MT8189_TYPE2_PIN(64, "GPIO64"),
+ MT8189_TYPE2_PIN(65, "GPIO65"),
+ MT8189_TYPE2_PIN(66, "GPIO66"),
+ MT8189_TYPE2_PIN(67, "GPIO67"),
+ MT8189_TYPE2_PIN(68, "GPIO68"),
+ MT8189_TYPE0_PIN(69, "GPIO69"),
+ MT8189_TYPE0_PIN(70, "GPIO70"),
+ MT8189_TYPE0_PIN(71, "GPIO71"),
+ MT8189_TYPE0_PIN(72, "GPIO72"),
+ MT8189_TYPE0_PIN(73, "GPIO73"),
+ MT8189_TYPE0_PIN(74, "GPIO74"),
+ MT8189_TYPE0_PIN(75, "GPIO75"),
+ MT8189_TYPE0_PIN(76, "GPIO76"),
+ MT8189_TYPE0_PIN(77, "GPIO77"),
+ MT8189_TYPE0_PIN(78, "GPIO78"),
+ MT8189_TYPE0_PIN(79, "GPIO79"),
+ MT8189_TYPE0_PIN(80, "GPIO80"),
+ MT8189_TYPE0_PIN(81, "GPIO81"),
+ MT8189_TYPE0_PIN(82, "GPIO82"),
+ MT8189_TYPE0_PIN(83, "GPIO83"),
+ MT8189_TYPE0_PIN(84, "GPIO84"),
+ MT8189_TYPE0_PIN(85, "GPIO85"),
+ MT8189_TYPE0_PIN(86, "GPIO86"),
+ MT8189_TYPE0_PIN(87, "GPIO87"),
+ MT8189_TYPE0_PIN(88, "GPIO88"),
+ MT8189_TYPE0_PIN(89, "GPIO89"),
+ MT8189_TYPE0_PIN(90, "GPIO90"),
+ MT8189_TYPE0_PIN(91, "GPIO91"),
+ MT8189_TYPE0_PIN(92, "GPIO92"),
+ MT8189_TYPE0_PIN(93, "GPIO93"),
+ MT8189_TYPE0_PIN(94, "GPIO94"),
+ MT8189_TYPE0_PIN(95, "GPIO95"),
+ MT8189_TYPE0_PIN(96, "GPIO96"),
+ MT8189_TYPE0_PIN(97, "GPIO97"),
+ MT8189_TYPE0_PIN(98, "GPIO98"),
+ MT8189_TYPE0_PIN(99, "GPIO99"),
+ MT8189_TYPE0_PIN(100, "GPIO100"),
+ MT8189_TYPE0_PIN(101, "GPIO101"),
+ MT8189_TYPE0_PIN(102, "GPIO102"),
+ MT8189_TYPE0_PIN(103, "GPIO103"),
+ MT8189_TYPE0_PIN(104, "GPIO104"),
+ MT8189_TYPE0_PIN(105, "GPIO105"),
+ MT8189_TYPE0_PIN(106, "GPIO106"),
+ MT8189_TYPE0_PIN(107, "GPIO107"),
+ MT8189_TYPE0_PIN(108, "GPIO108"),
+ MT8189_TYPE0_PIN(109, "GPIO109"),
+ MT8189_TYPE0_PIN(110, "GPIO110"),
+ MT8189_TYPE0_PIN(111, "GPIO111"),
+ MT8189_TYPE0_PIN(112, "GPIO112"),
+ MT8189_TYPE0_PIN(113, "GPIO113"),
+ MT8189_TYPE0_PIN(114, "GPIO114"),
+ MT8189_TYPE0_PIN(115, "GPIO115"),
+ MT8189_TYPE0_PIN(116, "GPIO116"),
+ MT8189_TYPE0_PIN(117, "GPIO117"),
+ MT8189_TYPE0_PIN(118, "GPIO118"),
+ MT8189_TYPE0_PIN(119, "GPIO119"),
+ MT8189_TYPE0_PIN(120, "GPIO120"),
+ MT8189_TYPE0_PIN(121, "GPIO121"),
+ MT8189_TYPE0_PIN(122, "GPIO122"),
+ MT8189_TYPE0_PIN(123, "GPIO123"),
+ MT8189_TYPE0_PIN(124, "GPIO124"),
+ MT8189_TYPE0_PIN(125, "GPIO125"),
+ MT8189_TYPE0_PIN(126, "GPIO126"),
+ MT8189_TYPE0_PIN(127, "GPIO127"),
+ MT8189_TYPE0_PIN(128, "GPIO128"),
+ MT8189_TYPE0_PIN(129, "GPIO129"),
+ MT8189_TYPE0_PIN(130, "GPIO130"),
+ MT8189_TYPE0_PIN(131, "GPIO131"),
+ MT8189_TYPE0_PIN(132, "GPIO132"),
+ MT8189_TYPE0_PIN(133, "GPIO133"),
+ MT8189_TYPE0_PIN(134, "GPIO134"),
+ MT8189_TYPE0_PIN(135, "GPIO135"),
+ MT8189_TYPE0_PIN(136, "GPIO136"),
+ MT8189_TYPE0_PIN(137, "GPIO137"),
+ MT8189_TYPE0_PIN(138, "GPIO138"),
+ MT8189_TYPE0_PIN(139, "GPIO139"),
+ MT8189_TYPE0_PIN(140, "GPIO140"),
+ MT8189_TYPE0_PIN(141, "GPIO141"),
+ MT8189_TYPE0_PIN(142, "GPIO142"),
+ MT8189_TYPE0_PIN(143, "GPIO143"),
+ MT8189_TYPE0_PIN(144, "GPIO144"),
+ MT8189_TYPE0_PIN(145, "GPIO145"),
+ MT8189_TYPE0_PIN(146, "GPIO146"),
+ MT8189_TYPE0_PIN(147, "GPIO147"),
+ MT8189_TYPE0_PIN(148, "GPIO148"),
+ MT8189_TYPE0_PIN(149, "GPIO149"),
+ MT8189_TYPE0_PIN(150, "GPIO150"),
+ MT8189_TYPE0_PIN(151, "GPIO151"),
+ MT8189_TYPE0_PIN(152, "GPIO152"),
+ MT8189_TYPE0_PIN(153, "GPIO153"),
+ MT8189_TYPE0_PIN(154, "GPIO154"),
+ MT8189_TYPE0_PIN(155, "GPIO155"),
+ MT8189_TYPE1_PIN(156, "GPIO156"),
+ MT8189_TYPE1_PIN(157, "GPIO157"),
+ MT8189_TYPE1_PIN(158, "GPIO158"),
+ MT8189_TYPE1_PIN(159, "GPIO159"),
+ MT8189_TYPE1_PIN(160, "GPIO160"),
+ MT8189_TYPE1_PIN(161, "GPIO161"),
+ MT8189_TYPE1_PIN(162, "GPIO162"),
+ MT8189_TYPE1_PIN(163, "GPIO163"),
+ MT8189_TYPE1_PIN(164, "GPIO164"),
+ MT8189_TYPE1_PIN(165, "GPIO165"),
+ MT8189_TYPE1_PIN(166, "GPIO166"),
+ MT8189_TYPE1_PIN(167, "GPIO167"),
+ MT8189_TYPE1_PIN(168, "GPIO168"),
+ MT8189_TYPE1_PIN(169, "GPIO169"),
+ MT8189_TYPE1_PIN(170, "GPIO170"),
+ MT8189_TYPE1_PIN(171, "GPIO171"),
+ MT8189_TYPE1_PIN(172, "GPIO172"),
+ MT8189_TYPE1_PIN(173, "GPIO173"),
+ MT8189_TYPE1_PIN(174, "GPIO174"),
+ MT8189_TYPE1_PIN(175, "GPIO175"),
+ MT8189_TYPE1_PIN(176, "GPIO176"),
+ MT8189_TYPE1_PIN(177, "GPIO177"),
+ MT8189_TYPE1_PIN(178, "GPIO178"),
+ MT8189_TYPE1_PIN(179, "GPIO179"),
+ MT8189_TYPE2_PIN(180, "GPIO180"),
+ MT8189_TYPE2_PIN(181, "GPIO181"),
+ MT8189_TYPE0_PIN(182, "GPIO182"),
};
static const struct mtk_io_type_desc mt8189_io_type_desc[] = {
[IO_TYPE_GRP0] = {
.name = "mt8189",
- .bias_set = mtk_pinconf_bias_set_v1,
+ .bias_set = mtk_pinconf_bias_set_pu_pd,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ .get_pinconf = mtk_pinconf_get_pu_pd,
+ },
+ [IO_TYPE_GRP1] = {
+ .name = "MSDC",
+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ .get_pinconf = mtk_pinconf_get_pupd_r1_r0,
+ },
+ [IO_TYPE_GRP2] = {
+ .name = "I2C",
+ .bias_set = mtk_pinconf_bias_set_pu_pd_rsel,
.drive_set = mtk_pinconf_drive_set_v1,
.input_enable = mtk_pinconf_input_enable_v1,
+ .get_pinconf = mtk_pinconf_get_pu_pd_rsel,
},
};
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index d152e216634..cfffbaeef84 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -237,9 +237,39 @@ static int mtk_get_pin_io_type(struct udevice *dev, int pin,
io_type->bias_set = priv->soc->io_type[io_n].bias_set;
io_type->drive_set = priv->soc->io_type[io_n].drive_set;
io_type->input_enable = priv->soc->io_type[io_n].input_enable;
+ io_type->get_pinconf = priv->soc->io_type[io_n].get_pinconf;
return 0;
}
+
+static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size)
+{
+ struct mtk_io_type_desc io_type;
+ int err, pos;
+
+ /* If we fail to get the type, then we just don't add any more info. */
+ if (mtk_get_pin_io_type(dev, pin, &io_type))
+ return 0;
+
+ pos = snprintf(buf, size, " (%s)", io_type.name);
+ if (pos >= size)
+ return pos;
+
+ if (io_type.get_pinconf) {
+ err = io_type.get_pinconf(dev, pin, buf + pos, size - pos);
+ if (err < 0)
+ return err;
+
+ pos += err;
+ }
+
+ return pos;
+}
+#else
+static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size)
+{
+ return 0;
+}
#endif
static int mtk_get_groups_count(struct udevice *dev)
@@ -270,12 +300,20 @@ static int mtk_get_pins_count(struct udevice *dev)
static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector,
char *buf, int size)
{
- int val, err;
+ int val, err, pos;
+
err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val);
if (err)
return err;
- snprintf(buf, size, "Aux Func.%d", val);
+ pos = snprintf(buf, size, "Aux Func.%d", val);
+ if (pos >= size)
+ return 0;
+
+ err = mtk_pinconf_get(dev, selector, buf + pos, size - pos);
+ if (err < 0)
+ return err;
+
return 0;
}
@@ -450,6 +488,20 @@ int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
return 0;
}
+int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val)
+{
+ int err;
+
+ /* val is expected to be one of MTK_PULL_SET_RSEL_XXX */
+
+ err = mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val);
+ if (err)
+ return err;
+
+ return mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_RSEL, val & 0x7);
+}
+
int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val)
{
int err;
@@ -656,6 +708,55 @@ static int mtk_pinconf_group_set(struct udevice *dev,
return 0;
}
+
+int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size)
+{
+ int err, pu, pd;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PU, &pu);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PD, &pd);
+ if (err)
+ return err;
+
+ return snprintf(buf, size, " PU:%d PD:%d", pu, pd);
+}
+
+int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size)
+{
+ int err, r0, r1, pupd;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PUPD, &pupd);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R1, &r1);
+ if (err)
+ return err;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R0, &r0);
+ if (err)
+ return err;
+
+ return snprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0);
+}
+
+int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size)
+{
+ int pos, err, rsel;
+
+ pos = mtk_pinconf_get_pu_pd(dev, pin, buf, size);
+ if (pos < 0 || pos >= size)
+ return pos;
+
+ err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_RSEL, &rsel);
+ if (err)
+ return err;
+
+ return pos + snprintf(buf + pos, size - pos, " RSEL:%d", rsel);
+}
#endif
static int mtk_pinctrl_pinmux_property_set(struct udevice *dev, u32 pinmux_group)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 58f13613633..bd17964090a 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -67,6 +67,7 @@ enum {
PINCTRL_PIN_REG_PUPD,
PINCTRL_PIN_REG_R0,
PINCTRL_PIN_REG_R1,
+ PINCTRL_PIN_REG_RSEL,
PINCTRL_PIN_REG_MAX,
};
@@ -203,6 +204,7 @@ struct mtk_io_type_desc {
bool pullup, u32 val);
int (*drive_set)(struct udevice *dev, u32 pin, u32 arg);
int (*input_enable)(struct udevice *dev, u32 pin, u32 arg);
+ int (*get_pinconf)(struct udevice *dev, u32 pin, char *buf, size_t size);
#endif
};
@@ -253,6 +255,8 @@ int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
bool disable, bool pullup, u32 val);
int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
bool pullup, u32 val);
+int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
bool pullup, u32 val);
int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
@@ -260,6 +264,9 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg);
int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg);
int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg);
+int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size);
+int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size);
+int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size);
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-11 17:46:14 +0000