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2026-03-16phy: cadence: Add config to enable Cadence Torrent PHY at SPL stageHrushikesh Salunke
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence Torrent PHY driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]>
2026-03-16arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe bootHrushikesh Salunke
To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled and configured at the R5 stage. Add the required clk-data and dev-data for SERDES0 and PCIE1. Signed-off-by: Hrushikesh Salunke <[email protected]> Signed-off-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Udit Kumar <[email protected]>
2026-03-16Merge tag 'efi-2026-03-14' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi into next Pull request efi-2026-03-14 CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29512 UEFI: * Require at least 128 KiB of stack space to use EFI sub-system. * Avoid buffer overrun in efi_var_restore(). * Avoid superfluous variable store writes on unchanged data * Implement SPI Flash store for EFI variables. * Add an efidebug ecpt sub-command to display the ECPT table and a unit test for the command. Others: * Add missing include string.h to make exception command build again. * lib: uuid: add EBBR 2.1 conformance profile GUID
2026-03-16Merge tag 'u-boot-dfu-20260316' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu into next u-boot-dfu-20260316 DFU: * Make DFU_WRITE_ALT symbol available outside of DFU * Fix PCI subclass_code warning in spl_dfu Usb Gadget: * Mark udc_disconnect() as static
2026-03-16dfu: Make the DFU_WRITE_ALT symbol available outside of DFUTom Rini
The DFU_WRITE_ALT symbol is used both directly and indirectly (via UPDATE_COMMON) for EFI capsule updates (FIT or raw), but does not depend on DFU itself. Move this symbol outside of "if DFU" to remove a Kconfig dependency problem. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Reviewed-by: Mattijs Korpershoek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mattijs Korpershoek <[email protected]>
2026-03-14cmd/exception: missing include string.hHeinrich Schuchardt
When building qemu_arm64_defconfig with CMD_EXCEPTION a build error occurs: In file included from cmd/arm/exception64.c:87: include/exception.h: In function ‘exception_complete’: include/exception.h:41:23: error: implicit declaration of function ‘strlen’ [-Wimplicit-function-declaration] 41 | len = strlen(argv[1]); | ^~~~~~ Add the missing include. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2026-03-14efi_vars: Implement SPI Flash storeShantur Rathore
Currently U-Boot uses ESP as storage for EFI variables. Devices with SPI Flash are used for storing environment with this commit we allow EFI variables to be stored on SPI Flash. Signed-off-by: Shantur Rathore <[email protected]> Signed-off-by: Michal Simek <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on AML-S905D3-CC Acked-by: Ilias Apalodimas <[email protected]>
2026-03-14efi_loader: avoid superfluous variable store writes on unchanged dataMichal Simek
Every SetVariable() call triggers efi_var_mem_ins() followed by efi_var_to_storage(), even when the variable value is not actually changing. This is unfriendly to flash-backed stores that suffer wear from unnecessary erase/write cycles. Add a change-detection path to efi_var_mem_ins(): when size2 == 0 (i.e. not an append) and the caller passes a non-NULL changep flag, look up the existing variable and compare attributes, length, time and data byte-by-byte. If everything matches, set *changep = false and return EFI_SUCCESS without touching the variable buffer. Both efi_set_variable_int() and efi_set_variable_runtime() now check the flag and skip efi_var_mem_del() / efi_var_to_storage() when nothing changed. Introduce efi_memcmp_runtime() - a runtime-safe byte-by-byte memory comparison helper, following the same pattern as the existing efi_memcpy_runtime(). The standard memcmp() is not available after ExitBootServices() and calling it from Linux will crash. Tested-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]>
2026-03-14efi_loader: avoid buffer overrun in efi_var_restore()Heinrich Schuchardt
The value of buf->length comes from outside U-Boot and may be incorrect. We must avoid to overrun our internal buffer for excessive values. If buf->length is shorter than the variable file header, the variable file is invalid. Reviewed-by: Ilias Apalodimas <[email protected]> Tested-by: Michal Simek <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
2026-03-14test/py: add ECPT testsVincent Stehlé
Add a couple of EFI Conformance Profiles Table (ECPT) tests, which exercise the "efidebug ecpt" command. Signed-off-by: Vincent Stehlé <[email protected]> Cc: Tom Rini <[email protected]> Cc: Heinrich Schuchardt <[email protected]> Cc: Ilias Apalodimas <[email protected]>
2026-03-14cmd: efidebug: add ecpt commandVincent Stehlé
Add an "efidebug ecpt" command, to print the conformance profiles in the ECPT: => efidebug ecpt cce33c35-74ac-4087-bce7-8b29b02eeb27 EFI EBBR 2.1 Conformance Profile Suggested-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Vincent Stehlé <[email protected]> Cc: Ilias Apalodimas <[email protected]> Cc: Tom Rini <[email protected]> Acked-by: Ilias Apalodimas <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]>
2026-03-14efi_loader: export efi_ecpt_guidVincent Stehlé
Export the ECPT GUID, to prepare accessing it from more than one location. The C file containing the GUID is compiled only when CONFIG_EFI_ECPT is set; gate the export accordingly. Signed-off-by: Vincent Stehlé <[email protected]> Cc: Heinrich Schuchardt <[email protected]> Cc: Ilias Apalodimas <[email protected]> Cc: Tom Rini <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]>
2026-03-14lib: uuid: add EBBR 2.1 conformance profile GUIDVincent Stehlé
Add support for printing the EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID as human readable text. This is compiled in only when CONFIG_CMD_EFIDEBUG and CONFIG_EFI_EPCT are set. Suggested-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Vincent Stehlé <[email protected]> Cc: Tom Rini <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]>
2026-03-14efi_loader: require at least 128 KiB of stack spaceHeinrich Schuchardt
The UEFI specification requires at least 128 KiB stack space. Consider this value as a prerequisite for CONFIG_EFI_LOADER. Mention the requirement in the CONFIG_STACK_SPACE description and decribe that the UEFI sub-system uses CONFIG_STACK_SPACE when defining the memory map. Reviewed-by: Ilias Apalodimas <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
2026-03-13rockchip: rk3568: Include all addressable DRAM in memory mapJonas Karlman
Rockchip RK356x supports up to 8 GiB DRAM, however U-Boot only includes the initial 32-bit 0-4 GiB addressable range in its memory map, something that matches gd->ram_top and current expected memory available for use in U-Boot. The vendor DRAM init blobs add following ddr_mem rk atags [1]: 4 GiB: [0x0, 0xf0000000) and [0x1f0000000, 0x200000000) 8 GiB: [0x0, 0x200000000) Add the remaining 64-bit 4-8 GiB addressable range, that already is reported to OS, to the U-Boot memory map to more correctly describe all available and addressable DRAM of RK356x. While at it also add the missing UL suffix to the PCIe address range for consistency. [1] https://gist.github.com/Kwiboo/6d983693c79365b43c330eb3191cbace Acked-by: Quentin Schulz <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2026-03-13Merge patch series "arm: dts: k3-am68-r5-phycore-som: Add PMIC ESM node"Tom Rini
This series from Dominik Haller <[email protected]> adds and enables support for the PMIC ESM node on some phycore-som based platforms. Link: https://lore.kernel.org/r/[email protected]
2026-03-13Merge patch series "k3_*: Add config fragments for inline ECC and BIST"Tom Rini
Neha Malcom Francis <[email protected]> says: Typically we do not enable these configs by default but would still like to have the option to start building them in our default build flow for testing. Also there is the added advantage of users being able to see what is needed in case they choose to enable these features. Link: https://lore.kernel.org/r/[email protected]
2026-03-13configs: phycore_am68x_r5_defconfig: Add ESM and AVS configsDominik Haller
Add TPS6287X which provides VDD_CPU_AVS and ESM_K3+ESM_PMIC for the watchdogs. Signed-off-by: Dominik Haller <[email protected]>
2026-03-13doc: board: ti: Add support for config fragment buildsNeha Malcom Francis
Add sections dedicated to explaining how BIST and inline ECC can be enabled via the config fragments. Signed-off-by: Neha Malcom Francis <[email protected]>
2026-03-13arm: dts: k3-am68-r5-phycore-som: Add PMIC ESM nodeDominik Haller
Add the PMIC ESM node which is responsible for triggering the PMIC reset. Signed-off-by: Dominik Haller <[email protected]>
2026-03-13configs: k3_*: Add config fragments for enabling inline ECC and/or BISTNeha Malcom Francis
Add config fragment support for enabling inline ECC and/or BIST on TI K3 supported platforms. Signed-off-by: Neha Malcom Francis <[email protected]>
2026-03-13Merge patch series "Minor fixes for the k3_fuse driver"Tom Rini
Anshul Dalal <[email protected]> says: This series adds some minor *non-critical* fixes to the k3_fuse misc driver in U-Boot. Link: https://lore.kernel.org/r/[email protected]
2026-03-13misc: k3_fuse: Limit writes to 25bit valuesVignesh Raghavendra
K3 OTP bits can only be programmed 25bits at a time. Limit the value accordingly using a 25 bit mask. Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Anshul Dalal <[email protected]>
2026-03-13misc: k3_fuse: Enable fuse Sense supportVignesh Raghavendra
fuse sense is essentially read, map it to fuse read. Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Anshul Dalal <[email protected]>
2026-03-13misc: k3_fuse: Check readback on fuse progVignesh Raghavendra
Error out if readback value doesn't match the programmed value. Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Anshul Dalal <[email protected]>
2026-03-13misc: k3_fuse: Fix printing of error codesVignesh Raghavendra
Use signed int format to print error codes so that its more readable Fixes: ed5f2e5bed91 ("drivers: k3_fuse: Add fuse sub-system func calls") Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Anshul Dalal <[email protected]>
2026-03-13Merge patch series "board: k3: Sync rm-cfg with TIFS v11.02.09 firmware"Tom Rini
Sparsh Kumar <[email protected]> says: This series updates the Resource Management (RM) configuration files for AM62 family devices to align with the TIFS v11.02.09 firmware. Background ---------- With the latest TIFS firmware (v11.02.09), an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x, am62ax, and am62px devices. This series brings the rm-cfg and tifs-rm-cfg files in sync with these firmware changes across both TI reference boards and vendor boards. These changes are backward compatible with older TIFS firmware versions. Additionally, the am62x platform was originally introduced without a tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family. This series addresses that gap and enables tifs-rm-cfg in binman for am625-sk and am62p-sk platforms. Changes ------- TI reference boards (patches 1-4): - Update rm-cfg.yaml for am62x, am62ax, am62px - Sync am62px tifs-rm-cfg.yaml with TIFS firmware template - Add missing tifs-rm-cfg.yaml for am62x - Enable tifs-rm-cfg in binman for am625-sk and am62p-sk Vendor boards (patches 5-9): - beagleplay (am62x-based) - phytec phycore_am62x - toradex verdin-am62 - phytec phycore_am62ax - toradex verdin-am62p with the required interrupt reservation. The tifs-rm-cfg.yaml files cannot be updated without access to the corresponding SysConfig files, as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync. Link: https://lore.kernel.org/r/[email protected]
2026-03-13board: toradex: verdin-am62p: rm-cfg: Update rm-cfg to reflect new resource ↵Sparsh Kumar
reservation With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62px devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13board: phytec: phycore_am62ax: rm-cfg: Update rm-cfg to reflect new resource ↵Sparsh Kumar
reservation With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62ax devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13toradex: verdin-am62: rm-cfg: Update rm-cfg to reflect new resource reservationSparsh Kumar
With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13board: phytec: rm-cfg: Update rm-cfg to reflect new resource reservationSparsh Kumar
With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13board: beagle: beagleplay: rm-cfg: Update rm-cfg to reflect new resource ↵Sparsh Kumar
reservation With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13arm: dts: k3: am62x/am62px: Enable tifs-rm-cfg in binmanSparsh Kumar
Add rcfg_yaml_tifs node override to use tifs-rm-cfg.yaml instead of the default rm-cfg.yaml for am625-sk and am62p-sk platforms. This enables binman to include the tifs-rm-cfg.yaml configuration when building tiboot3 images, bringing these platforms in line with other K3 devices like am62a-sk that already use tifs-rm-cfg.yaml. This builds on the tifs-rm-cfg files added/updated earlier in this series. Signed-off-by: Sparsh Kumar <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
2026-03-13board: ti: am62x: tifs-rm-cfg: Add the missing tifs-rm-cfg:Sparsh Kumar
The am62x platform was originally introduced without a tifs-rm-cfg.yaml file. Add the tifs-rm-cfg to bring am62x in line with other am62 family of devices (am62px and am62a) which all include this file. This complements the rm-cfg update earlier in this series. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13board: ti: am62px: tifs-rm-cfg: Sync tifs-rm-cfg with TIFS firmware updatesSparsh Kumar
Synchronize tifs-rm-cfg file with the latest v11.02.09 TIFS firmware rm configuration: - Update am62px tifs-rm-cfg with revised resource allocations - Apply formatting updates to align with TIFS template This brings tifs-rm-cfg in sync with the rm-cfg changes earlier in this series. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13board: ti: rm-cfg: Update rm-cfg to reflect new resource reservationSparsh Kumar
With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x, am62ax and am62px devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <[email protected]>
2026-03-13arm: dts: sc594: Update sc594 EZKIT GPIO polaritiesCaleb Ethridge
Updates the polarities for the GPIOs on the sc594 EZKIT carrier board for the newest revision, Rev D. The new carrier board revision has different polarities for some GPIOs. This patch updates the sc594 entries to match the sc598 entries that were updated in a previous commit, as both SOMs can utilize the EZKIT. Note that these updates are for the EZKIT carrier board used by both sc598 and sc594 SOMs, not the SOMs themselves. Fixes: be79378 ("board: adi: Add support for SC594") Signed-off-by: Caleb Ethridge <[email protected]> Reviewed-by: Greg Malysa <[email protected]>
2026-03-13linux_compat: fix NULL pointer dereference in get_mem()Anton Moryakov
Add NULL check after memalign() call in get_mem() to prevent potential NULL pointer dereference (CWE-476). The function memalign() can return NULL on allocation failure. Dereferencing the returned pointer without checking for NULL may cause a crash in low-memory conditions. Changes: - Add NULL check after memalign() allocation - Return NULL on failure, consistent with function semantics This fixes the static analyzer warning: linux_compat.c:34: dereference of memalign return value without NULL check Reported-by: static analyzer Svace Signed-off-by: Anton Moryakov <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2026-03-13serial: ns16550: Fix return-type warningNikita Shubin
Fix compiler warning: drivers/serial/ns16550.c: In function ‘serial_in_dynamic’: drivers/serial/ns16550.c:153:1: warning: control reaches end of non-void function [-Wreturn-type] 153 | } | ^ Observed with gcc 15.2.1: $ riscv64-unknown-linux-gnu-gcc --version riscv64-unknown-linux-gnu-gcc (Gentoo 15.2.1_p20260214 p5) 15.2.1 Fixes: 62cbde4c4e46 ("serial: ns16550: Support run-time configuration") Signed-off-by: Nikita Shubin <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2026-03-13arm: dts: k3-j721s2*: Enable OSPI1 with 32-bit address mappings for R5 SPLAnurag Dutta
The R5 SPL requires 32-bit address mappings for OSPI1(QSPI) access. Override the OSPI1 node with appropriate 32-bit register ranges to enable proper address translation on the 32-bit R5 core, while preserving 64-bit mappings for A72 cores. While at it, remove the disabled status override for ospi1 node to support booting from qspi. Signed-off-by: Anurag Dutta <[email protected]>
2026-03-13spl: Remake SPL elf from binMichal Simek
On Xilinx MB-V there is a need to use ELF file for SPL which is placed in BRAM (Block RAM) because tools for placing code to bitstream requires to use ELF. That's why introduce SPL_REMAKE_ELF similar to REMAKE_ELF option as was originally done by commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after relocate-rela"). There is already generic and simple linker script (arch/u-boot-elf.lds) which can be also used without any modification. Signed-off-by: Michal Simek <[email protected]>
2026-03-13sandbox: symbol CONFIG_DM_SOUND does not existHeinrich Schuchardt
The correct configuration symbol is CONFIG_SOUND. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2026-03-13spl: spi: fix loss of spl_load() error on soft resetDimitrios Siganos
When CONFIG_SPI_FLASH_SOFT_RESET is enabled, spi_nor_remove() is called after spl_load() to switch the flash back to legacy SPI mode. However, the return value of spi_nor_remove() unconditionally overwrites the return value of spl_load(), discarding any load error. Fix this by preserving the spl_load() error and only propagating the spi_nor_remove() error as a fallback. Also log a message when spi_nor_remove() fails, since in the case where spl_load() already failed its error would otherwise be silently discarded. Signed-off-by: Dimitrios Siganos <[email protected]>
2026-03-13lmb: Reinstate access to memory above ram_topMarek Vasut
Revert commit eb052cbb896f ("lmb: add and reserve memory above ram_top") and commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank"). These are based on incorrect premise of the first commit, that "U-Boot does not use memory above ram_top". While U-Boot itself indeed does not and should not use memory above ram_top, user can perfectly well use that memory from the U-Boot shell, for example to load content in there. Currently, attempt to use that memory to load large image using TFTP ends with "TFTP error: trying to overwrite reserved memory...". With this change in place, the memory can be used again. Fixes: eb052cbb896f ("lmb: add and reserve memory above ram_top") Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Reported-by: Yuya Hamamachi <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2026-03-13Merge tag 'u-boot-ufs-20260313' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ufs into next - ufs_hba_ops callbacks cleanup - Rockchip UFS reset support - UFS support in SPL
2026-03-13Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini
into next CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/29497 - sifive: switch to OF_UPSTREAM - driver: cache: Remove SiFive PL2 driver - riscv: fixes for non-existent CONFIG
2026-03-13Merge tag 'net-20260312' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-net into next Pull request net-20260312. net: - Move network PHY under NETDEVICES - s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO} - Add support for Airoha AN8811HB PHY - airoha: PCS and MDIO support for Airoha AN7581 SoC net-lwip: - Fix issue when TFTP blocksize is >8192 - Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and resource usage. - Enable mii command for NET_LWIP
2026-03-13net: Move network PHY under NETDEVICESTom Rini
A number of network PHY drivers have Kconfig dependencies on various network drivers under NETDEVICES. This is in addition to logical dependencies of network PHYs needing network drivers. Resolve the Kconfig problems by moving the network PHY lines to be after the network devices, within the overall NETDEVICES guard. Signed-off-by: Tom Rini <[email protected]> Acked-by: Jerome Forissier <[email protected]>
2026-03-13net: lwip: scale buffer pool size with TFTP block sizePranav Tilak
TFTP transfers fail when tftpblocksize is set to 8192 or larger due to insufficient buffer resources for IP fragment reassembly. Calculate PBUF_POOL_SIZE and IP_REASS_MAX_PBUFS dynamically based on CONFIG_TFTP_BLOCKSIZE using IP fragmentation boundaries (1480 usable bytes per fragment at 1500 MTU). The pool size includes headroom for TX, ARP, and protocol overhead, while ensuring PBUF_POOL_SIZE remains greater than IP_REASS_MAX_PBUFS as required by lwIP. Signed-off-by: Pranav Tilak <[email protected]>
2026-03-13net: lwip: Fix PBUF_POOL_BUFSIZE when PROT_TCP_LWIP is disabledJonas Karlman
The PBUF_POOL_BUFSIZE ends up being only 592 bytes, instead of 1514, when PROT_TCP_LWIP Kconfig option is disabled. This results in a full Ethernet frame requiring three PBUFs instead of just one. This happens because the PBUF_POOL_BUFSIZE constant depends on the value of a TCP_MSS constant, something that defaults to 536 when PROT_TCP_LWIP is disabled. PBUF_POOL_BUFSIZE = LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_HLEN) Ensure that a full Ethernet frame fits inside a single PBUF by moving the define of TCP_MSS outside the PROT_TCP_LWIP ifdef block. Fixes: 1c41a7afaa15 ("net: lwip: build lwIP") Acked-by: Jerome Forissier <[email protected]> Signed-off-by: Jonas Karlman <[email protected]>