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No functions except reserving gd in the board files. The files are
useless, remove them.
Signed-off-by: Peng Fan <[email protected]>
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This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.
Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.
start=00000000, end=00001000, type=16
start=00001000, end=000a0000, type=1
start=000a0000, end=000f6000, type=2
start=000f6000, end=000f7000, type=16
start=000f7000, end=00100000, type=2
start=00100000, end=6f170000, type=1
start=6f170000, end=70000000, type=16
start=70000000, end=80800000, type=2
start=e0000000, end=f8000000, type=2
start=fa000000, end=fc000000, type=2
start=fc800000, end=fc880000, type=2
start=fd800000, end=fe800000, type=2
start=feb00000, end=feb80000, type=2
start=fec00000, end=fed00000, type=2
start=fed20000, end=fed80000, type=2
start=feda1000, end=feda2000, type=2
start=fedc0000, end=fede0000, type=2
start=100000000, end=102400000, type=2
start=102400000, end=47f800000, type=1
start=4000000000, end=4020000000, type=2
By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.
Signed-off-by: Jeremy Compostella <[email protected]>
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Since commit 27cc5951c862 ("include: env: ti: add default for
do_main_cpsw0_qsgmii_phyinit"), the value of the environment variable
do_main_cpsw0_qsgmii_phyinit happened to remain '0' and couldn't be
changed without user intervention. This behavior is due to the following
cyclic dependency:
A) ti_common.env sets do_main_cpsw0_qsgmii_phyinit to '0' and its value
can only be updated automatically by main_cpsw0_qsgmii_phyinit.
B) main_cpsw0_qsgmii_phyinit is defined in j721e.env and it can run only
if 'do_main_cpsw0_qsgmii_phyinit' is already '1' which isn't possible
unless the user manually assigns the value.
Fix the aforementioned cyclic dependency by using board_late_init() to
detect the QSGMII Daughtercard and set do_main_cpsw0_qsgmii_phyinit.
Additionally, to address the issue of do_main_cpsw0_qsgmii_phyinit being
'undefined' for other platforms, replace:
if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
with:
if env exists do_main_cpsw0_qsgmii_phyinit;
in ti_common.env.
Fixes: 27cc5951c862 ("include: env: ti: add default for do_main_cpsw0_qsgmii_phyinit")
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Anshul Dalal <[email protected]>
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Fix a segmentation fault caused by a null pointer access during root
partition checking. The function part_get_info() was falsely given null
for the disk_partition struct, which later resulted in accessing a null
pointer and thus undefined behavior.
Fixes: 5d7c080ae5dc ("bootstd: rauc: Don't check root part filesystem")
Signed-off-by: Martin Schwan <[email protected]>
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Add missing "to" so that the sentence makes sense.
Signed-off-by: Hugo Villeneuve <[email protected]>
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libfdt expects FDT/DTO blobs to be 8-byte aligned. When loading the
base FDT or overlays from a FIT, the mapped buffer may be unaligned,
which can break fdt_open_into() on strict-alignment architectures.
boot_get_fdt_fit() relocates the base FDT with boot_relocate_fdt()
before applying overlays. That uses the bootm memory map and can
overlap with the FIT buffer when the FIT is loaded into RAM,
corrupting data needed to load the kernel and ramdisk.
Allocate writable, 8-byte aligned copies of the base FDT and overlays
with memalign() and fdt_open_into(). Grow the base buffer as needed,
apply overlays to it and pack the final tree. Free each temporary
overlay copy after application and check fdt_pack() errors.
Fixes: 8fbcc0e0e839 ("boot: Assure FDT is always 8-byte aligned")
Fixes: 881f0b77dc8c ("image: apply FDTOs on FDT image node")
Signed-off-by: James Hilliard <[email protected]>
Cc: Jamie Gibbons <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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It has been a long while since Jagan Teki, Joe Hershberger or Ramon
Fried have been active in the community. We thank them for their time
over the years. Remove them from the active maintainer list and mark a
few things as Orphaned for now.
Signed-off-by: Tom Rini <[email protected]>
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Fix a typo in the docstring for run_build() where source_dir was
misspelled.
Signed-off-by: David Lechner <[email protected]>
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- A fix for CDNS3 in correctly determining dr_mode for OTG.
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https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx/FPGA changes for v2026.07-rc1
gpio:
- Add gpio delay driver
zynqmp:
- Wire gpio usb delay
- Enable SPL pinctrl per pin
xilinx:
- Enable NFS support
versal2:
- Extend DDR initialization
zynqmp-rtc:
- Use clock framework for calibration value
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https://source.denx.de/u-boot/custodians/u-boot-tpm into next
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/29283
An update on AB subsystem allowing multiple FWU metadata
storage drivers to be selected simultaneously instead of
being mutually exclusive. The board can then select the
appropriate driver at runtime based on the devicetree
description.
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The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.
To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
the Controller should assume the Host role.
Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-04-rc3
CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/29293
UEFI:
* add missing EFI_CALL around tcg2 read_blocks calls
* fix ECPT table size computation
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https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request efi-next-2026-02-15
CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/jobs/1380382
UEFI:
* Add MBR support to EFI_PARTITION_INFO_PROTOCOL
* disk: part_dos: Move header to the main include directory
* disk: part_dos: Align dos_partition_t with struct partition
* disk: part_efi: Remove redundant struct partition definition
* disk: part_dos: Document part_get_info_extended() helper function
* disk: part_dos: Refactor to allow retrieving raw MBR partition data
* efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL to support MBR
* efi_selftest: Enhance MBR test for PARTITION_INFO_PROTOCOL
* Prepare for supporting more stores (e.g. SPI-flash) for EFI variables.
* efi_var: Unify read/write access helper function
* efi_loader: Setup default location for UEFI Variables storing
* efi_var_file: refactor to move buffer functions
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EFI_VARIABLE_FILE_STORE is only available when FAT_WRITE is enabled but
that's not valid for all platforms and dependency should be covered.
Also Kconfig behavior is that if default option is not valid then Kconfig
selects the first presented valid option instead hence it is better to
record EFI_VARIABLE_NO_STORE as safe default option.
Suggested-by: Tom Rini <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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efi_var_to/from_file() suggest method where variables are placed. But there
is no reason for it and generic name can be used to wire also different
locations for variables.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Tested-by: Neil Armstrong <[email protected]> # on AML-S905D3-CC
Reviewed-by: Heinrich Schuchardt <[email protected]>
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Currently efi_var_file.c has functions to store/read
EFI variables to/from memory buffer. These functions
can be used with other EFI variable stores so move
them out to efi_var_common.c
Signed-off-by: Shantur Rathore <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Tested-by: Neil Armstrong <[email protected]> # on AML-S905D3-CC
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully
supported MBR partitions. As a result, it lacked specific checks for the
content of the raw MBR partition record.
Now that MBR support has been implemented, enhance the selftest to provide
coverage for the MBR entries too.
This verifies that the protocol correctly reads and exposes MBR partition
records and prevents this functionality to regress due future changes.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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The EFI_PARTITION_INFO_PROTOCOL provides detailed information about
partitions. The UEFI specification mentions that both GPT and MBR
partition schemes are supported, but the U-Boot implementation only
supports the former.
This can cause compatibility issues for platforms whose boot ROM only
supports MBR. This change adds support for MBR partition tables to
the protocol, making U-Boot compatible with systems that require a
legacy MBR table.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Refactor the part_get_info_extended() helper function (which already
recursively traverses DOS partitions) to optionally return the raw MBR
partition structure (dos_partition_t).
This allows other subsystems, such as EFI, to retrieve the partition
details in the legacy MBR format.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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The function receives many parameters but these are not documented.
Add a description for these to make it easier to follow what it does.
Suggested-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Now that dos_partition_t and struct partition are identical, the duplicated
data structure definition in the part_efi.h header can just be removed.
This results in a single, shared definition for MBR partition table
entries, instead of having the same definition in two different places.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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The dos_partition_t struct defined in part_dos.h is nearly identical to
the struct partition defined in part_efi.h. They differ primarily in how
define their starting sector and number of sectors fields.
The former uses unsigned char arrays while the latter uses __le32 types.
Using __le32 is preferable, as it removes the ambiguity and potential
misuse of a raw byte array. This also aligns the structure with how the
Linux kernel defines it nowadays, which is the original source of it.
To prepare for future consolidation where one of the data structures can
be removed, this change aligns both definitions and updates all accessors
for dos_partition_t.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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There are two different struct definitions for MBR partition table
entries: one in part_dos.h and a nearly identical one in part_efi.h.
To enable future consolidation of these two structures, move part_dos.h
to the main include directory. This makes it accessible from other parts
of the codebase, such as part_efi.h, and is the first step toward removing
the redundant definition.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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The size of the memory allocated for the EFI Conformance Profiles Table is
computed with `num_entries' always equal to zero, which is incorrect when
CONFIG_EFI_EBBR_2_1_CONFORMANCE is enabled.
This can be verified by allocating the ECPT memory with malloc() instead of
efi_allocate_pool(), building u-boot with sandbox_defconfig and
CONFIG_VALGRIND=y, and by finally running the following command:
valgrind --suppressions=scripts/u-boot.supp \
./u-boot -T -c 'efidebug tables'
Fix this by using an array of the supported profiles GUIDs instead, which
should also be easier to extend in the future as U-Boot should publish the
GUIDs for all supported EBBR revisions.
Fixes: 6b92c1735205 ("efi: Create ECPT table")
Suggested-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Vincent Stehlé <[email protected]>
Cc: Ilias Apalodimas <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Jose Marinho <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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The read_blocks() function from the Block IO protocol is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.
To demonstrate the issue on an AArch64 machine, define the DEBUG macro in
include/efi_loader.h and build u-boot with sandbox_defconfig, then download
and uncompress the ACS-DT image [1], and finally execute the following
command:
$ ./u-boot -T -c " \
host bind 0 systemready-dt_acs_live_image.wic; \
setenv loadaddr 0x10000; \
load host 0 \${loadaddr} EFI/BOOT/Shell.efi; \
bootefi \${loadaddr} \${fdtcontroladdr}"
The following assertion should fail:
lib/efi_loader/efi_net.c:858: efi_network_timer_notify: Assertion `__efi_entry_check()' failed.
This happens due to the following EFIAPI functions call chain:
efi_start_image()
efi_disk_read_blocks()
(due to the missing EFI_CALL, entry_count == 2)
efi_network_timer_notify()
Link: https://github.com/ARM-software/arm-systemready/releases/download/v25.12_DT_3.1.1/systemready-dt_acs_live_image.wic.xz [1]
Fixes: ce3dbc5d080d ("efi_loader: add UEFI GPT measurement")
Signed-off-by: Vincent Stehlé <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
Cc: Ilias Apalodimas <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Masahisa Kojima <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Acked-by: Masahisa Kojima <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.
DDR and memory handling
* Add DRAM size checking support for Arria10.
* Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
* Assign unit address to memory node for improved memory
representation and consistency.
Agilex / Agilex5 updates
* Restore multi-DTB support for NAND boot and fix NAND clock handling.
* Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
* Fix DT property naming conventions for Agilex5.
* Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
to avoid unintended clock control.
New board support
* Add support for CoreCourse Cyclone V boards:
* AC501
* AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.
Fixes and cleanup
* Fix GEN5 handoff script path.
* Remove incorrect CONFIG_SPL_LDSCRIPT settings.
* Replace legacy TARGET namespace and perform related cleanup across
SoCFPGA code.
* General Kconfig, build and SoCFPGA maintenance updates.
Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.
[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <[email protected]>
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Add a test when delay is set to 0 to improve performances
by 20% on ARM based systems
Signed-off-by: Jean-Marie Verdun <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
# Conflicts:
# drivers/ddr/altera/Makefile
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CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC550 C5 to mainstream u-boot
This is a more complex and unified board with
feature. More info on [1]
[1] https://corecourse.cn/forum.php?mod=viewthread&tid=29788&extra=page%3D1
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC501 C5 to mainstream u-boot
This is a UBGA-484 based board with basic
feature. More info on [1]
[1] https://corecourse.cn/forum.php?mod=viewthread&tid=27704&highlight=AC501
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable high-speed eMMC modes on Agilex5 SoC development kit for
improved storage performance.
Defconfig changes:
- Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT
Device tree changes:
- Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
- Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
- Add sdhci-caps to set 200MHz base clock and 8-bit bus width
- Add PHY and controller timing configuration for HS200 mode
- Add PHY and controller timing configuration for HS400 mode
Signed-off-by: Tanmay Kathpalia <[email protected]>
Acked-by: Tien Fong Chee <[email protected]>
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Enable Ultra High Speed (UHS-I) mode support for SD cards on
Agilex5 SoC development kit.
Defconfig changes:
- Enable CONFIG_MMC_UHS_SUPPORT and CONFIG_SPL_MMC_UHS_SUPPORT
Device tree changes:
- Remove no-1-8-v to allow 1.8V signaling for UHS modes
- Add sd-uhs-sdr50 and sd-uhs-sdr104 capabilities
- Add sdhci-caps and sdhci-caps-mask for proper capability reporting
- Add PHY and controller timing configuration
Signed-off-by: Tanmay Kathpalia <[email protected]>
Acked-by: Tien Fong Chee <[email protected]>
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Replace underscores with hyphens in the PHY timing configuration
property names to follow standard devicetree naming conventions:
- phy-gate-lpbk_ctrl-delay-sd-ds -> phy-gate-lpbk-ctrl-delay-sd-ds
- phy-gate-lpbk_ctrl-delay-sd-hs -> phy-gate-lpbk-ctrl-delay-sd-hs
Signed-off-by: Tanmay Kathpalia <[email protected]>
Acked-by: Tien Fong Chee <[email protected]> Best regards, Tien
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src variables not longer defined, fixed by srctree
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]> Best regards,
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The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits,
which could truncate DDR size values on larger-memory systems.
Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent
the full capacity field according to the hardware specification.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Signed-off-by: Chen Huei Lok <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]> Best regards,
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operations
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Assign unit address of 0 to memory node following latest Linux convention.
Without this unit address, SPL will not be able to retrieve proper memory
node values set from the device tree.
Update all dts files which includes the common .dtsi to add unit address
as well.
Fixes: e291277689f6 ("sync socfpga common u-boot dts")
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]> Best regards,
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In v2025.10, the Agilex clock driver was updated to support
clk_enable() and clk_disable() using clock-ID based bitmasks.
However, only AGILEX_NAND_CLK was implemented, while the NAND DT
node still referenced both nand and nand_x clocks.
Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
clock-ID specification, clk_enable() failed during NAND probe.
As a result, the Denali NAND controller never completed
initialization.
Fix this by mapping the NAND X clock to the existing l4_mp clock
bitmask, aligning the DT expectations with the clock driver and
restoring proper NAND controller initialization.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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These platforms set CONFIG_SPL_LDSCRIPT to a file that doesn't exist,
and in turn were using the default of arch/arm/cpu/armv8/u-boot-spl.lds
instead.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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From v2025.10 onward, Agilex platforms use the upstream Linux device
tree sources instead of local copies.
To continue using a single defconfig while supporting NAND boot,
restore Multi-DTB support and update the DT paths to the upstream
intel directory.
NAND boot is configured to use FDT-1, while other boot flows
continue to use the default device tree.
No functional change is intended for non-NAND boot paths.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.
When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.
Commit 13c54cf588d82 and 0c3a6f748c9 add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.
To fix this, do the following:
* Implement `spl_perform_board_fixups()` function for verdin-am62
and verdin-am62p. Make this function call `fixup_memory_node()`,
which updates the DT.
* Add an if-block in `dram_init()`, to ensure that only R5 is able
to call `get_ram_size()`, and that A53 reads this size from the
DT.
Signed-off-by: Suhaas Joshi <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
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In theory, for the same vendor, we should use the same instructions as
the spi-nor-core implementation.
Fixes: 72151ad10f8d ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte")
Fixes: 5bf3f3dd11db ("mtd: spi-nor: Enable QE bit for ISSI flash")
Signed-off-by: Shiji Yang <[email protected]>
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These chips are internally made of two/four dies with linear addressing
capabilities to make it transparent to the user that two/four dies were
used. There is one drawback however, the read status operation is racy
as the status bit only gives the active die status and not the status of
the other die. For commands affecting the two dies, it means if another
command is sent too fast after the first die has returned a valid
status (deviation can be up to 200us), the chip will get corrupted/in an
unstable state.
The solution adopted here is to iterate manually over all internal
dies (which takes about 30us per die) until all are ready. This approach
will always be faster than a blind delay which represents the maximum
deviation, while also being totally safe.
A flash-specific hook for the status register read had to be
implemented. Testing with the flash_speed benchmark in Linux shown no
difference with the existing performances (using the regular status read
core function).
As the presence of multiple dies is not filled in these chips SFDP
tables (the table containing the crucial information is optional), we
need to manually wire the hook.
This change is adapted from Linux.
Link: https://lore.kernel.org/all/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com/
Signed-off-by: Miquel Raynal <[email protected]>
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Invert the conditional when to exit, and fall back to common code
in the default case. This should have no functional impact on either
code path.
Signed-off-by: Marek Vasut <[email protected]>
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The spi_slave_of_to_plat() is called from one place, spi_child_post_bind().
Squash it into the later and remove the public declaration, make this
function local static. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Some Winbond Flash chips share the same device ID. Names are not that
important for the SPI Flash, hence we don't need these duplicate ID
definitions. And the Flash size of w25q512jv is actually wrong. Clean
them up to keep the source file tidy.
Signed-off-by: Shiji Yang <[email protected]>
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Change the Kconfig from a "choice" to a conditional block, allowing
multiple FWU metadata storage drivers to be selected simultaneously
instead of being mutually exclusive.
This enables systems with FWU metadata on different storage types
(e.g., both GPT-partitioned block devices and MTD devices) to have
both drivers compiled in. The board can then select the appropriate
driver at runtime based on the devicetree description.
The change converts FWU_MDATA to a menuconfig and replaces the
"choice/endchoice" block with "if FWU_MDATA/endif", making
FWU_MDATA_GPT_BLK default to 'y' for backward compatibility.
Signed-off-by: Kory Maincent <[email protected]>
Acked-by: Sughosh Ganu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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USB hub requires longer delay to get out of the reset to work properly
that's why use gpio-delay to ensure enough waiting time.
Reviewed-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e206e3ab2ad266935b81f5e9d3af2ed47b866826.1770105146.git.michal.simek@amd.com
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