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2025-04-22MIPS: Provide dummy acpi_table.hJiaxun Yang
Some drivers need this header. Provide this dummy header as riscv did. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Daniel Schwierzeck <[email protected]>
2025-04-22ahci: dwc_ahsata: Generalize the driverJiaxun Yang
Remove hard dependencies to arch headers, get clock from clk subsystem if arch clock function is not available, align compatible strings with devicetree binding. No functional change on existing platforms, just get it build on other platforms. Signed-off-by: Jiaxun Yang <[email protected]>
2025-04-22ahci: DMA addressing fixesJiaxun Yang
Ensure that we are using correct physical/virtual address for DMA buffer write and hardware register settings. The convention is: in ahci_ioports all pointers are virtual, that will be converted to physical address when writing to hardware registers or into sg/cmd_tbl. Also fixed 64bit physical address support for dwc_ahsata, ensure higher bits are written into registers/sg properly. Use memalign for allocating aligned buffer in dwc_ahsata so we don't have to do our own alignment in driver. Signed-off-by: Jiaxun Yang <[email protected]>
2025-04-22pci: Enable PCI_MAP_SYSTEM_MEMORY when ARCH_MAP_SYSMEM is not setJiaxun Yang
For MIPS we are always looking gd->dram in virtual address so PCI_MAP_SYSTEM_MEMORY should always be enabled. If in future we ever want to make it physical we have to set ARCH_MAP_SYSMEM. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Daniel Schwierzeck <[email protected]>
2025-04-22pci: auto: Reduce bridge mem alignment boundary for bostonJiaxun Yang
Boston has a very limited memory range for PCI controllers, where 1MB can't easily fit into it. Make alignment boundary of PCI memory resource allocation a Kconfig option and default to 0x10000 for boston. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Daniel Schwierzeck <[email protected]>
2025-04-22pci: xilinx: Handle size of ecam region properlyJiaxun Yang
Probe size of ecam from devicetree properly and cap accessible bus number accorading to ecam region size to ensure we don't go beyond hardware address space. Also disable all interrupts to ensure errors are handled silently. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Daniel Schwierzeck <[email protected]>
2025-04-22Merge patch series "configs: ACPI enabled QEMU defconfigs"Tom Rini
Heinrich Schuchardt <[email protected]> says: For QEMU we have developed supporting passsing through ACPI tables. This functionality has been broken multipled times due to missing CI builds. * Two new defconfigs qemu_arm64_acpi and qemu-riscv64_smode_acpi. * Assign the defconfigs to the respective maintainers. Link: https://lore.kernel.org/r/[email protected]
2025-04-22Merge patch series "Enable UNIT_TEST for all qemu* generic targets"Tom Rini
Jerome Forissier <[email protected]> says: Enable CONFIG_UNIT_TEST in most of the configs/qemu*_defconfig files to increase test coverage in CI, and fix what needs to be fixed. Link: https://lore.kernel.org/r/[email protected]
2025-04-22Merge patch series "ut: fix print_guid() and enable UNIT_TEST for qemu_arm64"Tom Rini
Jerome Forissier <[email protected]> says: There is a bug in the print_guid() unit test in test/common/print.c when PARTITION_TYPE_GUID is not enabled but either CMD_EFIDEBUG or EFI are. The first patch fixes the issue and the second one enables UNIT_TEST in the qemu_arm64 defconfig so that the unit tests are run in CI (this platform has CMD_EFIDEBUG so the bug applies). Link: https://lore.kernel.org/r/[email protected]
2025-04-22qemu-arm64: enable UNIT_TESTJerome Forissier
Enable CONFIG_UNIT_TEST in configs/qemu_arm64_defconfig so that the unit tests are run in CI. Signed-off-by: Jerome Forissier <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]>
2025-04-22lib/uuid.c: use unique name for PARTITION_SYSTEM_GUIDJerome Forissier
The name defined for PARTITION_SYSTEM_GUID in list_guid[] depends on configuration options. It is "system" if CONFIG_PARTITION_TYPE_GUID is enabled or "System Partition" if CONFIG_CMD_EFIDEBUG or CONFIG_EFI are enabled. In addition, the unit test in test/common/print.c is incorrect because it expects only "system" (or a hex GUID). Make things more consistent by using a clear and unique name: "EFI System Partition" whatever the configuration, and update the unit test accordingly. Signed-off-by: Jerome Forissier <[email protected]> Suggested-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Ilias Apalodimas <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]>
2025-04-22MAINTAINERS: add qemu-riscv* defconfigs to QEMU RISC-V 'VIRT' BOARDHeinrich Schuchardt
Add the follow board to VIRT which otherwise would be unmaintained: * qemu-riscv64_smode_acpi_defconfig Signed-off-by: Heinrich Schuchardt <[email protected]>
2025-04-22configs: add qemu-riscv64_smode_acpi_defconfigHeinrich Schuchardt
Add a configuration that supports ACPI. Signed-off-by: Heinrich Schuchardt <[email protected]>
2025-04-22MAINTAINERS: add all qemu_arm64* defconfigs to VIRTHeinrich Schuchardt
Add the following boards to VIRT which otherwise would be unmaintained. * qemu_arm64_acpi_defconfig * qemu_arm64_lwip_defconfig Signed-off-by: Heinrich Schuchardt <[email protected]>
2025-04-22configs: add qemu_arm64_acpi_defconfigHeinrich Schuchardt
Add a qemu_arm64 variant that supports ACPI. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2025-04-22configs: enable CONFIG_UNIT_TEST for all qemu* generic targetsJerome Forissier
The qemu* "generic" targets (i.e. not those emulating a particular board) are typically used for testing as many features as possible, especially in CI so it makes sense to have UNIT_TEST enabled for all of the defconfigs for these targets. Not enabling UNIT_TEST in qemu-x86_defconfig due to: LD u-boot ld.bfd: section .rel.dyn VMA wraps around address space ld.bfd: section .start16 LMA [fffff800,fffff86f] overlaps section .rel.dyn LMA [ffffb77c,0002ac93] make: *** [Makefile:1824: u-boot] Error 1 Suggested-by: Tom Rini <[email protected]> Signed-off-by: Jerome Forissier <[email protected]>
2025-04-22test: run some test commands only if HUSH_PARSER is enabledJerome Forissier
Some test commands (such as "false", or the empty string) need CONFIG_HUSH_PARSER=y. Fix test/cmd/command.c. Signed-off-by: Jerome Forissier <[email protected]>
2025-04-22Merge tag 'i2cfixes-for-2025.07-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c updates for v2025.07-rc1 - omap24xx_i2c: Enable Repeated Start functionality add Repeated Start functionality for the DM_I2C xfer API (omap_i2c_xfer() from Aniket Limaye - mediatek i2c driver fixes from Martin - add end marker for struct udevice_id mtk_i2c_ids - remove duplicate entry in mt_i2c_regs_v1
2025-04-22Merge tag 'u-boot-socfpga-next-20250422' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga This pull request contains updates for the SoCFPGA platform, targeting the 2025.07 release cycle. Highlights include enhancements to Agilex5 support, improvements in DDR error handling, and bridge reset handling for SoC64 devices. Key updates: Agilex5 platform enhancements: * New MMU region mappings and memory layout updates using LMB_ARCH_MEM_MAP. * Fixes for bloblist configuration, kernel FIT image generation, and VAB flow enablement. * GPIO pin control added for SDIO selection. * Marvell PHY driver enabled in defconfig. Agilex5 / SoC64 DDR subsystem: * Added ECC debug improvements for IOSSM. * Introduced LPDDR inline ECC support. * Resolved size calculation overflow in memory driver. SoC64 improvements: * Enhanced mailbox communication with the SDM to reflect various boot stage transitions. * Implemented F2S bridge reset support and updated related reset manager registers. * Expanded SoC64 CPU info reporting. General maintenance: * Additional peripherals released from reset for Arria10. * Cleanup of legacy or incorrect Kconfig implications. This patch set has been tested on Agilex 5 devkit. Passing all pipeline tests at: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/25867
2025-04-22i2c: mediatek: remove duplicate entry in mt_i2c_regs_v1[]Martin Schiller
This removes a duplicate entry in mt_i2c_regs_v1[]. Signed-off-by: Martin Schiller <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22i2c: mediatek: add missing empty entry at end of mkt_i2c_ids[]Martin Schiller
This adds the missing empty entry at the end of mtk_i2c_ids[]. Signed-off-by: Martin Schiller <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22drivers: i2c: Kconfig: Add CONFIG_SYS_I2C_OMAP24XX_REPEATED_STARTAniket Limaye
Add a Kconfig option to disable sending Stop conditions between multiple i2c_msgs within a single xfer. Enable this config by default for ARCH_K3 platforms. Signed-off-by: Aniket Limaye <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22i2c: omap24xx_i2c: support CONFIG for repeated start in DM_I2C xferAniket Limaye
Repeated Start Condition (Sr) can be used to transfer multiple i2c msgs without sending a Stop condition (P). So far, the driver default was to always send a Stop condition after every i2c msg. Add support for a config option (CONFIG_SYS_I2C_OMAP24XX_REPEATED_START) to disable sending the Stop condition by default. If this config is enabled, Stop condition will be sent only if explicitly requested in the msg flags OR if it is the last msg in the transfer. Consequently, handle the Repeated Start condition (Sr) in the next msg by not calling the wait_for_bb() check since it will simply timeout in the absence of a stop condition (BB will be 1 until Stop is programmed) Signed-off-by: Aniket Limaye <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22i2c: omap24xx_i2c: Use new function __omap24_i2c_xfer_msg()Aniket Limaye
Remove __omap24_i2c_read/write() usage from omap_i2c_xfer() in favour of the more flexible __omap24_i2c_xfer_msg(). Consequently, these are also no longer needed when DM_I2C is enabled. New function __omap24_i2c_xfer_msg() will take care of individual read OR write transfers with a target device. It goes through below sequence: - Program the provided Target Chip address (OMAP_I2C_SA_REG) - Program the provided Data len (OMAP_I2C_CNT_REG) - Program the provided Control register flags (OMAP_I2C_CON_REG) - Read from or Write to the provided Data buffer (OMAP_I2C_DATA_REG) For a detailed programming guide, refer to the TRM[0] (12.1.3.4 I2C Programming Guide). This patch by itself should be a transparent change. However this is needed for implementing a proper Repeated Start (Sr) functionality for i2c_msgs. Previous implementation for omap_i2c_xfer called __omap24_i2c_read/write functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of these calls would program the registers always with a Stop bit set, not allowing for a repeated start between i2c_msgs in the same xfer(). [0]: https://www.ti.com/lit/zip/spruj28 (TRM) Signed-off-by: Aniket Limaye <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22i2c: omap24xx_i2c: Remove unused CONFIG_I2C_REPEATED_STARTAniket Limaye
Remove unused piece of code under CONFIG_I2C_REPEATED_START which does not have any Kconfig entry at all. Signed-off-by: Aniket Limaye <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2025-04-22ddr: altera: iossm: Enhance debug information for ECC errorsTingting Meng
ECC debug information was enhanced to improve the readability of error messages. Signed-off-by: Tingting Meng <[email protected]>
2025-04-22ddr: altera: agilex5: LPDDRs in-line ECC supportTingting Meng
In-line ECC support was added for LPDDR by reserving the last one-eighth of the memory space for ECC data. Full memory initialization using the BIST MEM INIT mailbox command, based on address and size, is required to correctly generate ECC data and enable proper ECC logic verification. Signed-off-by: Tingting Meng <[email protected]>
2025-04-22arm: dts: agilex5: Update CCU configurationTingting Meng
Cache allocation for dirty writes in the CCU system cache was disabled for performance optimization. Signed-off-by: Tingting Meng <[email protected]>
2025-04-22arm: socfpga: socfpga_soc64: Enable LMB_ARCH_MEM_MAPTingting Meng
LMB_ARCH_MEM_MAP is enabled, and lmb_arch_add_memory() is introduced to correctly handle memory reservations for the second and third DDR memory banks. Signed-off-by: Tingting Meng <[email protected]>
2025-04-22arm: socfpga: agilex5: Add MMU mapping regionTingting Meng
MMU mapping regions were added for the second and third DDR memory banks. Signed-off-by: Tingting Meng <[email protected]>
2025-04-22arm: socfpga: soc64: Update SoC64 CPU infoAlif Zakuan Yuslaimi
As of 2025, Altera is now a standalone company prior to being a subsidiary of Intel Corporation. Update CPU info printout naming from Intel to Altera. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
2025-04-22arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as outputAlif Zakuan Yuslaimi
Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3) direction as output with value 0 after power-on reset. This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin after board init. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22configs: agilex5: Restore fixed bloblistTingting Meng
CONFIG_BLOBLIST_FIXED and CONFIG_BLOBLIST_ADDR options were unintentionally removed during recent external updates to the defconfig. This patch restores the missing entries to ensure proper board functionality. No new features are introduced. Fixes: d6a53f523afe ("spl: Add an SPL_HAVE_INIT_STACK option") Signed-off-by: Tingting Meng <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22ARM: socfpga: Drop incorrect imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION*Tom Rini
The use of both "imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION" and "imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE" here is wrong as those are both part of the same choice statement. Furthermore you cannot select/imply something from a choice statement, it must be a "default ... if ..." construct within the choice statement in question. Signed-off-by: Tom Rini <[email protected]>
2025-04-22configs: Enable VAB flow for Agilex5 SoCFPGA boardsNaresh Kumar Ravulapalli
Vendor Authorized Boot flow configurations are enabled for boards based on Agilex5 SoCFPGA. Also, required changes are made to the SoCFPGA make file for building and linking relevant secure source code files. Signed-off-by: Naresh Kumar Ravulapalli <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22arch: arm: dts: Enable kernel itb file generation for Agilex5 SoCFPGANaresh Kumar Ravulapalli
Load and entry addresses are corrected for Agilex5 SoCFPGA board which would enable to generate the kernel itb file with the right addresses. Signed-off-by: Naresh Kumar Ravulapalli <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22configs: agilex5: Enable Marvell PHY driverAlif Zakuan Yuslaimi
Enable Marvell Ethernet PHYs support for Agilex5 defconfig Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22arm: socfpga: spl: Notify SDM on FSBL executionAlif Zakuan Yuslaimi
Send out "HPS_STAGE_NOTIFY" mailbox command to the Secure Device Manager (SDM) in SPL to inform SDM on FSBL execution. This is necessary for the SDM to recognize that the FSBL stage has begun its execution and should be made as early as possible in the FSBL process. Therefore, the mailbox will initialize and send out the notification right after the completion of timer initialization. Signed-off-by: Mahesh Rao <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22arm: socfpga: soc64: Enable F2S bridge reset supportAlif Zakuan Yuslaimi
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as FPGA2SoC and SoC2FPGA bridges for all SoC64 families. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22arm: socfpga: soc64: Update reset manager registers for F2S bridgeAlif Zakuan Yuslaimi
Add reset manager registers in preparation for F2S bridge reset support as well as the mask support to enable/disable the bridges. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges are available only in Stratix10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22arm: socfpga: mailbox: Notify SDM on HPS code execution stagesAlif Zakuan Yuslaimi
Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on the stage of HPS code execution. Generally, there are three main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System (OS) which is Linux. This enables the user to query the SDM for HPS error details. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22reset: socfpga: release more A10 peripherals out of resetNaresh Kumar Ravulapalli
Current implementation releases most peripherals out of reset for gen5, but A10 has more peripherals than gen5, hence this patch is required to release the rest of peripherals to support old kernels. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Naresh Kumar Ravulapalli <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-22drivers: ddr: altera: Fix integer overflow during size calculationNaresh Kumar Ravulapalli
Data structure, dramaddrw, is defined as u32. Compiler performs 32-bit arithmetic and logic operations on this data structure. Fix is provided to avoid integer overflow while performing shifting operations greater than 32-bit. Signed-off-by: Naresh Kumar Ravulapalli <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-04-21fs/squashfs: avoid illegal free() in sqfs_opendir()Heinrich Schuchardt
* Use calloc() to allocate token_list. This avoids an illegal free if sqfs_tokenize() fails. * Do not iterate over token_list if it has not been allocated. Addresses-Coverity-ID: 510453: Null pointer dereferences (FORWARD_NULL) Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Joao Marcos Costa <[email protected]> Reviewed-by: Joao Marcos Costa <[email protected]>
2025-04-21Merge patch series "fs: exfat: Flush node before put in read() callback"Tom Rini
This series from Marek Vasut <[email protected]> includes a number of fixes to the exFAT filesystem support that he recently added. Link: https://lore.kernel.org/r/[email protected]
2025-04-21test_fs: Test 'mv' command on exfat and fs_genericMarek Vasut
Enable tests for the generic FS interface 'mv' command against both exfat and fs_generic. Signed-off-by: Marek Vasut <[email protected]>
2025-04-21fs: exfat: Implement trivial 'rename' supportMarek Vasut
Implement exfat_fs_rename() to rename or move files. This is used by the 'mv' generic FS interface command. The rename implementation for other filesystems was added recently and was not part of exfat porting layer due to merge issue, which made 'mv' command crash, fix this by adding the missing implementation. Fixes: b86a651b646c ("fs: exfat: Add U-Boot porting layer") Signed-off-by: Marek Vasut <[email protected]>
2025-04-21test_fs: Add test -e testMarek Vasut
Add test for the 'test -e' command to check for existence of files. This exercises struct fstype_info .exists callback. Signed-off-by: Marek Vasut <[email protected]>
2025-04-21fs: exfat: Fix exfat_fs_exists() return valueMarek Vasut
The exfat_fs_exists() should return 0 in case the path does not exist, and 1 in case the path does exist. Fix the inverted return value. This fixes 'test -e' command with exfat. Fixes: b86a651b646c ("fs: exfat: Add U-Boot porting layer") Signed-off-by: Marek Vasut <[email protected]>
2025-04-21fs: exfat: Rework exfat_fs_readdir() to behave like exfat_fs_ls()Marek Vasut
The exfat_fs_readdir() depends on state created in exfat_fs_opendir(), but that state may be disrupted by fs_close() called by the FS layer in fs_opendir(), because exfat porting layer unmounts the filesystem in ->close() callback. To avoid this disruption, avoid creating state in exfat_fs_opendir(), cache only the directory name to list there, and rework exfat_fs_readdir() to work in a similar way to exfat_fs_ls(). That is, make exfat_fs_readdir() open the directory, look up specific entry, extract its properties to be reported to FS layer, and close the directory. This is slow, but avoids the disruption. The slowness does not affect regular 'ls' command, which uses exfat_fs_ls() fast path. Fixes: b86a651b646c ("fs: exfat: Add U-Boot porting layer") Signed-off-by: Marek Vasut <[email protected]>